Texas Instruments 的 TMP6131-Q1 规格书

规格书反馈/错误

i TEXAS INSTRUMENTS 25 w / VT : M Vremp : ’me * Rmm mp Ram: + Rmm A

TMP61-Q1 Automotive Grade, ±1% 10-kΩ Linear Thermistor With 0402 and 0603

Package Options

1 Features

• Automotive Qualifications

– AEC-Q100 Grade 1: –40 °C to 125 °C

– AEC-Q100 Grade 0 (DYA): –40 °C to 150 °C

– AEC-Q100 Grade 0 (ELPG): –40 °C to 170 °C

• AEC-Q200 Tested

•Functional Safety-Capable

–Documentation available to aid functional safety

system design

• Silicon-based thermistor with a

positive temperature coefficient (PTC)

• Linear resistance change across temperature

• 10-kΩ nominal resistance at 25 °C (R25)

– ±1% maximum (0 °C to 70 °C)

• Consistent sensitivity across temperature

– 6400 ppm/°C TCR (25 °C)

– 0.2% typical TCR tolerance across temperature

range

• Fast thermal response time of 0.6 s (DEC)

• Long lifetime and robust performance

– Built-in fail-safe in case of short-circuit failures

– 0.5% typical long term sensor drift

2 Applications

• Thermal compensation

– Display backlight

– Battery management systems

• Thermal threshold detection

– Motor control

– On-board chargers & DC-DC converters

3 Description

Get started today with the Thermistor Design Tool,

offering complete resistance vs temperature table (R-

T table) computation, other helpful methods to derive

temperature and example C-code.

The TMP61-Q1 linear thermistor offers linearity and

consistent sensitivity across temperature to enable

simple and accurate methods for temperature

conversion. The low power consumption and a small

thermal mass of the device minimize self-heating.

With built-in fail-safe behaviors at high temperatures

and powerful immunity to environmental variation,

these devices are designed for a long lifetime of high

performance. The small size of the TMP6 series also

allows for close placement to heat sources and quick

response times.

Take advantage of benefits over NTC thermistors

such as no extra linearization circuitry, minimized

calibration, less resistance tolerance variation, larger

sensitivity at high temperatures, and simplified

conversion methods to save time and memory.

The The TMP61-Q1 is currently available in a 0402

X1SON package, a 0603 SOT-5X3 package, and a 2-

pin through-hole TO-92S package.

Device Information (1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TMP61-Q1

X1SON (2) 0.60 mm × 1.00 mm

TO-92S (2) 4.00 mm × 3.15 mm

SOT-5X3 (2) 0.80 mm × 1.20 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

RBias

VBias

VTemp

RTMP61 VTemp

RTMP61

IBias

Typical Implementation Circuits

Temperature (qC)

Resistance (k:)

-40 -15 10 35 60 85 110 135 160

61_F

Typical Resistances vs Ambient Temperature

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

I TEXAS INSTRUMENTS

Table of Contents

1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................5

Pin Functions.................................................................... 5

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings .............................................................. 6

7.3 Recommended Operating Conditions ........................6

7.4 Thermal Information ...................................................7

7.5 Electrical Characteristics ............................................8

7.6 Typical Characteristics................................................ 9

8 Detailed Description...................................................... 11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram......................................... 11

8.3 TMP61-Q1 R-T table.................................................12

8.4 Feature Description...................................................12

8.5 Device Functional Modes..........................................12

9 Application and Implementation.................................. 13

9.1 Application Information............................................. 13

9.2 AEC-Q200 Qualifications.......................................... 13

9.3 Typical Application.................................................... 13

10 Power Supply Recommendations..............................19

11 Layout........................................................................... 19

11.1 Layout Guidelines................................................... 19

11.2 Layout Examples ....................................................19

12 Device and Documentation Support..........................20

12.1 Documentation Support.......................................... 20

12.2 Receiving Notification of Documentation Updates..20

12.3 Support Resources................................................. 20

12.4 Trademarks.............................................................20

12.5 Glossary..................................................................20

12.6 Electrostatic Discharge Caution..............................20

13 Mechanical, Packaging, and Orderable

Information.................................................................... 20

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (March 2020) to Revision F (February 2021) Page

• Added AEC-Q200 Tested to Features................................................................................................................ 1

• Added Functional Safety-Capable to Features...................................................................................................1

• Changed DYA to Grade-0...................................................................................................................................1

• Updated Device Comparison Table.................................................................................................................... 4

• Increased Maximum Storage Temperature in Absolute Maximum Ratings Table to 175 °C.............................. 6

• Changed Max Ambient Temperature from 125 °C to 150 °C for DYA package in Recommended Operating

Conditions ..........................................................................................................................................................6

• Changed DYA package to Grade-0 150 C rating in Recommended Operating Conditions ...............................6

• Added HTOL and HTSL notes to Recommended Operating Conditions ...........................................................6

• Added 1000 hour Long Term Drift specification for DYA package......................................................................8

• Updated Typical Characteristics curves..............................................................................................................9

• Added QEC-Q200 Qualification feature section............................................................................................... 13

Changes from Revision D (February 2020) to Revision E (March 2020) Page

• Removed preview notice from the SOT-5X3 package........................................................................................1

• Updated Description section...............................................................................................................................1

• Changed minimum Junction Temperature from -40 to -65 in Absolute Maximum Ratings table........................ 6

• Changed Max Junction Temperature from 150 °C to 155 °C in Recommended Operating Conditions .............6

Changes from Revision C (January 2020) to Revision D (February 2020) Page

• Updated Features list..........................................................................................................................................1

• Updated Applications list.................................................................................................................................... 1

• Updated Description........................................................................................................................................... 1

• Updated Device Comparison Table ELPG package TA support from 150 °C to 170 °C.................................... 4

• Added DYA package to Device Comparison Table.............................................................................................4

• Added description for Junction temperature in Absolute Maximum Ratings ..................................................... 6

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS

• Added TJMAX spec for Automotive Grade 0 to Absolute Maximum Ratings ...................................................... 6

• Added ISNS spec for TA = 150 °C to 170 °C to Recommended Operating Conditions .......................................6

• Changed TA description to Automotive Grade 1 in Recommended Operating Conditions ............................... 6

• Changed TA description to Automotive Grade 0 in Recommended Operating Conditions ............................. 6

• Changed ambient temperature support for Automotive Grade 0 in from 150 °C to 170 °C...............................6

• Added 'Resistance Tolerance' Spec for TA = 150 °C to 170 °C.......................................................................... 8

• Added 'Long Term Drift ' for DYA package..........................................................................................................8

• Changed min spec 'Long Term Drift' for RH = 86 % from 0.1 % to -1 %............................................................ 8

• Added typical spec 'Long Term Drift' fpr RH = 86 %...........................................................................................8

• Changed max spec 'Long Term Drift' for RH = 86 % from 0.8 % to 1 %.............................................................8

• Changed min spec 'Long Term Drift' for DEC package from 0.1 % to -1 %........................................................8

• Added typical spec 'Long Term Drift' for DEC package...................................................................................... 8

• Changed max spec 'Long Term Drift' for RH = 86 % from 1 % to 1.8 %.............................................................8

• Changed min spec 'Long Term Drift ' for LPG package from 0.1 % to -0.5 %................................................... 8

• Added typical spec 'Long Term for Drift' LPG package......................................................................................8

• Changed max spec 'Long Term Drift' for RH = 86 % from 1.1 % to 1.4 %..........................................................8

• Added 'Long Term Drift' Spec for ELPG package..............................................................................................8

• Added Automotive Grade 0 typical characteristic curves................................................................................... 9

• Updated Overview section................................................................................................................................ 11

• Added TMP61-Q1 R-T Table section................................................................................................................12

• Updated Feature Description section............................................................................................................... 12

• Removed Transfer Tables.................................................................................................................................12

• Added Built-In Fail Safe section........................................................................................................................12

• Updated Application and implementation section to match TI datasheet standards........................................ 13

• Added link to Thermistor Design tool................................................................................................................14

• Removed Thermal Compensation section........................................................................................................14

Changes from Revision B (September 2019) to Revision C (January 2020) Page

• Added DYA package in PREVIEW status...........................................................................................................5

• Standardized pinout diagrams............................................................................................................................ 5

• Clarified Equation 1 ..........................................................................................................................................11

Changes from Revision A (June 2019) to Revision B (September 2019) Page

• Changed data sheet status from Production Mixed to Production Data............................................................. 1

• Added preview SOT-5X3 package .....................................................................................................................1

• Removed 'Functional, Unspecified Performance' rows...................................................................................... 6

• Added 'Long Term Drift' spec for LPG package..................................................................................................8

• Added Thermal Response Time graphs for the LPG package........................................................................... 9

• Added transfer tables for the LPG package......................................................................................................12

Changes from Revision * (April 2019) to Revision A (June 2019) Page

• Changed device status from Advanced Information to Production Data ........................................................... 1

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS

5 Device Comparison Table

PART

NUMBER R25 TYP R25 %TOL RATING TAPACKAGE OPTIONS

TMP61 10k 1% Catalog

–40 °C to 125 °C X1SON / DEC (0402)

–40 °C to 150 °C SOT-5X3 / DYA (0603)

–40 °C to 150 °C TO-92S / LPG

TMP61-Q1 10k 1%

Automotive Grade-1 –40 °C to 125 °C X1SON / DEC (0402)

Automotive Grade-0 –40 °C to 150 °C SOT-5X3 / DYA (0603)

–40 °C to 170 °C TO-92S / LPG

TMP63 100k 1% Catalog –40 °C to 125 °C X1SON / DEC (0402)

–40 °C to 150 °C SOT-5X3 / DYA (0603)

TMP63-Q1 100k 1% Automotive Grade-1 –40 °C to 125 °C X1SON / DEC (0402)

Automotive Grade-0 –40 °C to 150 °C SOT-5X3 / DYA (0603)

TMP64 47k 1% Catalog –40 °C to 125 °C X1SON / DEC (0402)

–40 °C to 150 °C SOT-5X3 / DYA (0603)

TMP64-Q1 47k 1% Automotive Grade-1 –40 °C to 125 °C X1SON / DEC (0402)

Automotive Grade-0 –40 °C to 150 °C SOT-5X3 / DYA (0603)

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS

6 Pin Configuration and Functions

±1 2 +

Figure 6-1. DEC Package 2-Pin X1SON (Top View)

±+

Figure 6-2. LPG Package 2-Pin TO-92S Top View (Angled)

±1 2 +

ID Area

Figure 6-3. DYA Package 2-Pin SOT-5X3 Bottom View (Angled)

Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

– 1 —Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +

terminal is at a higher voltage potential than the – terminal.

+ 2

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

TEXAS INSTRUMENTS

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

Voltage across the device 6 V

Junction temperature (TJ) Automotive Grade 1 (DEC, DYA QLPG package) -65 155 °C

Junction temperature (TJ) Automotive Grade 0 (ELPG package) -65 175 °C

Current through the device 450 µA

Storage temperature (Tstg) -65 175 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per AEC Q100-002(1)

HBM classification level 2 ±2000 V

Charged-device model (CDM), per AEC Q100-011

CDM classification level C6 ±1000 V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VSns Voltage Across Pins 2 (+) and 1 (–) 0 5.5 V

ISns

Current passing through the device TA = -40 °C to 150 °C 0 400 µA

Current passing through the device TA = 150 °C to 170 °C 50 250

Operating free-air temperature (Automotive Grade 1 DEC, QLPG Package) –40 125

°C

Operating free-air temperature (Automotive Grade 0 DYA Package) –40 150

Operating free-air temperature (Automotive Grade 0 ELPG Package)(1) (2) –40 170

(1) HTOL was performed at 160 °C for 2300 hours and 175 °C for 24 hours

(2) HTSL for was performed at 175 °C for 2000 hours

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS

7.4 Thermal Information

THERMAL METRIC(1) (2)

TMP61-Q1

UNITDEC (X1SON) LPG (TO-92S) DYA (SOT-5X3)

2 PINS 2 PINS 2 PINS

RθJA Junction-to-ambient thermal resistance(3) (4) 443.4 215 742.9 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 195.7 99.9 315.8 °C/W

RθJB Junction-to-board thermal resistance 254.6 191.7 506.2 °C/W

ΨJT Junction-to-top characterization parameter 19.9 35.1 109.3 °C/W

ΨJB Junction-to-board characterization parameter 254.5 191.7 500.4 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance – – – °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) For information on self-heating and thermal response time see Layout Guidelines section.

(3) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K

board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are

included in the PCB, per JESD 51-5.

(4) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

TEXAS INSTRUMENTS ISns

7.5 Electrical Characteristics

TA = -40 °C to 125 °C (TMP61Q), TA = -40 °C to 170 °C (TMP61E), ISns = 200 μA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R25 Thermistor Resistance at 25°C(1) TA = 25°C 9.9 10 10.1 kΩ

RTOL Resistance Tolerance(1)

TA = 25 °C –1 1

%TA = 0 °C to 70 °C –1 1

TA = -40 °C to 150 °C –1.5 1.5

RTOL Resistance Tolerance(1) TA = 150 °C to 170 °C -2.5 2.5 %

TCR-35

Temperature Coefficient of

Resistance

T1 = -40 °C, T2 = -30 °C +6220

ppm/°CTCR25 T1 = 20 °C, T2 = 30 °C +6400

TCR85 T1 = 80 °C, T2 = 90 °C +5910

TCR-35 %

Temperature Coefficient of

Resistance Tolerance

T1 = -40 °C, T2 = -30 °C ±0.4

%TCR25 % T1 = 20 °C, T2 = 30 °C ±0.2

TCR85 % T1 = 80 °C, T2 = 90 °C ±0.3

ΔR Sensor Long Term Drift (Reliability)

96 hours continuous operation

RH = 85 %, TA = 130 °C, VBias = 5.5V -1 0.1 1

600 hours continuous operation at TA = 150 °C

VBias = 5.5V, DEC Package -1 0.5 1.8

600 hours continuous operation at TA = 150 °C

VBias = 5.5V, DYA Package -1 0.2 1.2

1000 hours continuous operation at TA = 150

°C

VBias = 5.5V, DYA Package

-1 0.2 1.2

1000 hours continuous operation at TA = 150

°C

VBias = 5.5V, QLPG Package

-0.5 0.5 1.4

ΔR Sensor Long Term Drift (Reliability)

2300 hours continuous operation at TA = 160

°C

24 hours continuous operation at TA = 175 °C

VBias = 5.5V, ELPG Package

-2 1.1 4 %

tRES (stirred

liquid)

Thermal response to 63 % (DEC

Package)

T1 = 25 °C in Still Air to T2 = 125 °C in Stirred

Liquid 0.6 s

tRES (stirred

liquid)

Thermal response to 63 % (LPG

Package)

T1 = 25 °C in Still Air to T2 = 125 °C in Stirred

Liquid 2.9 s

tRES (still air)

Thermal response to 63 % (DEC

Package) T1 = 25 °C to T2 = 70 °C in Still Air 3.2 s

tRES (still air)

Thermal response to 63 % (LPG

Package) T1 = 25 °C to T2 = 70 °C in Still Air 20 s

(1) Limits defined based on 4th order equation, tolerance will change with 'Sensor Long Term Drift' specification.

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

TEXAS INSTRUMENTS emu 5340

7.6 Typical Characteristics

at TA = 25 °C, (unless otherwise noted)

Temperature (qC)

Resistance (k:)

-40 -15 10 35 60 85 110 135 160 180

61_1

IBIAS = 50 PA

IBIAS = 75 PA

IBIAS = 100 PA

IBIAS = 125 PA

IBIAS = 150 PA

IBIAS = 175 PA

IBIAS = 200 PA

Figure 7-1. Automotive Grade 0 Resistance vs.

Ambient Temperature Using Multiple Bias Currents

Temperature (qC)

Resistance (k:)

-40 -15 10 35 60 85 110 135 160 180

61_1

VBIAS = 1.8 V

VBIAS = 2.5 V

VBIAS = 3.3 V

VBIAS = 5 V

RBIAS = 10 kΩ with ±0.01% tolerance

Figure 7-2. Automotive Grade 0 Resistance vs.

Ambient Temperature Using Multiple Bias Voltages

Current Through TMP61, ISns (PA)

TCR (ppm/qC)

6240

6270

6300

6330

6360

6390

6420

6450

6480

6510

10 50 100 200 400

d004

Figure 7-3. TCR vs. Sense Currents (ISNS)

Voltage Across TMP61, VSns (V)

TCR (ppm/qC)

6290

6300

6310

6320

6330

6340

0.9 1.25 1.65 2.5

d005

VSns = 1.8 V, 2.5 V, 3.3 V, and 5.0 V, RBias = 10 kΩ with ±0.01%

Tolerance

Figure 7-4. TCR vs Sense Voltages, VSns

Current (PA)

Resistance (k:)

0 50 100 150 200 250 300 350 400 450

TMP6

-40 qC

25 qC

50 qC

100 qC

125 qC

150 qC

Figure 7-5. Supply Dependence Resistance vs.

Bias Current

Voltage (V)

Resistance (k:)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

TMP6

-40 qC

25 qC

50 qC

100 qC

125 qC

150 qC

RBias = 10 kΩ ( ±0.01% tolerance)

Figure 7-6. Supply Dependence vs. Bias Voltage

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS 25 ‘2

Time (Ps)

Output (V)

0.5

1.5

2.5

1.6 3.2 4.8 6.4 80

d008

VBias

VSns

VSNS = 1 V

Figure 7-7. Step Response

Time (s)

Resistance (k:)

0 0.19 0.38 0.57 0.76 0.95 1.14 1.33 1.52 1.71

0.6s0.6s

d009

Ambient material: stirred liquid

Figure 7-8. Thermal Response Time

Time (s)

Resistance (k:)

3.39 4.38 5.37 6.36 7.35 8.34 9.33 10.32 11.31

9.5

10.5

11.5

3.2s3.2s

d010

Ambient condition: still air

Figure 7-9. Thermal Response Time

Time (s)

Resistance (k:)

0 20 40 60 80 100 120 140 160

9.5

10.5

11.5

12.5

20s

D016

Ambient condition: still air

Figure 7-10. Thermal Response Time (LPG

Package)

Time (s)

Resistance (k:)

0 2 4 6 8 10 12 14 16 18

2.9s

d015

Ambient material: stirred liquid

Figure 7-11. Thermal Response Time (LPG Package)

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS mp V _ VEms * RTMFGI VTgmp = [Bias * RTMPGl Temp 7 — RBL‘as + RTMPGI

8 Detailed Description

8.1 Overview

The TMP61-Q1 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a

uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI

uses a special silicon process where the doping level and active region areas devices control the key

characteristics (the temperature coefficient resistance (TCR) and nominal resistance (R25)). The device has an

active area and a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage

potential. Connect the negative terminal to the lowest voltage potential.

Unlike an NTC, which is a purely resistive device, the TMP61-Q1 resistance is affected by the current across the

device and the resistance changes when the temperature changes. In a voltage divider circuit, TI recommends

to maintain the top resistor value at 10 kΩ. Changing the top resistor value or the VBIAS value changes the

resistance vs temperature table (R-T table) of the TMP61-Q1, and subsequently the polynomials as described in

the Section 9.3.1.1 section. Consult the Section 8.3 section for more information.

Equation 1 can help the user approximate the TCR.

 

T2 T1

R R

TCR

T2 T1 R 



 u

(1)

where

• TCR is in ppm/°C

Key terms and definitions:

• ISNS: Current flowing through the TMP61-Q1 device

• VSNS: Voltage across the two TMP61-Q1 terminal

• IBIAS: Current supplied by the biasing circuit.

• VBIAS: Voltage supplied by the biasing circuit.

• VTEMP: Output voltage that corresponds to the measured temperature. Note that this is different from VSNS. In

the use case of a voltage divider circuit with the TMP61-Q1 in the high side, VTEMP is measured across RBIAS.

8.2 Functional Block Diagram

RBias

VBias

VTemp

RTMP61 VTemp

RTMP61

IBias

Figure 8-1. Typical Implementation Circuits

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS

8.3 TMP61-Q1 R-T table

The TMP61-Q1 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current.

TI provides a Thermistor Design Tool to calculate the R-T table. The system designer must always validate the

calculations provided.

8.4 Feature Description

8.4.1 Linear Resistance Curve

The TMP61-Q1 has good linear behavior across the whole temperature range as shown in Section 7.6. This

range allows a simpler resistance-to-temperature conversion method that reduces look-up table memory

requirements. The linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary

with the device.

The linear resistance across the entire temperature range allows the device to maintain sensitivity at higher

operating temperatures.

8.4.2 Positive Temperature Coefficient (PTC)

The TMP61-Q1 has a positive temperature coefficient. As temperature increases the device resistance

increases leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient

system increases power consumption with temperature as the resistance decreases.

The TMP61-Q1 benefits from the reduced power consumption of the bias circuit with less self-heating than a

typical NTC system.

8.4.3 Built-In Fail Safe

The TMP6 family feature a positive tempeature coefficient. During a short-to-supply condition, the thermistor will

have increased current and power dissipated. Due to the positive temperature slope, the TMP6 will increase

resistance and limit self-heating by design.

In contrast, a NTC would continually reduce resistance due to self-heating leading to a positive feedback of

increasing power dissipation and decreasing resistance.

8.5 Device Functional Modes

The device operates in only one mode when operated within the Recommended Operating Conditions.

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TMP61-Q1 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves as a

temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on

the system-level requirements. The TMP61-Q1 has a nominal resistance at 25 °C (R25) of 10 kΩ with ±1%

maximum tolerance, a maximum operating voltage of 5.5 V (VSNS), and maximum supply current of 400 µA

(ISNS). This device may be used in a variety of applications to monitor temperature close to a heat source with

the very small DEC package option compatible with the typical 0402 (inch) footprint. Some of the factors that

influence the total measurement error include the ADC resolution (if applicable), the tolerance of the bias current

or voltage, the tolerance of the bias resistance in the case of a voltage divider configuration, and the location of

the sensor with respect to the heat source.

9.2 AEC-Q200 Qualifications

Although qualified under AEC-Q100, the TMP61-Q1 is also tested per the AEC-Q200 qualifications and passes

all required testing with the exception of the Terminal Strength (SMD) / Shear Test. For this test the following

results were observed:

• DEC Package passed up to 200g stress force

• DYA Package passed up to 400g stress force

The LPG package is not tested for AEC-Q200 qualifications.

9.3 Typical Application

9.3.1 Thermistor Biasing Circuits

VTemp

RBias

VBias

Figure 9-1. Voltage Biasing Circuit With Linear

Thermistor

VTemp

IBias

Figure 9-2. Current Biasing Circuit With Linear

Thermistor

VTemp

RBias

VBias

Figure 9-3. Voltage Biasing Circuit With Non-Linear

Thermistor

IBias

VTemp

Figure 9-4. Current Biasing Circuit With Non-Linear

Thermistor

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS VB‘AS Rams § RTMP61 VTEAP IN- GND RHLTER REF \N+ CHLTER ADC

9.3.1.1 Design Requirements

Existing thermistors, in general, have a non-linear temperature vs. resistance curve. To linearize the thermistor

response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or a resistance

linearization circuit by adding another resistance in parallel with the thermistor, RP. The Section 9.3.1 section

highlights the two implementations where RT is the thermistor resistance. To generate an output voltage across

the thermistor, the engineer can use a voltage divider circuit with the thermistor placed at either the high side

(close to supply) or low side (close to ground), depending on the desired voltage response (negative or positive).

Alternatively, the resistor can be biased directly using a precision current source (yielding the highest accuracy

and voltage gain). It is common to use a voltage divider with thermistors because of its simple implementation

and lower cost. The TMP61-Q1, on the other hand, has a linear positive temperature coefficient (PTC) of

resistance such that the voltage measured across it increases linearly with temperature. As such, the need for

linearization circuits is no longer a requirement, and a simple current source or a voltage divider circuit can be

used to generate the temperature voltage.

This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature

trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback

input for an active feedback control circuit.

The voltage across the device, as described in Equation 2, can be translated to temperature using either a

lookup table method (LUT) or a fitting polynomial, V(T). The Thermistor Design Tool must be used to translate

Vtemp to Temperature. The temperature voltage must first be digitized using an ADC. The necessary resolution

of this ADC is dependent on the biasing method used. Additionally, for best accuracy, tie the bias voltage (VBIAS)

to the reference voltage of the ADC to create a measurement where the difference in tolerance between the bias

voltage and the reference voltage cancels out. The application can also include a low-pass filter to reject system

level noise. In this case, place the filter as close to the ADC input as possible.

9.3.1.2 Detailed Design Procedure

The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage

(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due to

the voltage supply are cancelled and do not affect the temperature accuracy (as shown in Figure 9-5). Equation

2 describes the output voltage (VTEMP) based on the variable resistance of the TMP61-Q1 (RTMP61) and bias

resistor (RBIAS). The ADC code that corresponds to that output voltage, ADC full-scale range, and ADC

resolution is given in Equation 3.

Figure 9-5. TMP61-Q1 Voltage Divider With an ADC

TMP61

TEMP BIAS

TMP61 BIAS

V V ×

R + R

§ ·

¨ ¸

(2)

TEMP

ADC Code 2

FSR

(3)

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS \ Precision Current Source 5 400 [1A VTEMF'

where

• FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)

• n is the resolution of the ADC

Equation 4 shows when VREF = VBIAS, VBIAS cancels out.

TMP61

BIAS

TMP61 BIAS n n

TMP61

BIAS TMP61 BIAS

R + R R

ADC Code 2 2

V R + R

§ ·

u¨ ¸ § ·

¨ ¸

(4)

Use a polynomial equation or a LUT to extract the temperature reading based on the ADC code read in the

microcontroller. Use the Thermistor Design Tool to translate the TMP61-Q1 resistance to temperature.

The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the

output voltage of the divider circuit cannot increase much. Therefore, this application design does not use all of

the ADC codes due to the small voltage output range compared to the FSR. This application is very common,

however, and is simple to implement.

A current source-based circuit, such as the one shown in Figure 9-6, offers better control over the sensitivity of

the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I × R. For example,

if a current source of 40 µA is used with the device, the output voltage spans approximately 5.5 V and has a gain

up to 40 mV/°C. Having control over the voltage range and sensitivity allows for full use of the ADC codes and

full-scale range. Figure 9-7 shows the temperature voltage for various bias current conditions. Similar to the

ratiometric approach, if the ADC has a built-in current source that shares the same bias as the reference voltage

of the ADC, the tolerance of the supply current cancels out. In this case, a precision ADC is not required. This

method yields the best accuracy, but can increase the system implementation cost.

Figure 9-6. TMP61-Q1 Biasing Circuit With Current Source

Temperature (qC)

VTEMP (V)

-60 -40 -20 0 20 40 60 80 100 120 140 160

d013

IBIAS = 50 PA

IBIAS = 100 PA

IBIAS = 200 PA

IBIAS = 300 PA

IBIAS = 400 PA

Figure 9-7. TMP61-Q1 Temperature Voltage With Varying Current Sources

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS RTIWM

In comparison to the non-linear NTC thermistor in a voltage divider, the TMP61-Q1 has an enhanced linear

output characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are

shown in Figure 9-8. Consider an example where VBIAS = 5 V, RBIAS = 100 kΩ, and a parallel resistor (RP) is

used with the NTC thermistor (RNTC) to linearize the output voltage with an additional 100-kΩ resistor. The

output characteristics of the voltage dividers are shown in Figure 9-9. The device produces a linear curve across

the entire temperature range while the NTC curve is only linear across a small temperature region. When the

parallel resistor (RP) is added to the NTC circuit, the added resistor makes the curve much more linear but

greatly affects the output voltage range.

Figure 9-8. TMP61-Q1 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits

Temperature (qC)

VTEMP (V)

-60 -40 -20 0 20 40 60 80 100 120 140 160

d012

VNTC

VTMP61

VNTC with RP

Figure 9-9. NTC With and Without a Linearization Resistor vs. TMP61-Q1 Temperature Voltages

9.3.1.2.1 Thermal Protection With Comparator

Use the TMP61-Q1 device along with a voltage reference, and a comparator to program the thermal protection.

As shown in Figure 9-10, the output of the comparator remains low until the voltage of the thermistor divider, with

RBIAS and RTMP61, rises above the threshold voltage set by R1 and R2. When the output goes high, the

comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent

the output from continuously toggling around the temperature threshold when the output returns low. Either a

comparator with built-in hysteresis or feedback resistors may be used.

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS VEEF Rams g R1 g VTR‘P VTEMP +\ 4* RTMP51 £3) - / R2 5 V 5 V ‘7 RFB 300 k0 Rams R2 20 k0 200 k0 R1 \ 10 k0 \ V ' OUT \_ O VREF + / R3 /

Figure 9-10. Temperature Switch Using TMP61-Q1 Voltage Divider and a Comparator

9.3.1.2.2 Thermal Foldback

One application that uses the output voltage of the TMP61-Q1 in an active control circuit is thermal foldback.

This is performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures,

the LEDs begin to heat up due to environmental conditions and self heating. Thus, at a certain temperature

threshold based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs

and prevent thermal runaway. The device voltage output increases with temperature when the output is in the

lower position of the voltage divider and can provide a response used to fold back the current. Typically, the

device holds the current at a specified level until a high temperature is reached, known as the knee point, at

which the current must be rapidly reduced in order to continue operation. To better control the temperature/

voltage sensitivity, the device uses a rail-to-rail operational amplifier. Figure 9-11 shows the temperature knee

point where the foldback begins. The set by the reference voltage (2.5 V) at the positive input, and the feedback

resistors set the response of the foldback curve. The foldback knee point may be chosen based on the output of

the voltage divider and the corresponding temperature from Equation 5 (110 °C, for example). The device uses a

buffer between the voltage divider with RTMP61 and the input to the op amp to prevent loading and variations in

VTEMP.

Figure 9-11. Thermal Foldback Using TMP61-Q1 Voltage Divider and a Rail-to-Rail Op Amp

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS 56 Error (m

The op amp remains high as long as the voltage output is below VREF. When the temperature goes above 110

°C, the output falls to the 0-V rail of the op amp. The rate at which the foldback occurs depends on the feedback

network, RFB and R1, which varies the gain of the op amp, G, as shown in Equation 6. The foldback behavior

controls the voltage and temperature sensitivity of the circuit. The device feeds this voltage output into a LED

driver circuit that adjusts output current accordingly. VOUT is the final output voltage used for thermal foldback

and is calculated in Equation 7. Figure 9-12 describes the output voltage curve in this example which sets the

knee point at 110 °C.

TMP61

TEMP BIAS

TMP61 BIAS

V = V ×

R + R

§ ·

¨ ¸

(5)

G =

(6)

OUT TEMP REF

V G× V + (1+ G) × V 

(7)

Temperature (qC)

VTEMP (V)

0 25 50 75 100 125 150

D014

Figure 9-12. Thermal Foldback Voltage Output Curve

9.3.1.3 Application Curve

The TMP61-Q1 accuracy varies depending on the selected biasing circuit. This variation can be seen in Figure

9-13. VTEMP is shown with either VBIAS at 2 V in a resistor divider circuit (RBIAS = 10 kΩ ±1%) or IBIAS at 200 µA.

Supply sources used are assumed to be ideal. The best accuracy is achieved using a direct current bias method.

Temperature (qC)

VTEMP (V)

Error (qC)

-60 -40 -20 0 20 40 60 80 100 120 140 160

0 0

1 0.8

2 1.6

3 2.4

4 3.2

5 4

6 4.8

7 5.6

d011

VTemp (IBIAS= 200 PA)

VTemp (VBIAS = 2 V)

Error (qC) (IBIAS = 200 PA)

Error (qC) (VBIAS = 2 V)

Figure 9-13. TMP61-Q1 Voltage Output and Temperature Error Based on the Bias Method

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS (.) (+) V+

10 Power Supply Recommendations

The maximum recommended operating voltage of the TMP61-Q1 is 5.5 V (VSNS), and the maximum current

through the device is 400 µA (ISNS).

11 Layout

11.1 Layout Guidelines

The layout of the TMP61-Q1 is similar to that of a passive component. If the device is biased with a current

source, the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the

circuit is biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is

connected to ground and V+ is connected to the output, VTEMP. If the device is placed on the upper side of the

divider, V+ is connected to the voltage source and V– is connected to the output voltage, VTEMP. Figure 11-1

shows the device layout.

11.2 Layout Examples

Figure 11-1. Recommended Layout: DEC Package

www.ti.com

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021

Product Folder Links: TMP61-Q1

l TEXAS INSTRUMENTS m

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

MSL Ratings and Reflow Profiles (SPRABY1)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TMP61-Q1

SNIS210F – APRIL 2019 – REVISED FEBRUARY 2021 www.ti.com

Product Folder Links: TMP61-Q1

I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 29-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TMP6131ELPGMQ1 ACTIVE TO-92 LPG 2 3000 RoHS & Green SN N / A for Pkg Type -40 to 170 TMP61

TMP6131QDECRQ1 ACTIVE X1SON DEC 2 10000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 EL

TMP6131QDECTQ1 ACTIVE X1SON DEC 2 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 EL

TMP6131QDYARQ1 ACTIVE SOT-5X3 DYA 2 3000 RoHS & Green SN Level-3-260C-168 HR -40 to 150 1GK

TMP6131QDYATQ1 ACTIVE SOT-5X3 DYA 2 250 RoHS & Green SN Level-3-260C-168 HR -40 to 150 1GK

TMP6131QLPGMQ1 ACTIVE TO-92 LPG 2 3000 RoHS & Green SN N / A for Pkg Type -40 to 125 TMP61

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 29-Dec-2020

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TMP61-Q1 :

•Catalog: TMP61

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TMP6131QDECRQ1 X1SON DEC 2 10000 178.0 8.4 0.7 1.15 0.47 2.0 8.0 Q1

TMP6131QDECTQ1 X1SON DEC 2 250 178.0 8.4 0.7 1.15 0.47 2.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TMP6131QDECRQ1 X1SON DEC 2 10000 205.0 200.0 33.0

TMP6131QDECTQ1 X1SON DEC 2 250 205.0 200.0 33.0

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2020

Pack Materials-Page 2

,«3 al- --I :11 iiiz‘ D }}\*D i‘ I-III

www.ti.com

PACKAGE OUTLINE

0.50

0.41

0.05

0.00

0.65

0.1 C A B

2X 0.55

0.45

2X 0.3

0.2

A1.05

0.95 B

0.65

0.55

4224506/A 08/2018

X1SON - 0.5 mm max heightDEC0002A

PLASTIC SMALL OUTLINE - NO LEAD

PIN 1 INDEX AREA

SEATING PLANE

0.03 C

0.1 C A B

SYMM

X0.125)(45 PIN 1 ID

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M

2. This drawing is subject to change without notice.

SCALE 11.000

““““

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

(R0.05) TYP (0.65)

2X (0.5)

2X (0.25)

4224506/A 08/2018

X1SON - 0.5 mm max heightDEC0002A

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:60X

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.

It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK DETAILS

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

METAL UNDER

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

(0.7)

2X (0.5)

2X (0.3) (0.05)

4224506/A 08/2018

X1SON - 0.5 mm max heightDEC0002A

PLASTIC SMALL OUTLINE - NO LEAD

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:60X

SYMM

PCB PAD METAL

UNDER SOLDER PASTE

V g _;_ v \ $7 7, 7777777 777 \ _‘__ 7 a f $4TLU‘EMEW

www.ti.com

PACKAGE OUTLINE

1.7

1.5

2X 0.35

0.25

2X 0.4

0.2

0.77 MAX

2X 0.15

0.08

2X 0.3

0.1 0.7

0.5 TYP

B1.3

1.1

0.85

0.75

NOTE 3

SOT (SOD-523) - 0.77 mm max heightDYA0002A

PLASTIC SMALL OUTLINE

4224978/B 09/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEITA SC-79 registration except for package height

PIN 1

ID AREA

SEATING PLANE

0.05 C

0.1 C A B

0.05

SYMM

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

AROUND 0.05 MIN

AROUND

2X (0.4)

(R0.05) TYP

2X (0.67)

(1.48)

4224978/B 09/2021

SOT (SOD-523) - 0.77 mm max heightDYA0002A

PLASTIC SMALL OUTLINE

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SYMM

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDERMASK DETAILS

www.ti.com

EXAMPLE STENCIL DESIGN

2X (0.67)

2X (0.4)

(R0.05) TYP

(1.48)

SOT (SOD-523) - 0.77 mm max heightDYA0002A

PLASTIC SMALL OUTLINE

4224978/B 09/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:40X

SYMM

www.ti.com

PACKAGE OUTLINE

4.1

3.9

2X 15.5

15.1

3X 0.48

0.33 2X 1.27 0.05

3.25

3.05

3X 0.51

0.33

3X 0.51

0.40

2X (45 )

0.86

0.66

1.62

1.42

2.64

2.44

2.68

2.28

5.05

MAX

2.3

2.0

6X 0.076 MAX

(0.55)

2 MAX

4221971/B 06/2022

TO-92 - 5.05 mm max heightLPG0002A

TRANSISTOR OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

SCALE 1.300

www.ti.com

EXAMPLE BOARD LAYOUT

TYP

ALL AROUND

0.05 MAX (1.07)

(1.7)

(1.27)

(2.54)

(R0.05) TYP (1.07)

(1.7)

3X (R0.38) VIA

4221971/B 06/2022

TO-92 - 5.05 mm max heightLPG0002A

TRANSISTOR OUTLINE

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE:20X

METAL

TYP

OPENING

SOLDER MASK

www.ti.com

TAPE SPECIFICATIONS

0 1 0 1

12.9

12.5

6.55

6.15

13.0

12.4

2.5 MIN 6.5

5.5

3.8-4.2 TYP

9.5

8.5

19.0

17.5

1 MAX

0.45

0.35

0.25

0.15

TO-92 - 5.05 mm max heightLPG0002A

TRANSISTOR OUTLINE

4221971/B 06/2022

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments 的 TMP6131-Q1 规格书

信息

帮助

联系我们

关注我们