Microchip Technology 的 MCP6541(1R,1U,2,3,4) 规格书

6‘ MICRDCHIP E 3| 3 E EVE E I: I: E E E El E IE IZ % EEEE EEEE E E E E EEE EEE ENE E E EEEE EEE
2019-2020 Microchip Technology Inc. DS20001696K-page 1
MCP6541/1R/1U/2/3/4
Features
• Low Quiescent Current: 600 nA/Comparator (typ.)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• CMOS/TTL-Compatible Output
• Propagation Delay: 4 µs
(typical, 100 mV Overdrive)
• Wide Supply Voltage Range: 1.6V to 5.5V
• Available in Single, Dual and Quad
• Single Available in SOT-23-5, SC-70-5 * Packages
• Chip Select (CS) with MCP6543
• Low Switching Current
• Internal Hysteresis: 3.3 mV (typ.)
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
• Laptop Computers
• Mobile Phones
• Metering Systems
• Hand-held Electronics
• RC Timers
• Alarm and Monitoring Circuits
• Windowed Comparators
• Multivibrators
Related Devices
• Open-Drain Output: MCP6546/7/8/9
Description
The Microchip Technology Inc. MCP6541/1R/1U/2/3/4
family of comparators is offered in single (MCP6541,
MCP6541R, MCP6541U), single with Chip Select (CS)
(MCP6543), dual (MCP6542) and quad (MCP6544)
configurations. The outputs are push-pull (CMOS/TTL-
compatible) and are capable of driving heavy DC or
capacitive loads.
These comparators are optimized for low-power,
single-supply operation with greater than rail-to-rail
input operation. The push-pull output of the
MCP6541/1R/1U/2/3/4 family supports rail-to-rail out-
put swing and interfaces with TTL/CMOS logic. The
internal input hysteresis eliminates output switching
due to internal input noise voltage, reducing current
draw. The output limits supply current surges and
dynamic power consumption while switching. This
product family operates with a single-supply voltage as
low as 1.6V and draws less than 1 µA/comparator of
quiescent current.
The related MCP6546/7/8/9 family of comparators from
Microchip has an open-drain output. Used with a pull-
up resistor, these devices can be used as level-shifters
for any desired voltage up to 10V and in wired-OR
logic.
* SC-70-5 E-Temp parts not available at this release of
the data sheet.
MCP6541U SOT-23-5 is E-Temp only.
Package Types
VINA+
VIN–
MCP6541
VSS
VDD
OUT
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
PDIP, SOIC, MSOP
4
1
2
3
-
+
5
SOT-23-5
VDD
OUT
VIN+
VSS
VIN–
MCP6542
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
-
OUTA
+
-
+
VDD
OUTB
VINB–
VINB+
VIN+
VIN–
MCP6543
VSS
VDD
OUT
1
2
3
4
8
7
6
5
-
+
NC
CS
NC
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
MCP6544
VINA+
VINA–
VSS
1
2
3
4
14
13
12
11
-
OUTA
+
-
+
VDD
OUTD
VIND–
VIND+
10
9
8
5
6
7
OUTB
VINB–
VINB+VINC+
VINC-
OUTC
+
--
+
PDIP, SOIC, TSSOP
-
+
MCP6541R
4
1
2
3
5
SC-70-5, SOT-23-5
VSS
VIN+
VIN–
VDD
OUT
MCP6541U
+
4
1
2
3
-
+
5
VSS
OUT
VIN+
VDD
VIN–
MCP6541
SC-70-5, SOT-23-5
–
Push-Pull Output Sub-Microamp Comparators
MCP6541/1R/1U/2/3/4
DS20001696K-page 2 2019-2020 Microchip Technology Inc.
NOTES:
2019-2020 Microchip Technology Inc. DS20001696K-page 3
MCP6541/1R/1U/2/3/4
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Current at Analog Input Pin (VIN+, VIN-.........................±2 mA
Analog Input (VIN) †† ...................... VSS - 1.0V to VDD + 1.0V
All other Inputs and Outputs........... VSS - 0.3V to VDD + 0.3V
Difference Input Voltage ....................................... |VDD - VSS|
Output Short-Circuit Current ................................ Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ) .......................... +150°C
ESD Protection on all Pins (HBM;MM) ..................4 kV; 400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current
Limits”.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,VIN+ = VDD/2,
VIN– = VSS, and RL=100k to VDD/2 (Refer to Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 1.6 — 5.5 V
Quiescent Current per comparator IQ0.3 0.6 1.0 µA IOUT = 0
Input
Input Voltage Range VCMR VSS0.3 — VDD+0.3 V
Common-mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 5.3V
Common-mode Rejection Ratio CMRR 50 65 — dB VDD = 5V, VCM = 2.5V to 5.3V
Common-mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 2.5V
Power Supply Rejection Ratio PSRR 63 80 — dB VCM = VSS
Input Offset Voltage VOS -7.0 ±1.5 +7.0 mV VCM = VSS (Note 1)
Drift with Temperature VOS/TA— ±3 — µV/°C TA = -40°C to +125°C, VCM = VSS
Input Hysteresis Voltage VHYST 1.5 3.3 6.5 mV VCM = VSS (Note 1)
Linear Temp. Co. (Note 2)TC1— 6.7—µV/°CT
A = -40°C to +125°C, VCM = VSS
Quadratic Temp. Co. (Note 2)TC2— -0.035 — µV/°C2TA = -40°C to +125°C, VCM = VSS
Input Bias Current IB—1—pAV
CM = VSS
At Temperature (I-Temp parts) IB—25100pAT
A = +85°C, VCM = VSS (Note 3)
At Temperature (E-Temp parts) IB— 1200 5000 pA TA = +125°C, VCM = VSS (Note 3)
Input Offset Current IOS — ±1 — pA VCM = VSS
Common-mode Input Impedance ZCM —10
13||4 — ||pF
Differential Input Impedance ZDIFF —10
13||2 — ||pF
Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Input bias current at temperature is not tested for SC-70-5 package.
4: Limit the output current to Absolute Maximum Rating of 30 mA.
MCP6541/1R/1U/2/3/4
DS20001696K-page 4 2019-2020 Microchip Technology Inc.
AC CHARACTERISTICS
Push-Pull Output
High-Level Output Voltage VOH VDD0.2 — — V IOUT = -2 mA, VDD = 5V
Low-Level Output Voltage VOL ——V
SS+0.2 V IOUT = 2 mA, VDD = 5V
Short-Circuit Current ISC — -2.5, +1.5 — mA VDD = 1.6V (Note 4)
ISC —±30—mAV
DD = 5.5V (Note 4)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,
VIN+ = VDD/2, Step = 200 mV, Overdrive = 100 mV, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Rise Time tR—0.85— µs
Fall Time tF—0.85— µs
Propagation Delay (High-to-Low) tPHL —4 8µs
Propagation Delay (Low-to-High) tPLH —4 8µs
Propagation Delay Skew tPDS — ±0.2 — µs (Note 1)
Maximum Toggle Frequency fMAX —160—kHzV
DD = 1.6V
fMAX —120—kHzV
DD = 5.5V
Input Noise Voltage Eni —200—µV
P-P 10 Hz to 100 kHz
Note 1: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,VIN+ = VDD/2,
VIN– = VSS, and RL=100k to VDD/2 (Refer to Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Input bias current at temperature is not tested for SC-70-5 package.
4: Limit the output current to Absolute Maximum Rating of 30 mA.
2019-2020 Microchip Technology Inc. DS20001696K-page 5
MCP6541/1R/1U/2/3/4
FIGURE 1-1: Timing Diagram for the CS
Pin on the MCP6543.
FIGURE 1-2: Propagation Delay Timing
Diagram.
MCP6543 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ =
VDD/2, VIN– = VSS, and CL= 36 pF (Refer to Figures 1-1 and 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —5.0—pACS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8 VD
D
—V
DD V
CS Input Current, High ICSH —1—pACS = VDD
CS Input High, VDD Current IDD —18—pACS = VDD
CS Input High, GND Current ISS —–20— pACS = VDD
Comparator Output Leakage IO(LEAK) —1—pAV
OUT = VDD, CS = VDD
CS Dynamic Specifications
CS Low to Comparator Output
Low Turn-on Time
tON —250msCS = 0.2 VDD to VOUT = VDD/2,
VIN– = VDD
CS High to Comparator Output
High Z Turn-off Time
tOFF —10—µsCS = 0.8 VDD to VOUT = VDD/2,
VIN– = VDD
CS Hysteresis VCS_HYS
T
—0.6— VV
DD = 5V
VIL
Hi-Z
tON
VIH
CS
tOFF
VOUT
-20 pA (typ.)
Hi-Z
ISS
ICS
1pA (typ.) 1pA (typ.)
-20 pA (typ.)
-0.6 µA (typ.)
VOL
tPLH
VOUT
VIN–100 mV
100 mV tPHL
VOL
VIN+ = VDD/2
VOH
MCP6541/1R/1U/2/3/4
DS20001696K-page 6 2019-2020 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
1.1 Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
FIGURE 1-3: AC and DC Test Circuit for
the Push-Pull Output Comparators.
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C
Operating Temperature Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC-70 JA — 331 — °C/W
Thermal Resistance, 5L-SOT-23 JA —220.7—°C/W
Thermal Resistance, 8L-PDIP JA — 89.3 — °C/W
Thermal Resistance, 8L-SOIC JA —149.5—°C/W
Thermal Resistance, 8L-MSOP JA —211—°C/W
Thermal Resistance, 14L-PDIP JA —70—°C/W
Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note: The MCP6541/1R/1U/2/3/4 I-Temp parts operate over this extended temperature range, but with reduced
performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.
VDD
VSS = 0V
200 k
200 k
200 k
200 k
VOUT
VIN = VSS
36 pF
MCP654X
. .JJ
2019-2020 Microchip Technology Inc. DS20001696K-page 7
MCP6541/1R/1U/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 k to VDD/2, and CL = 36 pF.
FIGURE 2-1: Input Offset Voltage at
VCM =V
SS.
FIGURE 2-2: Input Offset Voltage Drift at
VCM =V
SS.
FIGURE 2-3: The MCP6541/1R/1U/2/3/4
Comparators Show No Phase Reversal.
FIGURE 2-4: Input Hysteresis Voltage at
VCM =V
SS.
FIGURE 2-5: Input Hysteresis Voltage
Linear Temp. Co. (TC1) at VCM =V
SS.
FIGURE 2-6: Input Hysteresis Voltage
Quadratic Temp. Co. (TC2) at VCM =V
SS.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Input Offset Voltage (mV)
Percentage of Occurrences
1200 Samples
VCM = VSS
0%
2%
4%
6%
8%
10%
12%
14%
16%
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
1200 Samples
VCM = VSS
TA
= -40°C to +125°C
-1
0
1
2
3
4
5
6
7
012345678910
Time (1 ms/div)
Inverting Input, Output Voltage
(V)
VOUT
VIN–
VDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1.62.02.42.83.23.64.04.44.85.25.66.0
Input Hysteresis Voltage (mV)
Percentage of Occurrences
1200 Samples
VCM = VSS
0%
5%
10%
15%
20%
25%
4.6
5.0
5.4
5.8
6.2
6.6
7.0
7.4
7.8
8.2
8.6
9.0
9.4
Input Hysteresis Voltage –
Linear Temp. Co.; TC1 (µV/°C)
Percentage of Occurrences
596 Samples
VCM = VSS
TA = -40°C to +125°C
VDD = 1.6VVDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-0.060
-0.056
-0.052
-0.048
-0.044
-0.040
-0.036
-0.032
-0.028
-0.024
-0.020
-0.016
Input Hysteresis Voltage –
Quadratic Temp. Co.; TC2 (µV/°C2)
Percentage of Occurrences
596 Samples
VCM = VSS
TA = -40°C to +125°C
VDD = 5.5V
VDD = 1.6V
MCP6541/1R/1U/2/3/4
DS20001696K-page 8 2019-2020 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=V
DD/2, VIN– = GND,
RL=100k to VDD/2, and CL=36pF.
FIGURE 2-7: Input Offset Voltage vs.
Ambient Temperature at VCM =V
SS.
FIGURE 2-8: Input Offset Voltage vs.
Common-mode Input Voltage at VDD =1.6V.
FIGURE 2-9: Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.
FIGURE 2-10: Input Hysteresis Voltage vs.
Ambient Temperature at VCM =V
SS.
FIGURE 2-11: Input Hysteresis Voltage vs.
Common-mode Input Voltage at VDD =1.6V.
FIGURE 2-12: Input Hysteresis Voltage vs.
Common-mode Input Voltage at VDD =5.5V.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Offset Voltage (mV)
VDD = 1.6V
VDD = 5.5V
VCM = VSS
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Offset Voltage (mV)
VDD = 1.6V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (mV)
VDD = 5.5V
TA
= +85°C
TA
= +125°C
TA = -40°C
TA
= +25°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-50-250 255075100125
Ambient Temperature (°C)
Input Hysteresis Voltage (mV)
VDD = 1.6V
VDD = 5.5V
VCM = VSS
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Hysteresis Voltage (mV)
TA = -40°C
TA = +125°C
TA = +85°C
TA = +25°C
VDD = 1.6V
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Hysteresis Voltage (mV)
VDD = 5.5V TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
, Vnr , Van/2
2019-2020 Microchip Technology Inc. DS20001696K-page 9
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=V
DD/2, VIN– = GND,
RL=100k to VDD/2, and CL=36pF.
FIGURE 2-13: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-14: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-15: Quiescent Current vs.
Common-mode Input Voltage at VDD =1.6V.
FIGURE 2-16: Input Bias Current, Input
Offset Current vs. Common-mode Input Voltage.
FIGURE 2-17: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-18: Quiescent Current vs.
Common-mode Input Voltage at VDD =5.5V.
55
60
65
70
75
80
85
90
-50-25 0 255075100125
Ambient Temperature (°C)
CMRR, PSRR (dB)
Input Referred
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V
0.1
1
10
100
1000
55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
IB
| IOS |
VDD = 5.5V
VCM = VDD
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Common Mode Input Voltage (V)
Quiescent Current
per comparator (µA)
VDD = 1.6V
Sweep VIN+, VIN– = VDD/2
Sweep VIN–, VIN+ = VDD/2
0.1
1
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents (A)
VDD = 5.5V
100f
100p
1p
10p
1n
10n
IB, TA = +125°C
IB, TA = +85°C
IOS, TA = +125°C
IOS, TA = +85°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
per Comparator (µA)
TA = +125°C
TA
= +85°C
TA
= +25°C
TA = -40°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Quiescent Current
per Comparator (µA)
VDD = 5.5V
Sweep VIN+, VIN– = VDD/2
Sweep VIN–, VIN+ = VDD/2
TA : 4125“: TA : «125%:
MCP6541/1R/1U/2/3/4
DS20001696K-page 10 2019-2020 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=V
DD/2, VIN– = GND,
RL=100k to VDD/2, and CL=36pF.
FIGURE 2-19: Supply Current vs. Toggle
Frequency.
FIGURE 2-20: Output Voltage Headroom
vs. Output Current at VDD =1.6V.
FIGURE 2-21: High-to-Low Propagation
Delay.
FIGURE 2-22: Output Short Circuit Current
Magnitude vs. Power Supply Voltage.
FIGURE 2-23: Output Voltage Headroom
vs. Output Current at VDD =5.5V.
FIGURE 2-24: Low-to-High Propagation
Delay.
0.1
1
10
0.1 1 10 100
Toggle Frequency (kHz)
Supply Current (µA)
VDD = 5.5V
VDD = 1.6V
100 mV Overdrive
VCM = VDD/2
RL = infinity
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Current (mA)
Output Voltage Headroom (V)
VDD = 1.6V
VOL–VSS:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD–VOH:
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
012345678
High-to-Low Propagation Delay (µs)
Percentage of Occurrences
600 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5VVDD = 1.6V
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Short Circuit Current
Magnitude (mA)
TA = -40°C
TA
= +25°C
TA
= +85°C
TA = +125°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
Output Current (mA)
Output Voltage Headroom (V)
VDD = 5.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD – VOH:
TA = +125°C
TA
= +85°C
TA
= +25°C
TA = -40°C
VOL – VSS:
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
012345678
Low-to-High Propagation Delay (µs)
Percentage of Occurrences
600 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5VVDD = 1.6V
2019-2020 Microchip Technology Inc. DS20001696K-page 11
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=V
DD/2, VIN– = GND,
RL=100k to VDD/2, and CL=36pF.
FIGURE 2-25: Propagation Delay Skew.
FIGURE 2-26: Propagation Delay vs.
Power Supply Voltage.
FIGURE 2-27: Propagation Delay vs.
Common-mode Input Voltage at VDD =1.6V.
FIGURE 2-28: Propagation Delay vs.
Ambient Temperature.
FIGURE 2-29: Propagation Delay vs. Input
Overdrive.
FIGURE 2-30: Propagation Delay vs.
Common-mode Input Voltage at VDD =5.5V.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Propagation Delay Skew (µs)
Percentage of Occurrences
600 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 1.6V
VDD = 5.5V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Propagation Delay (µs)
VCM = VDD/2
tPLH @ 100 mV Overdrive
tPHL @ 100 mV Overdrive
tPLH @ 10 mV Overdrive
tPHL @ 10 mV Overdrive
0
1
2
3
4
5
6
7
8
0.00.20.40.60.81.01.21.41.6
Common Mode Input Voltage (V)
Propagation Delay (µs)
VDD = 1.6V
100 mV Overdrive
tPLH
tPHL
0
1
2
3
4
5
6
7
8
-50-250 255075100125
Ambient Temperature (°C)
Propagation Delay (µs)
100 mV Overdrive
VCM = VDD/2
tPLH @ VDD = 1.6V tPHL @ VDD = 1.6V
tPLH @ VDD = 5.5V tPHL @ VDD = 5.5V
1
10
100
1 10 100 1000
Input Overdrive (mV)
Propagation Delay (µs)
VCM = VDD/2
tPHL @ VDD = 5.5V
tPLH @ VDD = 1.6V
tPHL @ VDD = 1.6V
tPLH @ VDD = 5.5V
0
1
2
3
4
5
6
7
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Propagation Delay (µs)
VDD = 5.5V
100 mV Overdrive
tPHL
tPLH
cs (3
MCP6541/1R/1U/2/3/4
DS20001696K-page 12 2019-2020 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=V
DD/2, VIN– = GND,
RL=100k to VDD/2, and CL=36pF.
FIGURE 2-31: Propagation Delay vs. Load
Capacitance.
FIGURE 2-32: Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 1.6V (MCP6543 only).
FIGURE 2-33: Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD =1.6V
(MCP6543 only).
FIGURE 2-34: Chip Select (CS) Step
Response (MCP6543 only).
FIGURE 2-35: Supply Current (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 5.5V (MCP6543 only).
FIGURE 2-36: Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD =5.5V
(MCP6543 only).
0
5
10
15
20
25
30
35
40
45
50
0 102030405060708090
Load Capacitance (nF)
Propagation Delay (µs)
100 mV Overdrive
VCM = VDD/2
tPHL @ VDD = 1.6V
tPLH @ VDD = 1.6V
tPLH @ VDD = 5.5V
tPHL @ VDD = 5.5V
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
0.00.20.40.60.81.01.21.41.6
Chip Select (CS) Voltage (V)
Supply Current
per Comparator (A)
Comparato
r
Shuts Of
Comparator
Turns On
VDD = 1.6V
CS Hysteresis
CS
High-to-Low
CS
Low-to-High
1m
1µ
10µ
100n
1n
10n
100p
10p
100µ
0
5
10
15
20
25
30
01234567891011121314
Time (1 ms/div)
Supply Current (µA)
-8.1
-6.5
-4.9
-3.2
-1.6
0.0
1.6
Output Voltage,
Chip Select Voltage (V),
Start-up
IDD
Charging output
capacitance
VDD = 1.6V
VOUT
CS
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
012345678910
Time (ms)
Chip Select, Output Voltage (V)
VOUT
VDD = 5.5V
CS
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select (CS) Voltage (V)
Supply Current
per Comparator (A)
Comparato
r
Shuts Of
Comparator
Turns On
VDD = 5.5V
1m
1µ
10µ
100n
1n
10n
100p
10p
CS
Low-to-High
CS
Hysteresis
CS
High-to-Low
100µ
0
20
40
60
80
100
120
140
160
180
200
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Time (0.5 ms/div)
Supply Current
per Comparator (µA)
-24
-21
-18
-15
-12
-9
-6
-3
0
3
6
Output Voltage,
Chip Select Voltage (V)
Start-up IDD
Charging output
capacitance
VDD = 5.5V
VOUT
CS
2019-2020 Microchip Technology Inc. DS20001696K-page 13
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=V
DD/2, VIN– = GND,
RL=100k to VDD/2, and CL=36pF.
FIGURE 2-37: Input Bias Current vs. Input
Voltage.
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
MCP6541/1R/1U/2/3/4
DS20001696K-page 14 2019-2020 Microchip Technology Inc.
NOTES:
2019-2020 Microchip Technology Inc. DS20001696K-page 15
MCP6541/1R/1U/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
3.1 Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2 CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.3 Digital Outputs
The comparator outputs are CMOS, push-pull digital
outputs. They are designed to be compatible with
CMOS and TTL logic and are capable of driving heavy
DC or capacitive loads.
3.4 Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
TABLE 3-1: PIN FUNCTION TABLE
MCP6541
PDIP,
SOIC,
MSOP
MCP6541
SOT-23-5,
SC-70-5
MCP6541R
MCP6541U
SOT-23-5
SC-70-5
MCP6542
MCP6543
MCP6544
Symbol Description
6 1 1 4 1 6 1 OUT, OUTA Digital Output (comparator A)
2443222V
IN–, VINA– Inverting Input (comparator A)
3331333V
IN+, VINA+ Non-inverting Input (comparator A)
7525874V
DD Positive Power Supply
————5—5V
INB+ Non-inverting Input (comparator B)
————6—6V
INB– Inverting Input (comparator B)
— — — — 7 — 7 OUTB Digital Output (comparator B)
— — — — — — 8 OUTC Digital Output (comparator C)
——————9V
INC– Inverting Input (comparator C)
——————10V
INC+ Non-inverting Input (comparator C)
42524411V
SS Negative Power Supply
——————12V
IND+ Non-inverting Input (comparator D)
——————13V
IND– Inverting Input (comparator D)
— — — — — — 14 OUTD Digital Output (comparator D)
—————8—CS
Chip Select
1, 5, 8 — — — — 1, 5 — NC No Internal Connection
MCP6541/1R/1U/2/3/4
DS20001696K-page 16 2019-2020 Microchip Technology Inc.
NOTES:
2019-2020 Microchip Technology Inc. DS20001696K-page 17
MCP6541/1R/1U/2/3/4
4.0 APPLICATIONS INFORMATION
The MCP6541/1R/1U/2/3/4 family of push-pull output
comparators are fabricated on Microchip’s state-of-the-
art CMOS process. They are suitable for a wide range
of applications requiring very low-power consumption.
4.1 Comparator Inputs
4.1.1 PHASE REVERSAL
The MCP6541/1R/1U/2/3/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2, limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the input
pin (VIN+ and VIN–) from going too far above VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 2-37. Applications that are
high-impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages. With
this topology, the input voltage is 0.3V above VDD and
0.3V below VSS. Therefore, the input offset voltage is
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
The MCP6541/1R/1U/2/3/4 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV) and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage (200 µVp-p). Figure 4-3 depicts this behavior.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad VIN–
V1
MCP654X
R1
VDD
D1
R2
VSS – (minimum expected V2)
2mA
VOUT
V2
R2R3
D2
+
–
R1
VSS – (minimum expected V1)
2mA
MCP6541/1R/1U/2/3/4
DS20001696K-page 18 2019-2020 Microchip Technology Inc.
FIGURE 4-3: The MCP6541/1R/1U/2/3/4
comparators’ internal hysteresis eliminates
output chatter caused by input noise voltage.
4.2 Push-Pull Output
The push-pull output is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give rail-to-rail output performance. They
are driven with circuitry that minimizes any switching
current (shoot-through current from supply-to-supply)
when the output is transitioned from high-to-low, or from
low-to-high (see Figures 2-15,2-18, and 2-32 — 2-36
for more information).
4.3 MCP6543 Chip Select (CS)
The MCP6543 is a single comparator with Chip Select
(CS). When CS is pulled high, the total current
consumption drops to 20 pA (typ.); 1 pA (typ.) flows
through the CS pin, 1 pA (typ.) flows through the out-
put pin and 18 pA (typ.) flows through the VDD pin, as
shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low, the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
4.4 Externally Set Hysteresis
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Input offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other and thus reduces dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
4.4.1 NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for single-
supply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
FIGURE 4-4: Noninverting Circuit with
Hysteresis for Single-supply.
FIGURE 4-5: Hysteresis Diagram for the
Noninverting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EQUATION 4-1:
-3
-2
-1
0
1
2
3
4
5
6
7
8
Time (100 ms/div)
Output Voltage (V)
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
Input Voltage (10 mV/div)
VOUT
VIN–
VDD = 5.0V
Hysteresis
VREF
VIN
VOUT
MCP654X
VDD
R1RF
+
-
VOUT
High-to-Low Low-to-High
VDD
VOH
VOL
VSS
VSS VDD
VTHL VTLH
VIN
VTLH VREF 1
R1
RF
-------+



VOL
R1
RF
-------



–=
VTHL VREF 1
R1
RF
-------+



VOH
R1
RF
-------



–=
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
Egg:
2019-2020 Microchip Technology Inc. DS20001696K-page 19
MCP6541/1R/1U/2/3/4
4.4.2 INVERTING CIRCUIT
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
FIGURE 4-6: Inverting Circuit With
Hysteresis.
FIGURE 4-7: Hysteresis Diagram for the
Inverting Circuit.
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
FIGURE 4-8: Thevenin Equivalent Circuit.
Where:
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
Figure 2-20 and Figure 2-23 can be used to determine
typical values for VOH and VOL.
4.5 Bypass Capacitors
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.6 Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-31).
The supply current increases with increasing toggle
frequency (Figure 2-19), especially with higher
capacitive loads.
4.7 Battery Life
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) frequently to conserve
start-up power. Capacitive loads will draw additional
power at start-up.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6541/1R/1U/2/3/4 family’s bias current at 25°C
(1 pA, typ.).
VIN
VOUT
MCP654X
VDD
R2
RF
R3
VDD
–
+
VOUT
High-to-LowLow-to-High
VDD
VOH
VOL
VSS
VSS VDD
VTLH VTHL
VIN
V23
VOUT
MCP654X
VDD
R23 RF
+
VSS
–
R23
R2R3
R2R3
+
-------------------=
V23
R3
R2R3
+
------------------- VDD
=
VTHL VOH
R23
R23 RF
+
-----------------------



V23
RF
R23 RF
+
----------------------


+=
VTLH VOL
R23
R23 RF
+
-----------------------



V23
RF
R23 RF
+
----------------------


+=
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
MCP6541/1R/1U/2/3/4
DS20001696K-page 20 2019-2020 Microchip Technology Inc.
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
FIGURE 4-9: Example Guard Ring Layout
for Inverting Circuit.
1. Inverting Configuration (Figures 4-6 and 4-9):
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b.Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
2. Non-inverting Configuration (Figure 4-4):
a.Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b.Connect the guard ring to the inverting input
pin (VIN–).
4.9 Unused Comparators
An unused amplifier in a quad package (MCP6544)
should be configured as shown in Figure 4-10. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
FIGURE 4-10: Unused Comparators.
4.10 Typical Applications
4.10.1 PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. Figure 4-11 shows an
example of this approach.
FIGURE 4-11: Precise Inverting
Comparator.
4.10.2 WINDOWED COMPARATOR
Figure 4-12 shows one approach to designing a win-
dowed comparator. The AND gate produces a logic ‘1’
when the input voltage is between VRB and VRT (where
VRT > VRB).
FIGURE 4-12: Windowed Comparator.
4.10.3 ASTABLE MULTIVIBRATOR
A simple astable multivibrator design is shown in
Figure 4-13. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF
.
FIGURE 4-13: Astable Multivibrator.
Guard Ring
VSS
VIN-V
IN+
¼ MCP6544
VDD
–
+
VREF
VDD
VDD
R1R2VOUT
VIN
VREF
MCP6041
MCP654X
+
+
–
–
VRT
MCP6542
VRB
VIN
1/2
MCP6542
1/2
+
+
–
–
MCP6541
VDD
R1R2
R3
VREF
C1
VOUT
+
–
HHH F‘WH‘Wf‘Wfl Ow LALuJLuJLJ HHHH XXXXYY o ‘9” UUUU F! F! HHH 3—D. UUU Wflflfl Wflfifl MCPG em (25$ C>SQ LALUJLUJLJ LALuJLu—H-J flflflfl flflflfl SN o 592 0 S92 UUUU UUUU
2019-2020 Microchip Technology Inc. DS20001696K-page 21
MCP6541/1R/1U/2/3/4
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) (MCP6541, MCP6542, MCP6543, MCP6544) Example:
8-Lead SOIC (150 mil) (MCP6541, MCP6542, MCP6543, MCP6544) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6541
I/P256
1146
MCP6542
I/SN1146
256
5-Lead SOT-23 (MCP6541, MCP6541R, MCP6541U) Example:
XXNN AB25
5-Lead SC-70 (MCP6541, MCP6541U)Example:
XXNN Front)
YWW (Back)
BA25 Front)
146 (Back)
Device I-Temp
Code
E-Temp
Code
MCP6541 ABNN GTNN
MCP6541R AGNN GUNN
MCP6541U — ATNN
Note: Applies to 5-Lead SOT-23
Device I-Temp Code E-Temp
Code
MCP6541T-I/LT ABNN Note 2
MCP6541UT-I/LT BANN Note 2
Note 1: I-Temp parts prior to March 2005 are
marked “BAN”
2: SC-70-5 E-Temp parts not available
at this release of this data sheet.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
MCP6541
E/P^^256
1146
MCP6541E
SN^^1146
256
OR
OR
3
e
3
e
H‘WH‘WH‘WF‘WH‘WF‘WH‘W O G 0% HHHHHHLLMHLUJLUJ HHHHHHH 0% UUUUUUU FHF‘WF‘WF‘WH‘WH‘WH‘W HHHHHHH 0 3:9 :II: :II: :II: :II: :II: :II: :II: :II: :II: :II: :II: :II: :II:
MCP6541/1R/1U/2/3/4
DS20001696K-page 22 2019-2020 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6544) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6544-I/P
114656
MCP6544E/P
1146256
OR
3
e
MCP6544
I/P
1146256
OR
3
e
14-Lead SOIC (150 mil) (MCP6544) Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX MCP6544ISL
1146256
MCP6544
1146256
I/SL^^
OR
3
e
OR
MCP6544
1146256
E/SL^^
3
e
8-Lead MSOP (MCP6541, MCP6542, MCP6543)Example:
OR
6543I
146256
6543E
146256
HHHHHHH Q\ C) HHHHHHH HHHHHHH I» yo 0 O mmum HHUHHUH UUUUUUU
2019-2020 Microchip Technology Inc. DS20001696K-page 23
MCP6541/1R/1U/2/3/4
Package Marking Information (Continued)
14-Lead TSSOP (MCP6544) Example:
XXXXXXXX
YYWW
NNN
MCP6544I
1146
256
MCP6544E
1146
256
OR
1w 9 m m fl— 7777 [51 Q 2X @— c 5X b I-III TOP VIEW PLANE t J fi—l L SIDE VIEW chrochip Techno
MCP6541/1R/1U/2/3/4
DS20001696K-page 24 2019-2020 Microchip Technology Inc.
0.15 C
0.15 C
0.10 C A B
C
SEATING
PLANE
13
4
2X
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-061-LT Rev E Sheet 1 of 2
2X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
5-Lead Plastic Small Outline Transistor (LT) [SC70]
D
EE1
e
e
5X b
0.30 C
5X TIPS
END VIEW
B
A
N
A
A1
A2
L
c
NOTE 1
2019-2020 Microchip Technology Inc. DS20001696K-page 25
MCP6541/1R/1U/2/3/4
Microchip Technology Drawing C04-061-LT Rev E Sheet 2 of 2
Number of Pins
Overall Height
Terminal Width
Overall Width
Terminal Length
Molded Package Width
Molded Package Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E1
A2
e
L
E
N
0.65 BSC
0.10
0.15
0.80
0.00
-
0.20
1.25 BSC
-
-
2.10 BSC
MILLIMETERS
MIN NOM
5
0.46
0.40
1.10
0.10
MAX
c-0.08 0.26
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Lead Thickness
5-Lead Plastic Small Outline Transistor (LT) [SC70]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Overall Length D 2.00 BSC
0.80 - 1.00
1.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
MCP6541/1R/1U/2/3/4
DS20001696K-page 26 2019-2020 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing No. C04-2061-LT Rev E
5-Lead Plastic Small Outline Transistor (LT) [SC70]
12
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pad Width
Contact Pitch
X
MILLIMETERS
0.65 BSC
MIN
E
MAX
Distance Between Pads
Contact Pad Length
G
Y0.95
GxDistance Between Pads 0.20
NOM
0.45
2.20
1.25
X
Y
E
C
Gx
G
3
45
SILK SCREEN
ECU .—@—. \ | 1 f 1 g N 1 1 i ' 1 LJ I E3 ’ /////;/// ’ \ ; [I ;///// ”I Q 0.15 c D ‘ 2X NOTE1 1 i 2 I i——lE|—’ IA —— Nx b “--E TOP VIEW fl / \ A A2 \ I L, iiii A17 $ [5 SIDE VIEW Microcmp Technology Drawing 004—09101 Rev E Sheel 1 of 2
2019-2020 Microchip Technology Inc. DS20001696K-page 27
MCP6541/1R/1U/2/3/4
0.15 C D
2X
NOTE 1 12
N
TOP VIEW
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.20 C
C
SEATING PLANE
AA2
A1
e
NX bB
0.20 C A-B D
e1
D
E1
E1/2
E/2
E
D
A
0.20 C2X
(DATUM D)
(DATUM A-B)
A
A
SEE SHEET 2
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
MCP6541/1R/1U/2/3/4
DS20001696K-page 28 2019-2020 Microchip Technology Inc.
Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
c
L
L1
T
VIEW A-A
SHEET 1
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
protrusions shall not exceed 0.25mm per side.
1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2.
Foot Angle
Number of Pins
Pitch
Outside lead pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Lead Thickness
Lead Width
Notes:
L1
I
b
c
Dimension Limits
E
E1
D
L
e1
A
A2
A1
Units
N
e
0°
0.08
0.20 -
-
-
10°
0.26
0.51
MILLIMETERS
0.95 BSC
1.90 BSC
0.30
0.90
0.89
-
0.60 REF
2.90 BSC
-
2.80 BSC
1.60 BSC
-
-
-
MIN
5
NOM
1.45
1.30
0.15
0.60
MAX
REF: Reference Dimension, usually without tolerance, for information purposes only.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Dimensioning and tolerancing per ASME Y14.5M
LBJ
2019-2020 Microchip Technology Inc. DS20001696K-page 29
MCP6541/1R/1U/2/3/4
RECOMMENDED LAND PATTERN
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing No. C04-2091B [OT]
Dimension Limits
Contact Pad Length (X5)
Overall Width
Distance Between Pads
Contact Pad Width (X5)
Contact Pitch
Contact Pad Spacing
3.90
1.10
G
Z
Y
1.70
0.60
MAXMIN
C
X
E
Units
NOM
0.95 BSC
2.80
MILLIMETERS
Distance Between Pads GX 0.35
1
5
X
Y
ZC
E
GX
G
2
SILK SCREEN
MCP6541/1R/1U/2/3/4
DS20001696K-page 30 2019-2020 Microchip Technology Inc.
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
E1
c
C
PLANE
.010 C
12
N
D
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
2019-2020 Microchip Technology Inc. DS20001696K-page 31
MCP6541/1R/1U/2/3/4
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB --.430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(NOTE 5)
5. Lead design above seating plane may vary, based on assembly vendor.
A // 0.10 c E. NOTE I TOP VIEW SIDE VIEW AI— PLANE A A2 SEATING SEE VIEW C VIEW A—A MIcrochIp Technology Drawmg N
MCP6541/1R/1U/2/3/4
DS20001696K-page 32 2019-2020 Microchip Technology Inc.
0.25 CA–B D
C
SEATING
PLANE
TOP VIEW
SIDE VIEW
VIEW A–A
0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
12
N
h
h
A1
A2
A
A
B
e
D
E
E
2
E1
2
E1
NOTE 5
NOTE 5
NX b
0.10 CA–B
2X
H0.23
(L1)
L
R0.13
R0.13
VIEW C
SEE VIEW C
NOTE 1
D
2019-2020 Microchip Technology Inc. DS20001696K-page 33
MCP6541/1R/1U/2/3/4
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-5°
Mold Draft Angle Bottom
15°-5°
Mold Draft Angle Top
0.51-0.31
b
Lead Width
0.25-0.17
c
Lead Thickness
1.27-0.40LFoot Length
0.50-0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
8NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
protrusions shall not exceed 0.15mm per side.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
§
Footprint L1 1.04 REF
5. Datums A & B to be determined at Datum H.
/ JUDE T
MCP6541/1R/1U/2/3/4
DS20001696K-page 34 2019-2020 Microchip Technology Inc.
RECOMMENDED LAND PATTERN
Microchip Technology Drawing C04-2057-SN Rev E
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
5.40
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
1.55
0.60
NOM
E
X1
C
Y1
SILK SCREEN
8-Lead Plastic Micro Small Outline Package (MS) [MSOP] NXb $ n13® I-Ii TOP VIEW Q 010 C A A2 I \ l I l l =' SEATlNG PLANE SIDEVIEW A1 7 7 j/ SEE DETAlLC —- “—E 7 J END VIEW Mmrocrup Technology Drawmg COAJHC SheeM oi2
2019-2020 Microchip Technology Inc. DS20001696K-page 35
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
B-Lead Plastic Micro Small Outline Package (MS) [MSOP] _ _GAUGE PLANE 0L SEAT‘NG PLANE L ’ W (L1) DETAIL c Umts MILUMETERS D1mension L1m1ts MW NOM MAX Number of Pms N 1 a | mm a 0.65 ssc Overs” He1ghl A , , 1 10 Momed Package Thickness A2 0 75 O 85 O 95 Standoff A1 0 oo , o 15 Overa‘l Wldm E 4.90 530 Mama Package wmn E1 3.00 550 Overa‘l Lengfih D 3 00 BSC Fool Length L o 40 1 0 60 | 0 so Faulprml L1 0 95 REF Fool Angle w 0" , 3’ Lead Tmckness C 0 08 , 0 23 Lead wmm b 0 22 , O 40 Notes: 1 Pm 1 wsua1 1ndex ieature may vary‘ but must be \ocaled withm me hatched eves 2 D1mens1ons D and E1 do not incmde mold flash or pro|rus1ons.Mo\d flash or prairusmns snau nut exceed 0.15mm per side. 3 D1mens1oning and Iolerancmg perASME v14 5M BSC B351: Dimensmn Tneoreucany exact value shown wunom to1erances. REF Reverence D1mensmn.usual\y wnneu: merance‘ for Informzhan purposes only. Microch‘p Techno‘ogy Drawmg 00471110 Shee| 2 012
MCP6541/1R/1U/2/3/4
DS20001696K-page 36 2019-2020 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Micro SmaH Outltne Package (MS) [MSOP] x—»‘ <_ ejduee="" t="" 1="" ts.“="" .="" screen="" ‘11»="" lax="" recommended="" land="" pattern="" umts="" mtllimeters="" dtmenston="" ltmtts="" mw="" |="" nom="" |="" max="" contact="" pitch="" e="" 0.65="" bsc="" cuntaet="" pad="" spacmg="" c="" a="" 40="" overal‘="" wldlh="" z="" 5="" 55="" canlact="" pad="" wtdth="" (x3)="" x1="" 0.45="" contact="" pad="" length="" (x5)="" w="" 1.45="" distance="" between="" pads="" :51="" 2.95="" dlslance="" between="" pads="" gx="" o="" 20="" notes:="" 1="" dimensiomng="" and="" toteranemg="" per="" asme="" v14="" 5m="" ass.="" basic="" dimensiun.="" theoreticatly="" exact="" vatue="" shown="" wilhom="" toterances.="" mlcmchlp="" tecnnutogy="" drawtng="" no="" c0a72111a="">
2019-2020 Microchip Technology Inc. DS20001696K-page 37
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
F‘WFWFFHF‘WF‘WH‘WF‘W % f 8/3 $ / mmmmmmm W H :H: JL LJ
MCP6541/1R/1U/2/3/4
DS20001696K-page 38 2019-2020 Microchip Technology Inc.


 
 
 
 

 

 
   
  
  
   
    
  
    
    
    
    
    
    
    
   
N
E1
D
NOTE 1
123
E
c
eB
A2
L
A
A1 b1
be
   
I-l-l NXb mu» U I I I I TOP VIEW E :I SIDE VIEW jg VIEW A—A MI —>‘<—h plane="" iaa2="" i="" seating="" ie="" :="" :="" :="" :="" see="" view="" c="" l.="" :1]="" 7c="" chrochip="" technology="" drawmg="" no.="" 004-055-5="">
2019-2020 Microchip Technology Inc. DS20001696K-page 39
MCP6541/1R/1U/2/3/4
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
0.20 C
0.25 CA–B D
12
N
2X N/2 TIPS
TOP VIEW
SIDE VIEW
VIEW A–A
A
e
B
E
D
E
2
D
E1
E2
2
NX b
A1
A2
A
C
SEATING
PLANE
0.10 C
14X
0.10 CA–B
0.10 C D
c
h
h
H
SEE VIEW C
(L1)
L
R0.13
R0.13
VIEW C
NOTE 1
3
0.10 C
NOTE 5
NOTE 5
2X
2X
MCP6541/1R/1U/2/3/4
DS20001696K-page 40 2019-2020 Microchip Technology Inc.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Foot Angle 0° - 8°
15°-5°
Mold Draft Angle Bottom
15°-5°
Mold Draft Angle Top
0.51-0.31bLead Width
0.25-0.10
c
Lead Thickness
1.04 REFL1Footprint
0.50-0.25hChamfer (Optional)
8.65 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25-0.10
A1
Standoff
--1.25A2Molded Package Thickness
1.75--AOverall Height
1.27 BSC
e
Pitch
14NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
Foot Length L 0.40 - 1.27
§
or protrusion, which shall not exceed 0.25 mm per side.
3.
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
4.
Notes:
Dimension D does not include mold flash, protrusions or gate burrs, which shall
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
5. Datums A & B to be determined at Datum H.
Lead Angle 0° - -
2019-2020 Microchip Technology Inc. DS20001696K-page 41
MCP6541/1R/1U/2/3/4
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
Contact Pad Length (X14)
Contact Pad Width (X14)
Y
X
1.55
0.60
NOM
CContact Pad Spacing 5.40
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
E
X
Y
C
SILK SCREEN
Microchip Technology Drawing No. C04-2065-SL Rev D
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
12
14
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] TOP VIEW ._D_.“ SEATING PLANE. """ SIDE VIEW Microchip Technology Drawing 004-0370 Sheei 1 of 2
MCP6541/1R/1U/2/3/4
DS20001696K-page 42 2019-2020 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] uhlts MlLLIMETERS Dimension lells MIN | NONI | MAX Number al Plhs N 14 Pltch e 0 65 Esc Overall Helgnt A . . 1 20 Molded Package Thlckness A2 0 so 1 cc 1 cs Standoff A1 0 05 . c 15 Overall Wldln E 6 40 BSC Molded Package Width E1 4 30 4 40 4 50 Molded Package Lengln D 4 90 5 00 510 Foot Length L 0 45 0 so 0 75 Foolprinl (L1) 1.00 REF Fool Angle V 0“ . 8° Lead Tnlckness c 0 09 . 0 20 Lead Width in o 19 . o 30 Notes 1 Pm 1 Visual lndEX leature may vary. but must be lucaled w1thln lhe hatched area 2. Dimenslons D and E1 do not lhclude mold llash or prolrusions Mold llash or prolrusmns shall nol exceed a 15mm per Slda 3. Dimehslomhg and tolerahcing per ASME v14.5M BSC Basio Dimenslon. Theorellcally exact value snown wlthout tolerances. REF Relererlce Dlmension, usually without tolerance. lor inlorrnation purposes only. Mlcmchlp Technology Drawlng No cm-umc Sheet 2 of 2
2019-2020 Microchip Technology Inc. DS20001696K-page 43
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOF] C1 . l l :3 :3 7 E |:| |:| 7 6 X1 ’ E :I \ ,l w L SILK SCREEN RECOMMENDED LAND PATTERN Umls MlLLIMETERS Dimenslon lells MIN | NONI | MAX Contacl Pllch E 0 65 ESC Conlam Pad Spacmg c1 5 90 Contacl Pad Wldth (X14) X‘l O 45 Comm Pad Lengm (x14) Y‘l 1 45 Dlslance Between Pads 6 0 20 Nules. 1 Dlmenslcnlng and Inlerancmg per ASME V14 5M ass. Baswc Dimensxon Theorehcally exam value shown wllhcul lolerances Mlcmchip Technology Drawing No C0472087A
MCP6541/1R/1U/2/3/4
DS20001696K-page 44 2019-2020 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc. DS20001696K-page 45
MCP6541/1R/1U/2/3/4
APPENDIX A: REVISION HISTORY
Revision K (March 2020)
The following is the list of modifications:
1. Updated package drawings for the SC-70
package.
Revision J (November 2019)
The following is the list of modifications:
1. Updated Section 5.0 “Packaging
Information”.
Revision H (December 2011)
The following is the list of modifications:
1. Updated Package Types drawings to correctly
show the device representation for the SC-70
package.
1. Updated package’s temperatures in the Te m-
perature Characteristics table.
2. Corrected the marking information table for the
5-Lead SC-70 package (MCP6541 and
MCP6541U) in Section 5.1 “Package Marking
Information”.
3. Updated package outline drawings in
Section 5.1 “Package Marking Information”
to show all views for each package.
4. Minor editorial changes.
Revision G (March 2011)
The following is the list of modifications:
1. Updated the marking information for the 5-Lead
SC-70 package in Section 5.1 “Package
Marking Information”.
Revision F (September 2007)
1. Corrected polarity of MCP6541U SOT-23-5 pin
out diagram on front page.
2. Section 5.0 “Packaging Information”:
Updated package outline drawings per
MarCom.
Revision E (September 2006)
The following is the list of modifications:
1. Added MCP6541U pinout for the SOT-23-5
package.
2. Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.
3. Added applications write-ups on unused
comparators.
4. Added disclaimer to package outline drawings.
Revision D (May 2006)
The following is the list of modifications:
1. Added E-temp parts.
2. Changed VHYST temperature specification to
linear and quadratic temperature coefficients.
3. Changed specifications and plots for E-Temp.
4. Added section 3.0 “Pin Descriptions”.
5. Corrected package marking (See Section 5.1
“Package Marking Information”).
6. Added Appendix A: “Revision History”.
Revision C (September 2003)
• Undocumented changes.
Revision B (November 2002)
• Undocumented changes.
Revision A (March 2002)
• Original Release of this Document.
MCP6541/1R/1U/2/3/4
DS20001696K-page 46 2019-2020 Microchip Technology Inc.
NOTES:
PART NO. v ‘01" CS CS
2019-2020 Microchip Technology Inc. DS20001696K-page 47
MCP6541/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6541: Single Comparator
MCP6541T: Single Comparator (Tape and Reel)
(SC-70, SOT-23, SOIC, MSOP)
MCP6541RT: Single Comparator (Rotated - Tape and
Reel) (SOT-23 only)
MCP6541UT: Single Comparator (Tape and Reel)
(SC-70, SOT-23; SOT-23-5 is E-Temp
only)
MCP6542: Dual Comparator
MCP6542T: Dual Comparator
(Tape and Reel for SOIC and MSOP)
MCP6543: Single Comparator with CS
MCP6543T: Single Comparator with CS
(Tape and Reel for SOIC and MSOP)
MCP6544: Quad Comparator
MCP6544T: Quad Comparator
(Tape and Reel for SOIC and TSSOP)
Temperature Range: I = -40°C to +85°C
E * = -40°C to +125°C
* SC-70-5 E-Temp parts not available at this release of the
data sheet.
Package: LT = Plastic Package (SC-70), 5-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead (MCP6544)
ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6544)
PART NO. -X /XX
PackageTemperature
Range
Device
Examples:
a) MCP6541T-I/LT: Tape and Reel,
Industrial Temperature,
5LD SC-70.
b) MCP6541T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23.
c) MCP6541-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
d) MCP6541-E/P: Extended Temperature,
8LD PDIP.
e) MCP6541-E/SN: Extended Temperature,
8LD SOIC.
f) MCP6541RT-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT23.
g) MCP6541UT-E/LT: Tape and Reel,
Industrial Temperature,
5LD SC-70
h) MCP6541UT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT23.
a) MCP6542-I/MS: Industrial Temperature,
8LD MSOP.
b) MCP6542T-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
c) MCP6542-I/P: Industrial Temperature,
8LD PDIP.
d) MCP6542-E/SN: Extended Temperature,
8LD SOIC.
a) MCP6543-I/SN: Industrial Temperature,
8LD SOIC.
b) MCP6543T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC.
c) MCP6543-I/P: Industrial Temperature,
8LD PDIP.
d) MCP6543-E/SN: Extended Temperature,
8LD SOIC.
a) MCP6544T-I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC.
b) MCP6544T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
c) MCP6544-I/P: Industrial Temperature,
14LD PDIP.
d) MCP6544T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP.
MCP6541/1R/1U/2/3/4
DS20001696K-page 48 2019-2020 Microchip Technology Inc.
NOTES:
2019-2020 Microchip Technology Inc. DS20001696K-page 49
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019-2020, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-5763-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
6‘ ‘MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS20001696K-page 50 2019-2020 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
02/28/20