onsemi 的 NUS6160MN 规格书

’ [IN ON Semioonductor® ® .
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 0
Publication Order Number:
NUS6160MN/D
NUS6160MN
Low Profile Overvoltage
Protection IC with
Integrated MOSFET
This device represents a new level of safety and integration by
combining an overvoltage protection circuit (OVP) with a dual 20 V
P−channel power MOSFET. The OVP is specifically designed to
protect sensitive electronic circuitry from overvoltage transients and
power supply faults. During such events, the IC quickly disconnects
the input supply from the load, thus protecting it. The integration of
the additional transistor and power MOSFET reduces layout space and
promotes better charging performance.
The IC is optimized for applications that use an external AC−DC
adapter or a car accessory charger to power a portable product or
recharge its internal batteries.
Features
•Overvoltage Turn−Off Time of Less Than 1.5 ms
•Undervoltage Lockout Protection; 3.0 V, Nominal
•High Accuracy Undervoltage Threshold of 5.0%
•−20 V Integrated P−Channel Power MOSFET
•Low RDS(on) = 64 mW @ −4.5 V
•Compact 3.0 x 4.0 mm QFN Package
•Maximum Solder Reflow Temperature @ 260°C
•This is a Pb−Free Device
Benefits
•Provide Battery Protection
•Integrated Solution Offers Cost and Space Savings
•Integrated Solution Improves System Reliability
•Optimized for Commercial PMUs from Top Suppliers
Applications
•Portable Computers and PDAs
•Cell Phones and Handheld Products
•Digital Cameras
QFN22
CASE 485AT
Device Package Shipping†
ORDERING INFORMATION
NUS6160 = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
MARKING
DIAGRAM
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NUS6160MNTWG QFN22
(Pb−Free)
3000 /
Tape & Reel
http://onsemi.com
(Note: Microdot may be in either location)
1NUS
6160
ALYWG
G
Figure 2. Typical Charging Solution hllp://onsemi.com 2
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2
N/C
Gate1
Drain1
Drain1
Drain1
N/C
N/C
In
GND
(Top View)
FETSW
Drain1
1
22
6
711
12
17
18
N/C
Source2
Source1
Drain1
Gate2
Drain2
Flag
N/C
Out
En
N/C
Figure 1. Pinout
FETREG
Drain2
Drain2
Drain2
N/C
Figure 2. Typical Charging Solution
Wall Adaptor
ChargeSW
ChargeREG
Vbat
NUS6160
20
15 1 8
3
4, 5, 6, 7
10
14
18 19 9, 11, 13
IN
GND
OUT
Battery
FETREG
FETSW
EN
FLAG
OUT, EN, FUSE T‘Viyv
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MAXIMUM RATINGS (TJ = 25°C, unless otherwise stated)
Rating Symbol Min Max Unit
VIN to Ground VIN −0.3 21 V
OUT, EN, FLAG Pins Voltage to Ground VOUT
, VEN, VFLAG −0.3 7.0 V
Maximum Current from VIN to VOUT (PMOS) Imax 600 mA
Drain−to−Source Voltage VDSS −20 V
Gate−to−Source Voltage VGS −8.0 8.0 V
Continuous Drain Current, Steady State ID−2.0 A
Pulsed Drain Current, tp = 10 ms IDM −4.0 A
Source Current IS−1.1 A
Operating Ambient Temperature TA−40 85 °C
Storage Temperature TSTG −55 150 °C
Operating Junction Temperature TJ150 °C
Thermal Resistance (Note 1)
1 in2 (645 mm2) (All devices fully enhanced)
OVP FET
FETSW
FETREG
1 in2 (645 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG)
OVP FET
FETSW
FETREG
0.25 in2 (161 mm2) (All devices fully enhanced)
OVP FET
FETSW
FETREG
0.25 in2 (161 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG)
OVP FET
FETSW
FETREG
qJA
68
42
46
43
39
80
79
53
56
53
49
92
°C/W
ESD Performance (Human Body Model) Pins 1, 15, 18, 19, 20 −2.5 kV
Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 1 oz. copper, double sided board. Thermal impedance requires total for DT calculations. See example in thermal description.
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PIN DESCRIPTION
Pin Name Description
1 Out This pin is the output of the internal OVP chip. It must be connected to the source of the upper
FET (Pin 8).
3Gate FETSW This pin is the gate of the upper FET which is normally used for a switch in series with the battery.
It is controlled by the PMU.
4, 5, 6, 7 Drain FETSW These pins are the drain of the upper FET. For the lowest on resistance connect all pins together.
This set of pins must be connected to the source of the lower (regulator) FET, Pin 10.
8Source FETSW This pin is the source of the upper FET and must be connected to the output pin of the internal
OVP chip (Pin 1).
9, 11, 13 Drain FETREG These pins are the drain of the lower FET which is normally used for the regulation function. It
connects to the positive terminal of the battery.
10 Source FETREG This pin is the source of the lower FET and must be connected to the drain pins of the upper FET.
12 N/C This pin has no internal connections and is isolated from all internal circuitry within the chip.
14 Gate FETREG This pin is the gate of the lower FET which is normally used for the regulation function in series
with the battery. It is controlled by the PMU.
15 FLAG The fault flag is an open drain output and therefore requires a pullup resistor. The FLAG pin will be
driven low when the input voltage exceeds the OVLO trip level.
2, 16, 17,
21, 22
N/C These pins are connected to the ground of the analog chip. This is a medium impedance
connection and should not be used for the ground signal. These pins should either be left floating
or connected to ground, but not any other potential. If these pins are connected to ground, the
ground pin (19) must still be used.
18 EN The ENABLE pin must be held low for normal operation. When this pin is tied high the unit will be
shut down. The state of the enable pin has no impact on the FAULT pin.
19 Gnd This is the ground reference pin for the internal OVP chip.
20 In This pin is the input to the internal OVP chip and connects to the wall, or car adaptor.
> OVLO‘ 5mm mA mm Fm FUSE > UVLO to FIIG > OVLO to FIIG From EN
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OVP ELECTRICAL CHARACTERISTICS
(Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.)
Characteristic Symbol Conditions Min Typ Max Unit
Input Voltage Range Vin 1.2 20 V
Undervoltage Lockout
Threshold
UVLO Vin falls down UVLO threshold 2.85 3.0 3.15 V
Undervoltage Lockout
Hysteresis
UVLOhyst 30 50 70 mV
Overvoltage Lockout Threshold OVLO Vin rises up OVLO threshold 6.9 7.07 7.4 V
Overvoltage Lockout Hysteresis OVLOhyst 50 100 125 mV
Vin versus Vout Dropout Vdrop Vin = 5 V, I charge = 500 mA 105 200 mV
Supply Quiescent Current Idd No Load, Vin = 5.25 V 24 35 mA
OVLO Supply Current Iddovlo Vin = 8 V 50 85 mA
Output Off State Current Istd Vin = 5.25 V, EN = 1.2 V 26 37 mA
FLAG Output Low Voltage Volflag Vin > OVLO, Sink 1 mA on FLAG pin 400 mV
FLAG Leakage Current FLAGleak FLAG level = 5 V 5.0 nA
EN Voltage High Vih Vin from 3.3 V to 5.25 V 1.2 V
EN Voltage Low Vol Vin from 3.3 V to 5.25 V 0.4 V
EN Leakage Current ENleak EN = 5.5 V or GND 170 nA
TIMINGS
Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9 4.0 15 ms
FLAG going up Delay tstart From Vin > UVLO to FLAG = 1.2 V, See Fig 3 &
10
3.0 ms
Output Turn Off Time toff From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 & 11
Vin increasing from normal operation to >OVLO at
1V/ms. No output capacitor.
0.8 1.5 ms
Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 &
12
Vin increasing from normal operation to >OVLO at
1V/ms
1.0 2.0 ms
Disable Time tdis From EN 0.4 to 1.2V to Vout ≤ 0.3V, See Fig 5 &
13
Vin = 4.75 V. No output capacitor.
2.0 ms
Thermal Shutdown Temperature Tsd 150 °C
Thermal Shutdown Hysteresis Tsdhyst 30 °C
NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design.
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MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted, all parameters apply to both FETSW and
FETREG)
Characteristic Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(Br)DSS VGS = 0 V, ID = −250 mA−20 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(Br)DSS/TJ−15 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V
VDS = −16 V
TJ = 25°C−1.0 mA
TJ = 85°C−5.0
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "8.0 V "100 nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−0.45 −1.5 V
Gate Threshold Temperature Coefficient VGS(TH)/TJ2.7 mV/°C
Drain−to−Source On Resistance RDS(ON) VGS = −4.5 V, ID = −1.0 A 64 80 mW
VGS = −4.5 V, ID = −0.6 A 62 80
Forward Transconductance gFS VDS = −10 V, ID = −2.9 A 7.0 S
CHARGES, CAPACITANCES, AND GATE RESISTANCE
Input Capacitance CISS VGS = 0 V, f = 1.0 MHz,
VDS = −16 V
750 pF
Output Capacitance COSS 100
Reverse Transfer Capacitance CRSS 45
Total Gate Charge QG(TOT)
VGS = −4.5 V, VDS = −16 V,
ID = −2.6 A
7.6 8.6 nC
Gate−to−Source Charge QGS 1.3
Gate−to−Drain Charge QGD 2.6
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(ON)
VGS = −4.5 V, VDD = −16 V,
ID = −2.6 A, RG = 2.0 W
5.5 ns
Rise Time tr12
Turn−Off Delay Time td(OFF) 32
Fall Time tf23
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V, IS = −1.1 A −0.8 −1.2 V
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 1.0 A
20 ns
Charge Time ta 15
Discharge Time tb 5
Reverse Recovery Charge QRR 0.01 mC
2. Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures
Figure 5. Disable on EN a/c 6.FD$G
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1.2 V
FLAG
Vout
Vin UVLO
tstart
0.8 Vin
ton
<OVLO
Vin − RDS(on) x I
Figure 3. Start Up Sequence Figure 4. Shutdown on Over Voltage
Detection
Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1
1.2 V
FLAG
Vout
tdis
Vin − RDS(on) x I
EN
0.3 V
1.2 V
FLAG
Vin
EN
3 ms
UVLO
OVLO
FLA
G
Vout
Vin
OVLO
toff
0.3
V
tstop 0.4
V
Vin − (RDS(on) I)
Voltage Detection
IN OUT VIN > OVLO or VIN < UVLO
CONDITIONS
Figure 7.
Voltage Detection
IN OUT UVLO < VIN < OVLO
CONDITIONS
Figure 8.
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TYPICAL OPERATING CHARACTERISTICS
Figure 9. Startup
Vin = Ch1, Vout = Ch3
Figure 10. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 11. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 12. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 13. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
Figure 14. Thermal Shutdown
Vin = Ch1, Vout = Ch2, FLAG = Ch3
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TYPICAL OPERATING CHARACTERISTICS
Figure 15. Direct Output Short Circuit Figure 16. RDS(on) vs. Temperature
(Load = 500 mA)
Figure 17. Supply Quiescent Current vs. Vin
300
0−50 50 100 150
RDS(on) (mW)
TEMPERATURE (°C)
250
200
150
100
50
0
Vin = 3.6 V
450
Vin = 5 V
120
135791113
IQ, SUPPLY QUIESCENT CURRENT (mA)
Vin, INPUT VOLTAGE (V)
100
80
60
40
20
0
−40°C
140
350
400
160
180
15 17 19 21
125°C
25°C
'rJ :1oo>c
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TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
125°C
0
10
5
8
632
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−ID, DRAIN CURRENT (AMPS)
6
2
0
1
Figure 18. On−Region Characteristics
0 1.512
6
4
2
0.5
0
2.5
Figure 19. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.04
6
0.08
0
Figure 20. On−Resistance vs. Drain Current
and Gate Voltage
−ID, DRAIN CURRENT (AMPS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
Figure 21. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 22. Drain−to−Source Leakage Current
vs. Voltage
TJ = 25°C
0.2
23
TJ = −55°C
TJ = 25°C
VGS = −4.5 V
4
25°C
−1.4 V
−1.6 V
−2.4 V
−1.8 V
78
0.12
VGS = −10 V to −2.8 V
38
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10000
0.1
−IDSS, LEAKAGE (nA)
VGS = −4.5 V
1000
1
100
VGS = −2.5 V
46
4
8
0.16
5
TJ = 100°C
TJ = 125°C
2
9
7
5
1
3
4
9
5
3
1
7
−50 0−25 25
1.3
1.1
0.9
0.7
0.5
50 12510075 150
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1.5
VGS = 0 V
3 3.5
0.02
0.06
0.18
0.1
0.14
4
57
vGS : .a v SINGLE PULSE : 25°C — Rnsmm LIMIT
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TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
010
4
600
400
200
08
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
032
4
1
0
Qg, TOTAL GATE CHARGE (nC)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Coss
Ciss
Crss
ID = −2.7 A
TJ = 25°C
1000
65
2
3
Q2
Q1
101
10
1
100
RG, GATE RESISTANCE (OHMS)
t, TIME (ns)
VDD = −10 V
ID = −1.0 A
VGS = −4.5 V
1000
800
5
td(off)
td(on)
tf
tr
−VGS −VDS
6418
0.9
0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
−IS, SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
1.20.50.4
1
5
Figure 23. Capacitance Variation
Figure 24. Gate−to−Source and
Drain−to−Source Voltage vs. Total Gate Charge
Figure 25. Resistive Switching Time Variation
vs. Gate Resistance
Figure 26. Diode Forward Voltage vs. Current
Figure 27. Maximum Rated Forward Biased
Safe Operating Area
0.1 1 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.01
100
−ID, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
VGS = −8 V
SINGLE PULSE
TC = 25°C
1 ms
100 ms
dc
10 ms
2
700
500
300
100
900
7
QT
100
0.6 0.80.7
0.1
1
12 14 16 18 20
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
3
4
1.0 1.1
10 ms
, A v." (V) ‘ 20 v ovLo UVLO vaul OVLO UVLO
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Operational Description
The NUS6160 provides overvoltage protection for
positive voltages up to 20 V. A P−Channel FET protects the
load connected on the Vout pin, against positive overvoltage
conditions. The Output follows the VBUS level until OVLO
threshold is reached.
Undervoltage Lockout (UVLO)
To ensure proper operation under all conditions, the
device has a built−in undervoltage lock out (UVLO) circuit.
As the input ramps from 0 V, the output remains
disconnected from input until the Vin voltage is above 3.2 V
nominal. The FLAG output is pulled to low as long as Vin
does not reach the UVLO threshold. This circuit
incorporates hysteresis on the UVLO pin to provide noise
immunity to transient condition.
Figure 28. Output Characteristic vs. Vin
Overvoltage Lockout (OVLO)
To protect connected systems on Vout Pin from
overvoltage, the device has a built−in overvoltage lock out
(OVLO) circuit. During an overvoltage condition, the
output remains disabled until the input voltage is reduced to
below the OVLO hysteresis level. The FLAG output is tied
to low until Vin is higher than OVLO. This circuit
incorporates hysteresis on the OVLO pin to provide noise
immunity from transient conditions.
FLAG Output
The NUS6160 provides a FLAG output, which alerts
external systems that a fault has occurred. This pin goes low
as soon as the OVLO threshold is exceeded. When Vin level
recovers to its normal range the FLAG is set high.
The FLAG Pin is an open drain output, thus a pullup
resistor (typically 1 MW − Minimum 10 kW) must be
provided to Vbattery.
EN Input
To enable normal operation, the EN pin shall be forced
low or connected to ground. A high level on the pin
disconnects the OUT Pin from IN Pin. EN does not override
an OVLO or UVLO fault.
Internal PMOS FET
The NUS6160 includes an internal PMOS FET which
connects the input to the output pin. This FET is turned off
in the event of an overvoltage condition to protect the output
from a positive overvoltage condition. The low Rds(on),
during normal operation will minimize the voltage drop
across the device. (See Figure 16).
ESD Tests
The NUS6160 meets the requirements of the
IEC61000*4*2, level 4 (Input pin, 1 mF mounted on
board). For the air discharge condition, Vin is protected up
to $15 kV. In the contact condition, Vin is protected up to
±8 kV ESD. Please refer to Figure 29 to see the IEC
61000−4−2 electrostatic discharge waveform.
Figure 29. IEC 61000−4−2 Curve
Thermal Impedance
Due to cross heating of the three dice in the package, the
equivalent thetas are given for this device rather than the
individual thetas. To calculate the junction temperatures of
a single die, the total power must be used. For example,
given the following parameters, the die temperatures will be
as shown:
Idc = 500 mA
RDS(on) OVP = 305 mW
RDS(on) FETsw = 72 mW
FETreg has a 1.0 V Drop
Board copper area = 161 mm2
Calculate the individual power dissipations:
POVP = (0.50 A)2 x .305 W = 0.076 W
PSW = (0.50 A)2 x .072 W = 0.018 W
PREG = 0.50 A x 1.0 V = 0.50 W
PTOT = 0.076 + 0.018 + 0.50 = 0.594 W
From the Maximum ratings table for thetas, 161 mm2 and
1 V drop across FETREG:
OVP FET 53°C/W
FETSW 49°C/W
FETREG 92°C/W
The die temperature rises above ambient are:
TOVP = 53°C/W x 0.594 W = 32°C
TSW = 49°C/W x 0.594 W = 29°C
TREG = 92°C/W x 0.594 W = 55°C
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QFN22, 3x4, 0.5P
CASE 485AT−01
ISSUE B
DATE 17 SEP 2008
SCALE 2:1
PIN 1
REFERENCE
A
B
C0.15
C0.15
2X
2X
A
C
C0.08
25X
C0.10
SIDE VIEW
TOP VIEW
E4
D4
BOTTOM VIEW
b
22X
L
1
18
12
7
D
E
1
A3
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PADS AS WELL AS THE TERMINALS.
DIM MIN NOM
MILLIMETERS
A0.80 0.90
A1 0.00 0.025
A3 0.20 REF
b0.20 0.25
D3.00 BSC
D2 1.45 1.50
E4.00 BSC
E2 1.05 1.10
e0.50 BSC
K0.25 −−−
L0.30 0.325
0.10 B
0.05
AC
CNOTE 3
22X
K
16X
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXX
XXXXX
ALYWG
G
(Note: Microdot may be in either location)
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
NOTE 4 SEATING
PLANE
DETAIL B
L1 −−− −−−
G1.35 1.40
G1 0.95 1.05
G2 0.855 0.885
E3 1.30 1.35
E4 1.40 1.45
D3 0.52 0.57
D4 1.02 1.07
A1
A3
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTIONS
e
G2
D2
E3
E2
G
G
G1
D3
DETAIL A
SOLDERING FOOTPRINT*
0.50
0.52
22X
DIMENSIONS: MILLIMETERS
PITCH
22X
1
4.30
1.47
1.47
1.55
0.925
3.30
1.47
1.21
1.58
0.39
1.14
0.30
PACKAGE
OUTLINE
1.00
0.05
0.30
1.55
1.15
−−−
0.35
0.15
1.50
1.15
0.915
1.40
1.50
0.62
1.12
MAX
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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