Texas Instruments 的 LMH0307 规格书

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LMH0356

3G/HD/SD

SDI Reclocker

SDI In

ENABLE

SD/HD

Clock or

Second

Data Output

FAULT SDA SCL

LMH0307

3G/HD/SD

SDI Dual Cable Driver

Microcontroller

FPGA

SMBus

Data SMBus

Clock

SDI

SDI Out

LMH0307

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SNLS286I –APRIL 2008–REVISED APRIL 2013

3 Gbps HD/SD SDI Dual Output Cable Driver With Cable Detect

Check for Samples: LMH0307

1FEATURES DESCRIPTION

The LMH0307 3 Gbps HD/SD SDI Dual Output Cable

2• SMPTE 424M, SMPTE 292M, SMPTE 344M, and Driver with Cable Detect is designed for use in

SMPTE 259M Compliant SMPTE 424M, SMPTE 292M, SMPTE 344M, and

• Data Rates to 2.97 Gbps SMPTE 259M serial digital video applications. The

• Supports DVB-ASI at 270 Mbps LMH0307 implements two complementary output

drivers and drives 75Ωtransmission lines (Belden

• Cable Detect on Output 1694A, Belden 8281, or equivalent) at data rates up

• Loss of Signal Detect at Input to 2.97 Gbps.

• Output Driver Power Down Control The LMH0307 includes intelligent sensing capabilities

• Typical Power Consumption: 230 mW in SD to improve system diagnostics. The cable detect

Mode and 275 mW in HD Mode feature senses near-end termination to determine if a

cable is correctly attached to the output BNC. Input

• Power Save Mode Typical Power loss of signal (LOS) detects the presence of a valid

Consumption: 4 mW signal at the input of the cable driver. These sensing

• Single 3.3V Supply Operation features may be used to alert the user of a system

• Differential Input fault and activate a deep power save mode, reducing

the cable driver's power consumption to 4 mW. These

• Dual Complementary 75ΩOutputs features are accessible via an SMBus interface.

• Selectable Slew Rate The LMH0307 provides two selectable slew rates for

• Industrial Temperature Range: −40°C to +85°C SMPTE 259M and SMPTE 424M / 292M compliance.

• 16-Pin WQFN or 25-Ball CS-BGA package The output amplitude is adjustable ±10% in 5 mV

steps via the SMBus.

APPLICATIONS The LMH0307 is powered from a single 3.3V supply.

• SMPTE 424M, SMPTE 292M, SMPTE 344M, and Power consumption is typically 230 mW in SD mode

SMPTE 259M Serial Digital Interfaces and 275 mW in HD mode. The LMH0307 is available

• Digital Video Routers and Switches in two space-saving packages: a 4 x 4 mm 16-pin

WQFN and even more space-efficient 3 x 3 mm 25-

• Distribution Amplifiers ball CS-BGA package.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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SDO0

SD/HD

ENABLE SCL

RREF

SDO0

SDA

RSTI

RSTO FAULTSDO1

VEE

A5A

12345

LMH0307GR

(top view)

SDI

SDI SDO1

VEE VEE VEE VEE

NC VCC

RREF NC

2LMH0307SQ

(top view)

85 6 7

1316 15 14

VEE

SDI

SDI SDO0

SD/HD

VCC

ENABLE

SCL

RREF

SDO0

SDA

RSTI RSTO

FAULT

SDO1

LMH0307

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Connection Diagram

The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative

power supply voltage.

Figure 1. 16-Pin WQFN

Package Number RUM

Figure 2. 25-Ball CS-BGA

Package Number NYA

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PIN DESCRIPTIONS

WQFN Pin CS-BGA Ball Name Description

1 A1 SDI Serial data true input.

2 B1 SDI Serial data complement input.

4 D1, E1 RREF Bias resistor. Connect a 750Ωresistor to VCC (also connect D1 to E1 on CS-BGA

version).

5 D2 RSTI Reset input. RSTI has an internal pullup.

H = Normal operation.

L = Device reset. The device operates with default register settings. Forcing RSTI low

also forces RSTO low.

6 E2 ENABLE Output driver enable. ENABLE has an internal pullup.

H = Normal operation.

L = Output driver powered off.

7 E3 SDA SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin

requires an external pullup.

8 E4 SCL SMBus clock input. SCL is input only. This pin requires an external pullup.

10 D5 SD/HD Output slew rate control. SD/HD has an internal pulldown.

H = Output rise/fall time complies with SMPTE 259M.

L = Output rise/fall time complies with SMPTE 424M / 292M.

11 C5 SDO0 Serial data output 0 complement output.

12 B5 SDO0 Serial data output 0 true output.

13 A5 FAULT Fault open drain output flag. Requires external pullup resistor and may be wire ORed

with multiple cable drivers.

H = Normal operation.

L = Loss of signal or termination fault for any output.

14 A4 SDO1 Serial data output 1 true output.

15 A3 SDO1 Serial data output 1 complement output.

16 A2 RSTO Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset

back to zero by forcing RSTI to zero to reset the device. Used to daisy chain multiple

cable drivers on the same SMBus.

9 D4 VCC Positive power supply (+3.3V).

DAP, 3 B2, B4, C1, VEE Negative power supply (ground).

C2, C3, C4

— B3, D3, E5 NC No connect.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)

Supply Voltage −0.5V to 3.6V

Input Voltage (all inputs) −0.3V to VCC+0.3V

Output Current 28 mA

Storage Temperature Range −65°C to +150°C

Junction Temperature +125°C

Lead Temperature (Soldering 4 Sec) +260°C

Package Thermal Resistance θJA 16-pin WQFN +43°C/W

θJC 16-pin WQFN +7°C/W

θJA 25-ball CS-BGA +67.6°C/W

ESD Rating HBM 8 kV

MM 400V

CDM 2 kV

(1) "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The

stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.

The table of Electrical Characteristics specifies acceptable device operating conditions.

Recommended Operating Conditions

Supply Voltage (VCC – VEE) 3.3V ±5%

Operating Free Air Temperature (TA)−40°C to +85°C

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DC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2).

Symbol Parameter Conditions Reference Min Typ Max Units

VCMIN Input Common Mode Voltage SDI, SDI 1.6 + VCC –V

VSDI/2 VSDI/2

VSDI Input Voltage Swing Differential 100 2200 mVP−P

VCMOUT Output Common Mode Voltage SDO, SDO VCC –V

VSDO

VSDO Output Voltage Swing Single-ended, 75Ωload, 720 800 880 mVP-P

RREF = 750Ω1%

VIH Input Voltage High Level SD/HD, 2.0 V

ENABLE

VIL Input Voltage Low Level 0.8 V

ICC Supply Current SD/HD = 0, 84 100 mA

SDO/SDO enabled

SD/HD = 1, 70 77 mA

SDO/SDO enabled

SDO/SDO disabled 1.3 2.5 mA

SMBus DC Specifications

VSIL Data, Clock Input Low Voltage 0.8 V

VSIH Data, Clock Input High Voltage 2.1 VSDD V

Current through pullup resistor or

ISPULLUP VOL = 0.4V 4 mA

current source

VSDD Nominal Bus Voltage 3.0 3.6 V

ISLEAKB Input Leakage per bus segment (3) −200 200 µA

ISLEAKP Input Leakage per pin −10 10 µA

CSI Capacitance for SDA and SCL (3)(4) 10 pF

(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated

referenced to VEE = 0 Volts.

(2) Typical values are stated for VCC = +3.3V and TA= +25°C.

(3) Recommended value — Parameter not tested.

(4) Recommended maximum capacitive load per bus segment is 400 pF.

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AC Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1).

Symbol Parameter Conditions Reference Min Typ Max Units

DRSDI Input Data Rate SDI, SDI 2970 Mbps

tjit Additive Jitter 2.97 Gbps SDO, SDO 20 psP-P

1.485 Gbps 18 psP-P

270 Mbps 15 psP-P

tr,tfOutput Rise Time, Fall Time SD/HD = 0, 20% – 80%, 90 130 ps

SD/HD = 1, 20% – 80% 400 800 ps

Mismatch in Rise/Fall Time SD/HD = 0 30 ps

SD/HD = 1 50 ps

Duty Cycle Distortion SD/HD = 0, 2.97 Gbps(2) 27 ps

SD/HD = 0, 1.485 Gbps(2) 30 ps

SD/HD = 1(2) 100 ps

tOS Output Overshoot SD/HD = 0(2) 10 %

SD/HD = 1(2) 8 %

tSK SDO1 to SDO0 Skew SD/HD = 0(2) 8 ps

SD/HD = 1(2) 54 ps

RLSDO Output Return Loss 5 MHz - 1.5 GHz(3) 15 dB

1.5 GHz - 3.0 GHz(3) 10 dB

SMBus AC Specifications

fSMB Bus Operating Frequency 10 100 kHz

tBUF Bus free time between Stop 4.7 µs

and Start Condition

tHD:STA Hold time after (repeated) Start At ISPULLUP = MAX

Condition. After this period, the 4.0 µs

first clock is generated.

tSU:STA Repeated Start Condition setup 4.7 µs

time

tSU:STO Stop Condition setup time 4.0 µs

tHD:DAT Data hold time 300 ns

tSU:DAT Data setup time 250 ns

tLOW Clock low period 4.7 µs

tHIGH Clock high period 4.0 50 µs

tFClock/Data Fall Time 300 ns

tRClock/Data Rise Time 1000 ns

tPOR Time in which device must be 500 ms

operational after power on

(1) Typical values are stated for VCC = +3.3V and TA= +25°C.

(2) Specification is ensured by characterization.

(3) Output return loss is dependent on board design. The LMH0307 meets this specification on the SD307 evaluation board.

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tBUF tHD:STA

tLOW

tHD:DAT

tHIGH

tFtSU:DAT

ST SP

tSU:STO

SCL

SDA

tSU:STA

LMH0307

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TIMING DIAGRAM

Figure 3. SMBus Timing Parameters

DEVICE OPERATION

INPUT INTERFACING

The LMH0307 accepts either differential or single-ended input. For single-ended operation, the unused input

must be properly terminated.

OUTPUT INTERFACING

The LMH0307 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75ΩAC-coupled

coaxial cable with an RREF resistor of 750Ω. The RREF resistor is connected between the RREF pin and VCC. The

only resistor value that should be used for RREF is 750Ω.

The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane

layers below the RREF network should be removed to minimize parasitic capacitance.

OUTPUT SLEW RATE CONTROL

The LMH0307 output rise and fall times are selectable for either SMPTE 259M or SMPTE 424M / 292M

compliance via the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set high.

For faster rise and fall times, or SMPTE 424M and SMPTE 292M compliance, SD/HD is set low. SD/HD may

also be controlled using the SMBus, provided the SD/HD pin is held low. SD/HD has an internal pulldown.

OUTPUT ENABLE

The SDO0/SDO0 and SDO1/SDO1output drivers can be enabled or disabled with the ENABLE pin. When set

low, both output drivers are powered off and the LMH0307 enters a deep power save mode. ENABLE has an

internal pullup.

INPUT LOSS OF SIGNAL DETECTION (LOS)

The LMH0307 detects when the input signal does not have a video-like pattern. Self oscillation and low levels of

noise are rejected. This loss of signal detect allows a very sensitive input stage that is robust against coupled

noise without any degradation of jitter performance.

Via the SMBus, the loss of signal detect can either add an input offset or mute the outputs. An offset is added by

default. Additionally, the loss of signal detect can be linked to the ENABLE functionality so that when the LOS

goes low, ENABLE will also go low.

OUTPUT CABLE DETECTION

The LMH0307 detects when an output is locally terminated. When a video signal (or AC test signal) is present on

SDI, the device senses the SDO and SDO amplitudes. If the output is not properly terminated (via a terminated

cable or local termination), the amplitude will be higher than expected, and the Termination Fault signal is

asserted. The Termination Fault signal is de-asserted when the proper termination is applied. This feature allows

the system designer the flexibility to react to cable attachment and removal. Note that a long length of cable will

look like a proper termination at the device output.

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The cable driver must be enabled for the termination detection to operate. If the Termination Fault will be used to

power down the LMH0307, then periodic polling (enabling) is recommended to monitor the output termination.

For example, when a Fault condition is triggered, ENABLE can be driven low to power down the device. The

LMH0307 should be re-enabled periodically to check the status of the output termination. The LMH0307 needs to

be powered on for roughly 4 ms for Termination Fault detection to work.

SMBUS INTERFACE

The System Management Bus (SMBus) is a two-wire interface designed for the communication between various

system component chips. By accessing the control functions of the circuit via the SMBus, pin count is kept to a

minimum while allowing a maximum amount of versatility. The LMH0307 has several internal configuration

registers which may be accessed via the SMBus.

The 7-bit default address for the LMH0307 is 17h. The LSB is set to 0b for a WRITE and 1b for a READ, so the

8-bit default address for a WRITE is 2Eh and the 8-bit default address for a READ is 2Fh. The SMBus address

may be dynamically changed.

In applications where there might be several LMH0307s, the SDA, SCL, and FAULT pins can be shared. The

SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0307s may have

the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination

faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be

masked from the FAULT pin.

TRANSFER OF DATA VIA THE SMBus

During normal operation the data on SDA must be stable during the time when SCL is High.

There are three unique states for the SMBus:

START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.

STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.

IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they

are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.

SMBus TRANSACTIONS

The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read

Only), default value and function information.

WRITING A REGISTER

To write a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drives the 8-bit data byte.

6. The Device drives an ACK bit (“0”).

7. The Host drives a STOP condition.

The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may

now occur.

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READING A REGISTER

To read a register, the following protocol is used (see SMBus 2.0 specification).

1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.

2. The Device (Slave) drives the ACK bit (“0”).

3. The Host drives the 8-bit Register Address.

4. The Device drives an ACK bit (“0”).

5. The Host drives a START condition.

6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.

7. The Device drives an ACK bit “0”.

8. The Device drives the 8-bit data value (register contents).

9. The Host drives a NACK bit “1”indicating end of the READ transfer.

10. The Host drives a STOP condition.

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75:

75:

75:

75:

75:

Coaxial Cable

4.7 PF

6.8 nH

SCL

LMH0307

VEE

SDI

SDI SDO0

SD/HD

VCC

ENABLE

SCL

RREF

SDO0

SDA

RSTI RSTO

FAULT

49.9:

Differential

Input

750:

VCC

ENABLE

RSTI

SDA

VCC

VCC 10 k: 10 k:

SD/HD

10 k:

VCC

RSTO

FAULT

VCC

0.1 PF

4 9

8 13

0.1 PF

SDO1

75:

75:

75:

75:

75:

Coaxial Cable

4.7 PF

6.8 nH

VCC

0.1 PF

DAP

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APPLICATION INFORMATION

Figure 4 shows the application circuit for the LMH0307.

Figure 4. Application Circuit

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Host

(e.g. FPGA)

LVCMOS GPIO

SMBus Interface

LMH0307

GPO

SCL

SDA

RSTI RSTO

SCL

SDA

LMH0307

RSTI RSTO

SCL

SDA

LMH0307

RSTI RSTO

SCL

SDA

3.3V

LMH0307

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COMMUNICATING WITH MULTIPLE LMH0307 CABLE DRIVERS VIA THE SMBus

A common application for the LMH0307 will utilize multiple cable driver devices. Even though the LMH0307

devices all have the same default SMBus device ID (address), it is still possible for them share the SMBus

signals as shown in Figure 5. A third signal is required from the host to the first device. This signal acts as a

“Enable / Reset” signal. Additional LMH0307s are controlled from the upstream device. In this control scheme,

multiple LMH0307s may be controlled via the two-wire SMBus and the use of one GPO (General Purpose

Output) signal. Other SMBus devices may also be connected to the two wires, assuming they have their own

unique SMBus addresses.

Figure 5. SMBus Configuration for Multiple LMH0307 Cable Drivers

The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0307

RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next

device and so on.

The procedure at initialization is to:

1. Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the

next device in RESET in the chain.

2. Raise the host GPO signal to LMH0307 #1 RSTI input pin.

3. Write to Address 8’h2E (7’h17) Register 0 with the new address value (e.g. 8’h2C (7’h16).

4. Upon writing Register 0 in LMH0307 #1, its RSTO signal will switch High. Its new address is 8’h2C (7’h16),

and the next LMH0307 in the chain will now respond to the default address of 8’h2E (7’h17).

5. The process is repeated until all LMH0307 devices have a unique address loaded.

6. Direct SMBus writes and reads may now take place between the host and any addressed device.

The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of

the LMH0307 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the

bus have unique device IDs.

If power is toggled to the system, the SMBus address routine needs to be repeated.

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Table 1. SMBus Registers

Address R/W Name Bits Field Default Description

00h R/W ID 7:1 DEVID 0010111 Device ID. Writing this register will force the

RSTO pin high. Further accesses to the

device must use this 7-bit address.

0 RSVD 0 Reserved as 0. Always write 0 to this bit.

01h R STATUS 7:5 RSVD 000 Reserved.

4 TF1N 0 Termination Fault for SDI1.

0: No Termination Fault Detected.

1: Termination Fault Detected.

3 TF1P 0 Termination Fault for SDI1.

0: No Termination Fault Detected.

1: Termination Fault Detected.

2 TF0N 0 Termination Fault for SDI0.

0: No Termination Fault Detected.

1: Termination Fault Detected.

1 TF0P 0 Termination Fault for SDI0.

0: No Termination Fault Detected.

1: Termination Fault Detected.

0 LOS 0 Loss Of Signal (LOS) detect at input.

0: No Signal Detected.

1: Signal Detected.

02h R/W MASK 7 SD 0 SD Rate select bit. If the SD/HD pin is set

to VCC, it overrides this bit. With the SD/HD

pin set to ground, this bit selects the output

edge rate as follows:

0: HD edge rate.

1: SD edge rate.

6 PD1 0 Power Down for SDO1 output stage. If the

ENABLE pin is set to ground, it overrides

this bit. With the ENABLE pin set to VCC,

PD1 functions as follows:

0: SDO1 active.

1: SDO1 powered down.

5 PD0 0 Power Down for SDO0 output stage. If the

ENABLE pin is set to ground, it overrides

this bit. With the ENABLE pin set to VCC,

PD0 functions as follows:

0: SDO0 active.

1: SDO0 powered down.

4 MTF1N 0 Mask TF1N from affecting FAULT pin.

0: TF1N=1 will cause FAULT to be 0.

1: TF1N=1 will not affect FAULT; the

condition is masked off.

3 MTF1P 0 Mask TF1P from affecting FAULT pin.

0: TF1P=1 will cause FAULT to be 0.

1: TF1P=1 will not affect FAULT; the

condition is masked off.

2 MTF0N 0 Mask TF0N from affecting FAULT pin.

0: TF0N=1 will cause FAULT to be 0.

1: TF0N=1 will not affect FAULT; the

condition is masked off.

1 MTF0P 0 Mask TF0P from affecting FAULT pin.

0: TF0P=1 will cause FAULT to be 0.

1: TF0P=1 will not affect FAULT; the

condition is masked off.

0 MLOS 0 Mask LOS from affecting FAULT pin.

0: LOS=0 will cause FAULT to be 0.

1: LOS=0 will not affect FAULT; the

condition is masked off.

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Table 1. SMBus Registers (continued)

Address R/W Name Bits Field Default Description

03h R/W DIRECTION 7 HDTF0ThreshLSB 1 Least Significant Bit for HDTF0Thresh

detection threshold. Combines with

HDTF0Thresh bits in register 04h.

6 SDTF0ThreshLSB 1 Least Significant Bit for SDTF0Thresh

detection threshold. Combines with

SDTF0Thresh bits in register 05h.

5 RSVD 0 Reserved as 0. Always write 0 to this bit.

4 DTF1N 0 Direction of TF1N that affects FAULT pin

(when not masked).

0: TF1N=1 will cause FAULT to be 0 (when

the condition is not masked off).

1: TF1N=0 will cause FAULT to be 0 (when

the condition is not masked off).

3 DTF1P 0 Direction of TF1P that affects FAULT pin

(when not masked).

0: TF1P=1 will cause FAULT to be 0 (when

the condition is not masked off).

1: TF1P=0 will cause FAULT to be 0 (when

the condition is not masked off).

2 DTF0N 0 Direction of TF0N that affects FAULT pin

(when not masked).

0: TF0N=1 will cause FAULT to be 0 (when

the condition is not masked off).

1: TF0N=0 will cause FAULT to be 0 (when

the condition is not masked off).

1 DTF0P 0 Direction of TF0P that affects FAULT pin

(when not masked).

0: TF0P=1 will cause FAULT to be 0 (when

the condition is not masked off).

1: TF0P=0 will cause FAULT to be 0 (when

the condition is not masked off).

0 DLOS 0 Direction of LOS that affects FAULT pin

(when not masked).

0: LOS=0 will cause FAULT to be 0 (when

the condition is not masked off).

1: LOS=1 will cause FAULT to be 0 (when

the condition is not masked off).

04h R/W OUTPUT0 7:5 HDTF0Thresh 100 Sets the Termination Fault threshold for

SDO0, when SD is set to HD rates (0).

Combines with HDTF0ThreshLSB in

1001).

4:0 AMP0 10000 SDO0 output amplitude in roughly 5 mV

steps.

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Table 1. SMBus Registers (continued)

Address R/W Name Bits Field Default Description

05h R/W OUTPUT0CTRL 7 RSVD 0 Reserved as 0. Always write 0 to this bit.

6 FLOSOF 0 Force LOS to always OFF in regard to its

effect on the output signal. This forces the

device into either the mute or “add offset”

state. The LOS bit in register 01h still

reflects the correct state of LOS.

0: LOS operates normally, muting or adding

offset as specified by the MUTE bit.

1: Muting or adding offset is always in place

as specified by the MUTE bit.

5 FLOSON 0 Force LOS to always ON in regard to its

effect on the output signal. This prevents

the device from muting or adding offset.

The LOS bit in register 01h still reflects the

correct state of LOS.

0: LOS operates normally, muting or adding

offset as specified in the MUTE bit.

1: Muting or adding offset never occurs.

4 LOSEN 0 Configures LOS to be combined with the

ENABLE functionality.

0: Only the PD bits and ENABLE pin affect

the power down state of the output drivers.

1: If the ENABLE pin is set to ground, it

powers down the output drivers regardless

of the state of LOS or the PD bits. With the

ENABLE pin set to VCC, LOS=0 will power

down the output drivers, and LOS=1 will

leave the power down state dependent on

the PD bits.

3 MUTE 0 Selects whether the device will MUTE when

loss of signal is detected or add an offset to

prevent self oscillation. When an input

signal is detected (LOS=1), the device will

operate normally.

0: Loss of signal will force a small offset to

prevent self oscillation.

1: Loss of signal will force the channel to

MUTE.

2:0 SDTF0Thresh 010 Sets the Termination Fault threshold for

SDO0, when SD is set to SD rates (1).

Combines with SDTF0ThreshLSB in

0101).

06h R/W OUTPUT1 7:5 HDTF1Thresh 100 Sets the Termination Fault threshold for

SDO1, when SD is set to HD rates (0).

Combines with HDTF1ThreshLSB in

1001).

4:0 AMP1 10000 SDO1 output amplitude in roughly 5 mV

steps.

07h R/W OUTPUT1CTRL 7 HDTF1ThreshLSB 1 Least Significant Bit for HDTF1Thresh

detection threshold. Combines with

HDTF1Thresh bits in register 06h.

6 SDTF1ThreshLSB 1 Least Significant Bit for SDTF1Thresh

detection threshold. Combines with

SDTF1Thresh bits in register 07h.

5:3 RSVD 011 Reserved as 011. Always write 011 to these

bits.

2:0 SDTF1Thresh 010 Sets the Termination Fault threshold for

SDO1, when SD is set to SD rates (1).

Combines with SDTF1ThreshLSB in bit 6

(default for combined value is 0101).

Product Folder Links: LMH0307

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LMH0307

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SNLS286I –APRIL 2008–REVISED APRIL 2013

Table 1. SMBus Registers (continued)

Address R/W Name Bits Field Default Description

08h R/W TEST 7:5 CMPCMD 000 Compare command. Determines whether

the peak value or the current value of the

Termination Fault counters is read in

registers 0Ah-0Dh.

000: Resets compare value to 00; registers

0Ah-0Dh all show current counter values.

Sets detection to look for MAX peak values.

001: Capture counter 0. Register 0Ah

shows peak value.

010: Capture counter 1. Register 0Bh

shows peak value.

011: Capture counter 2. Register 0Ch

shows peak value.

100: Capture counter 3. Register 0Dh

shows peak value.

101: Resets compare value to 1Fh. Sets

detection to look for MIN peak values.

110, 111: Reserved.

4:0 RSVD 00000 Reserved as 00000. Always write 00000 to

these bits.

09h R REV 7:5 RSVD 000 Reserved.

4:3 DIEREV 10 Die Revision.

2:0 PARTID 010 Part Identifier. Note that single output

devices (LMH0303) have the LSB=1. Dual

output devices (LMH0307) have the LSB=0.

0Ah R TF0PCOUNT 7:5 RSVD 000 Reserved.

4:0 TF0PCOUNT 00000 This is either the current value of TF0P

Counter, or the peak value of the counter,

depending on CMPCMD in register 08h.

0Bh R TF0NCOUNT 7:5 RSVD 000 Reserved.

4:0 TF0NCOUNT 00000 This is either the current value of TF0N

Counter, or the peak value of the counter,

depending on CMPCMD in register 08h.

0Ch R TF1PCOUNT 7:5 RSVD 000 Reserved.

4:0 TF1PCOUNT 00000 This is either the current value of TF1P

Counter, or the peak value of the counter,

depending on CMPCMD in register 08h.

0Dh R TF1NCOUNT 7:5 RSVD 000 Reserved.

4:0 TF1NCOUNT 00000 This is either the current value of TF1N

Counter, or the peak value of the counter,

depending on CMPCMD in register 08h.

Product Folder Links: LMH0307

l TEXAS INSTRUMENTS

LMH0307

SNLS286I –APRIL 2008–REVISED APRIL 2013

www.ti.com

REVISION HISTORY

Changes from Revision H (April 2013) to Revision I Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 15

Product Folder Links: LMH0307

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMH0307GRE/NOPB ACTIVE csBGA NYA 25 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 307G

LMH0307SQ/NOPB ACTIVE WQFN RUM 16 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L0307

LMH0307SQE/NOPB ACTIVE WQFN RUM 16 250 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L0307

LMH0307SQX/NOPB ACTIVE WQFN RUM 16 4500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 L0307

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«m» Reel Diameter AD Dimension deswgned to accommodate the componem wwdlh ED Dimension desxgned to accommodate the componenl \engm K0 Dimenslun deswgned to accommodate the componem thickness , w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D Sprockemules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMH0307GRE/NOPB csBGA NYA 25 250 178.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1

LMH0307SQ/NOPB WQFN RUM 16 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LMH0307SQE/NOPB WQFN RUM 16 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LMH0307SQX/NOPB WQFN RUM 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2021

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMH0307GRE/NOPB csBGA NYA 25 250 208.0 191.0 35.0

LMH0307SQ/NOPB WQFN RUM 16 1000 208.0 191.0 35.0

LMH0307SQE/NOPB WQFN RUM 16 250 208.0 191.0 35.0

LMH0307SQX/NOPB WQFN RUM 16 4500 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2021

Pack Materials-Page 2

:5 w 7.—+—. w r‘j h 3 gomoééw 3 , 0000 W 3 p 00000 3 3 M nu m Conn A ‘ m 000001 777777 700000 magnum: gm‘aﬂ WWWJ - mMmsloNs ARE IN MlllIMHERS [was Ms ”4‘ we» n[r:v[u;[ om ' TEXAS INSTRUMENTS

MECHANICAL DATA

NYA0025A

www.ti.com

GRA25A (Rev A)

--I ,,A,J EA ,ﬁrn,, W @m : Aw D i , E :E E \M‘ 7 ﬂ kawfm‘ kéu i H iMr \ , H i 3 3/ 4 A W- W R, YLET

www.ti.com

PACKAGE OUTLINE

4.1

3.9

4.1

3.9

0.8

0.7

0.05

0.00

2X 1.95

12X 0.65

2X 1.95

16X 0.5

0.3

16X 0.35

0.25

2.6 0.1

(DIM A) TYP

WQFN - 0.8 mm max heightRUM0016A

PLASTIC QUAD FLATPACK - NO LEAD

4214998/A 11/2021

DIM A

OPT 1 OPT 2

0.2 0.1

0.08 C

0.1 C A B

0.05

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

(45 X 0.3)

SYMM

EXPOSED

THERMAL PAD

SYMM

SCALE 3.000

www.ti.com

EXAMPLE BOARD LAYOUT

12X (0.65)

(1.05)

(R0.05) TYP

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

16X (0.6)

16X (0.3)

(3.8)

( 2.6)

( 0.2) TYP

VIA

WQFN - 0.8 mm max heightRUM0016A

PLASTIC QUAD FLATPACK - NO LEAD

4214998/A 11/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

SEE SOLDER MASK

DETAIL

METAL EDGE

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DEFINED

SOLDER MASK DETAILS

www.ti.com

EXAMPLE STENCIL DESIGN

16X (0.6)

16X (0.3)

12X (0.65)

(3.8)

(0.675) TYP

4X ( 1.15)

(R0.05) TYP

WQFN - 0.8 mm max heightRUM0016A

PLASTIC QUAD FLATPACK - NO LEAD

4214998/A 11/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 17

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SYMM

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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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