Bourns Inc. 的 C650, C850 Series 规格书

Formerly FulTEc A
Features
■ Formerly brand
■ Extremely high speed performance
■ Blocks high voltages and currents
■ Very high bandwidth; GHz compatible
■ Small package, minimal PCB area
■ Simple, superior circuit protection
■ RoHS compliant*, UL Recognized
C650 and C850 Series TBU® High-Speed Protectors
Transient Blocking Units - TBU® Devices
Bourns® C650 and C850 series products are high-speed
bidirectional protection components, constructed using
MOSFET semiconductor technology, designed to protect
against faults caused by short circuits, AC power cross,
induction and lightning surges.
The TBU® high-speed protector, triggering as a function of
the MOSFET, blocks surges and provides an effective barrier
behind which sensitive electronics are not exposed to large
voltages or currents during surge events. The TBU® device is
provided in a surface mount DFN package and meets industry
standard requirements such as RoHS and Pb Free solder
refl ow profi les.
Electrical Characteristics (Tamb = 25 °C)
C650 and C850 TBU® High-Speed Protectors are bidirectional;
specifi cations are valid in both directions.
Symbol Parameter Min. Typ. Max. Unit
Iop
Maximum current through the device that will not cause
current blocking
Cx50-100-WH
Cx50-180-WH
Cx50-260-WH
100
180
260
mA
Itrigger
Typical current for the device to go from normal operating
state to protected state
Cx50-100-WH
Cx50-180-WH
Cx50-260-WH
150
220
330
mA
Iout Maximum current through the device
Cx50-100-WH
Cx50-180-WH
Cx50-260-WH
200
360
520
mA
Rdevice Series resistance of the TBU® device
C650-100-WH
C650-180-WH
C650-260-WH
C850-100-WH
C850-180-WH
C850-260-WH
12
8
8
17
11
11
14.5
10
10
19
14
14
Ω
tblock
Maximum time for the device to go from normal operating
state to protected state sμ1
Iquiescent
Current through the triggered TBU® device with 50 Vdc circuit
voltage 1mA
Vreset Voltage below which the triggered TBU® device will transition to
normal operating state 14 V
Absolute Maximum Ratings (Tamb = 25 °C)
Symbol Parameter Value Unit
Vimp Maximum protection voltage for impulse faults with rise time ≥ 1 μsec C650-xxx-WH
C850-xxx-WH
650
850 V
Vrms Maximum protection voltage for continuous Vrms faults C650-xxx-WH
C850-xxx-WH
300
425 V
Top Operating temperature range -40 to +85 °C
Tstg Storage temperature range -65 to +150 °C
Agency Approval
UL recognized component File # E315805.
Industry Standards
Description Model
Telcordia
GR-1089 Port Type 1, 3, 5 C650
C850
GR-974 C650
C850
ITU-T K.20, K.20E, K.21, K.21E, K.45 C850
*RoHS COMPLIANT
The C650 & C850 Series are currently
available, but not recommended for
new designs. Bourns® TBU-CA
Series is preferred.
*RoHS Directive 2002/95/EC Jan. 27, 2003 including annex and RoHS Recast 2011/65/EU June 8, 2011.
Specifications are subject to change without notice. Users should verify actual device performance in their specific
applications. The products described herein and this document are subject to specific legal disclaimers as set forth on the
last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
WARNING Cancer and Reproductive Harm
www.P65Warnings.ca.gov
BOURNS' ‘mgger rrrrrrrrrrr 'vaset Vrese‘ """"" "mggev
Typical Performance Characteristics
C650 and C850 Series TBU® High-Speed Protectors
V-I Characteristics Time to Block vs. Fault Current
Current vs. Temperature
-Itrigger
Vreset
-Vreset
Itrigger
+V
+I
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
0.1 1 10 100 1000
Fault Current (A )
Time to Block (sec)
20
40
60
80
100
120
140
-40 -20 0 20 40 60 80
Temperature (°C)
% of Current
Applications
■ Combo voice / xDSL linecards
■ Voice linecards
■ MDF, primary protection modules
■ Process control equipment
■ Test and measurement equipment
■ General electronics
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
BOURNS' —-—E—-—|:
TEST CONFIGURATION DIAGRAM V1 V2 Load
C650 and C850 Series TBU® High-Speed Protectors
Operational Characteristics
C650 Lightning, 650 V C850 Lightning, 850 V
The graphs below demonstrate the operational characteristics of the TBU® protector. For each graph the fault voltage, protected side
voltage, and current is presented.
C650 Power Fault, 300 Vrms, 100 A C850 Power Fault, 425 Vrms, 100 A
1 μs/div.
100 V/div.
400 mA/div.
Ch1 V1 Ch2 V2 Ch3 Current
1
3
2
1 μs/div.
100 V/div.
400 mA/div.
Ch1 V1 Ch2 V2 Ch3 Current
1
3
2
4 ms/div.
100 V/div.
200 mA/div.
Ch1 V1 Ch2 V2 Ch3 Current
1
2
3
4 ms/div.
100 V/div.
200 mA/div.
Ch1 V1 Ch2 V2 Ch3 Current
1
2
3
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
BOURNS Bawfipqflfiifl fi * * Ha am 3‘; m E a, \a Temperalure(”0) law cm Dawn 147 A25 CwPam 4» Tune (Seconds)
C650 and C850 Series TBU® High-Speed Protectors
Product Dimensions
321
PIN 1
TOP VIEW SIDE VIEW BOTTOM VIEW
C
A1 SEATING PLANE
BD
A
HH
K
K
F
D
J
J
E
XXXXX
YWWLL
DIMENSIONS: MM
(INCHES)
Dim. Min. Typ. Max.
A0.80
(.031)
0.90
(.035)
1.00
(.039)
A1 0.00
(.000)
0.025
(.001)
0.050
(.002)
B8.15
(.321)
8.25
(.325)
8.35
(.329)
C 3.90
(.154)
4.00
(.157)
4.10
(.161)
D 2.55
(.100)
2.60
(.102)
2.65
(.104)
E1.10
(.043)
1.15
(.045)
1.20
(.047)
F3.45
(.136)
3.50
(.138)
3.55
(.140)
H0.20
(.008)
0.25
(.010)
0.30
(.012)
J0.65
(.026)
0.70
(.028)
0.75
(.030)
K0.20
(.008)
0.25
(.010)
0.30
(.012)
Recommended Pad Layout
3.55
(.140)
0.70
(.028)
1.15
(.045)
2.625
(.103)
Pad # Apply
1 In/Out
2NC
3 In/Out
NC = Solder to PCB; do not make electrical
connection, do not connect to ground.
Pad Designation
TBU® protectors have matte-tin termination fi nish. Suggested layout should use non-solder mask defi ne (NSMD). Recommended stencil thick-
ness is 0.10-0.12 mm (.004-.005 in.) with stencil opening size 0.025 mm (.0010 in.) less than the device pad size. As when heat sinking any
power device, it is recommended that, wherever possible, extra PCB copper area is allowed. For minimum parasitic capacitance, do not allow
any signal, ground or power signals beneath any of the pads of the device.
Thermal Resistances
Symbol Parameter Value Unit
Rth(j-a) Junction to leads (package) 116 °C/W
Refl ow Profi le
ProfiylbmessA eerF-bP erutaeF el
Average Ramp-Up Rate (Tsmax to Tp) 3 °C/sec. max.
Preheat
- Temperature Min. (Tsmin)
- Temperature Max. (Tsmax)
- Time (tsmin to tsmax)
150 °C
200 °C
60-180 sec.
Time maintained above:
- Temperature (TL)
- Time (tL)
217 °C
60-150 sec.
Peak/Classifi cation Temperature (Tp) 260 °C
Time within 5 °C of Actual Peak Temp. (tp) 20-40 sec.
.xam .ces/C° 6 etaR nwoD-pmaR
Time 25 °C to Peak Temperature 8 min. max.
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
BOURNS' \ 102 16,5 20.2 13,5 12,8 25 1.5 330.25 326
C650 and C850 Series TBU® High-Speed Protectors
Typical Part MarkingHow to Order
C 650 - 180 - WH
Form Factor
C = One TBU® protector in the device
Impulse Voltage Rating
650 = 650 V
850 = 850 V
Iop Indicator
100 = 100 mA
180 = 180 mA
260 = 260 mA
Packaging Specifi cations (per EIA468-B)
B
A
DC
NF
G (MEASURED AT HUB)
USER DIRECTION OF FEED
K0
B0
P2
D1
CENTER
LINES OF
CAVITY
EMBOSSMENT
tD
P0
TOP
COVER
TAPE
E
W
P
A0
DIMENSIONS: MM
(INCHES)
Device A B C D G N
Min. Max. Min. Max. Min. Max. Min. Max. Ref. Ref.
C650, C850 326
(12.835)
330.25
(13.002)
1.5
(.059)
2.5
(.098)
12.8
(.504)
13.5
(.531)
20.2
(.795) - 16.5
(.650)
102
(4.016)
Device A0 B
0 D D1 E F
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. max.
C650, C850 4.2
(.165)
4.4
(.173)
8.45
(.333)
8.65
(.341)
1.5
(.059)
1.6
(.063)
1.5
(.059) -1.65
(.065)
1.85
(.073)
7.4
(.291)
7.6
(.299)
Device K0P P0 P
2 t W
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
C650, C850 1.1
(.043)
1.3
(.051)
7.9
(.311)
8.1
(.319)
3.9
(.159)
4.1
(.161)
1.9
(.075)
2.1
(.083)
0.25
(.010)
0.35
(.014)
15.7
(.618)
16.3
(.642)
QUANTITY: 3000 PIECES PER REEL
PIN 1
MANUFACTURER’S
TRADEMARK 5 DIGIT PRODUCT CODE:
• 1ST ALPHA CHARACTER INDICATES PRODUCT FAMILY.
C = C650/C850 SERIES
• 2ND & 3RD DIGITS INDICATE IMPULSE VOLTAGE.
• 4TH & 5TH DIGITS INDICATE TRIGGER CURRENT.
MANUFACTURING
DATE CODE:
• 1ST DIGIT INDICATES THE YEAR.
• 2ND & 3RD DIGITS INDICATE THE WEEK NUMBER.
• 4TH & 5TH DIGITS INDICATE LOT CODE.
XXXXX
YWWLL
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
BOURNS'
C650 and C850 Series TBU® High-Speed Protectors
Reference Application
The C-series devices are general protectors that can be used in a variety of applications. The basic operation of the device will be
demonstrated using the single line application shown in the fi gure below. The test circuit was subjected to a 1000 V, 10/700 μs surge
waveform. The devices used were the TBU-C850-100-WH and a 2031-42T-SM-RPLF GDT (OVP) with a 10 ohm resistor for the load
impedance.
The graph below shows the waveforms for the voltage across the overvoltage protector (GDT) and the current through the TBU®
device. As the input line voltage increases, the current through the TBU® device increases rapidly until the trip current is reached. Due
to fi nite reaction time for fast transients, the peak level may exceed the low frequency data sheet maximum for a very short period,
typically ~100 ns. After this initial overshoot, the TBU® device will transition to the protected state, setting the current to the nominal
current limiting level (~150 mA for this example). The TBU® device will then reduce the current down it to its very low quiescent level
of 1 mA, typically. As the input line voltage increases to about 500 V, the GDT is triggered, reducing the input line voltage to a very low
level which prevents the TBU® device from being subjected to a voltage level which exceeds its maximum rating (850 V in this
example). The TBU® High-Speed Orotector and the GDT will remain in these states until the surge ends, which is about 700 μs later
in this example. Only the fi rst 4 μs of the surge are shown in the graph. For surges or AC voltages below the GDT breakover voltage,
the GDT will not activate, and the TBU® device will stay in the protecting mode, blocking high voltages from the protected equipment.
General Application Circuit
“TBU” is a registered trademark of Bourns, Inc. in the United States and other countries.
REV. 09/15
ZLOAD
Line
TBU® Device
OVP
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
900
800
700
600
500
400
300
200
100
0
100
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (µs)
Voltage Across GDT (V)
TBU® Device Current (mA)
GDT Voltage
TBU® Device Current
TBU-C850-100-WH Response to a 1000 V, 10/700 μs Surge
Specifications are subject to change without notice.
Users should verify actual device performance in their specific applications.
The products described herein and this document are subject to specific legal disclaimers as set forth on the last page of this document, and at www.bourns.com/docs/legal/disclaimer.pdf.
BOURNS'
Legal Disclaimer Notice
This legal disclaimer applies to purchasers and users of Bourns® products manufactured by or on behalf of Bourns, Inc. and
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Unless otherwise expressly indicated in writing, Bourns® products and data sheets relating thereto are subject to change
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and complete before placing orders for Bourns® products.
The characteristics and parameters of a Bourns® product set forth in its data sheet are based on laboratory conditions, and
statements regarding the suitability of products for certain types of applications are based on Bourns’ knowledge of typical
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the user’s sole risk.
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