NXP USA Inc. 的 NX3L2G66 规格书

规格书反馈/错误

1. General description

The NX3L2G66 is a dual low-ohmic single-pole single-throw analog switch. Each switch

has two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When

pin nE is LOW, the analog switch is turned off.

Schmitt trigger action at the enable input (nE) makes the circuit tolerant to slower input

rise and fall times. The NX3L2G66 allows signals with amplitude up to VCC to be

transmitted from nY to nZ; or from nZ to nY. Its low ON resistance (0.5 ) and flatness

(0.13 ) ensures minimal attenuation and distortion of transmitted signals.

2. Features and benefits

Wide supply voltage range from 1.4 V to 4.3 V

Very low ON resistance (peak):

1.6  (typical) at VCC =1.4V

1.0  (typical) at VCC =1.65V

0.55  (typical) at VCC =2.3V

0.50  (typical) at VCC =2.7V

0.50  (typical) at VCC =4.3V

High noise immunity

ESD protection:

HBM JESD22-A114F Class 3A exceeds 7500 V

MM JESD22-A115-A exceeds 200 V

CDM AEC-Q100-011 revision B exceeds 1000 V

IEC61000-4-2 contact discharge exceeds 4000 V for switch ports

CMOS low-power consumption

Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

Direct interface with TTL levels at 3.0 V

Control input accepts voltages above supply voltage

High current handling capability (350 mA continuous current under 3.3 V supply)

Specified from 40 C to +85 C and from 40 C to +125 C

3. Applications

Cell phone

PDA

Portable media player

NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

Rev. 8 — 7 February 2013 Product data sheet

‘? \

Product data sheet Rev. 8 — 7 February 2013 2 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

4. Ordering information

5. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

6. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

NX3L2G66GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 1  1.95  0.5 mm SOT833-1

NX3L2G66GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;

8 terminals; body 3  2  0.5 mm SOT996-2

NX3L2G66GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6 1.6 0.5 mm SOT902-2

Table 2. Marking codes[1]

Type number Marking code

NX3L2G66GT D66

NX3L2G66GD D66

NX3L2G66GM D66

Fig 1. Logic symbol Fig 2. Logic diagram (one switch)

001aag497

1Y 1Z

001aah372

Emma DEED DCI |:||:| |:||:| |:||:|

Product data sheet Rev. 8 — 7 February 2013 3 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

7. Pinning information

7.1 Pinning

Fig 3. Pin configuration SOT833-1 (XSON8) Fig 4. Pin configuration SOT996-2 (XSON8)

NX3L2G66

GND

001aah373

Transparent top view

001aaj533

NX3L2G66

Transparent top view

GND

VCC

Fig 5. Pin configuration SOT902-2 (XQFN8)

001aah374

1Z2Z

VCC

GND

Transparent top view

terminal 1

index area

NX3L2G66

la,

Product data sheet Rev. 8 — 7 February 2013 4 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

7.2 Pin description

8. Functional description

[1] H = HIGH voltage level; L = LOW voltage level.

9. Limiting values

[1] The minimum input voltage rating may be exceeded if the input current rating is observed.

[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not

exceed 4.6 V.

[3] For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.

Table 3. Pin description

Symbol Pin Description

SOT833-1 and SOT996-2 SOT902-2

1Y, 2Y 1, 5 7, 3 independent input or output

1Z, 2Z 2, 6 6, 2 independent input or output

GND 4 4 ground (0 V)

1E, 2E 7, 3 1, 5 enable input (active HIGH)

VCC 8 8 supply voltage

Table 4. Function table[1]

Input nE Switch

LOFF-state

H ON-state

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +4.6 V

VIinput voltage enable input nE [1] 0.5 +4.6 V

VSW switch voltage [2] 0.5 VCC + 0.5 V

IIK input clamping current VI<0.5 V 50 - mA

ISK switch clamping current VI<0.5 V or VI>V

CC + 0.5 V - 50 mA

ISW switch current VSW >0.5 V or VSW < VCC + 0.5 V;

source or sink current -350 mA

VSW >0.5 V or VSW < VCC + 0.5 V;

pulsed at 1 ms duration, < 10 % duty cycle;

peak current

-500 mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb =40 Cto+125C[3] - 250 mW

Figure 6 Figuve 7

Product data sheet Rev. 8 — 7 February 2013 5 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

10. Recommended operating conditions

[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch

must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no

limit for the voltage drop across the switch.

[2] Applies to control signal levels.

11. Static characteristics

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 1.4 - 4.3 V

VIinput voltage enable input nE 0 - 4.3 V

VSW switch voltage [1] 0- V

CC V

Tamb ambient temperature 40 - +125 C

t/V input transition rise and fall rate VCC = 1.4 V to 4.3 V [2] - - 200 ns/V

Table 7. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground 0 V).

Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit

Min Typ Max Min Max

(85 C) Max

(125 C)

VIH HIGH-level

input voltage VCC = 1.4 V to 1.95 V 0.65VCC - - 0.65VCC --V

VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - - V

VCC = 3.6 V to 4.3 V 0.7VCC - - 0.7VCC --V

VIL LOW-level

input voltage VCC = 1.4 V to 1.95 V - - 0.35VCC - 0.35VCC 0.35VCC V

VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 0.8 V

VCC = 3.6 V to 4.3 V - - 0.3VCC -0.3V

CC 0.3VCC V

IIinput leakage

current enable input nE;

VI=GNDto4.3V;

VCC = 1.4 V to 4.3 V

--- -0.5 1A

IS(OFF) OFF-state

leakage

current

nY port; see Figure 6

VCC = 1.4 V to 3.6 V - - 5-50 500 nA

VCC = 3.6 V to 4.3 V - - 10 - 50 500 nA

IS(ON) ON-state

leakage

current

nZ port; see Figure 7

VCC = 1.4 V to 3.6 V - - 5-50 500 nA

VCC = 3.6 V to 4.3 V - - 10 - 50 500 nA

ICC supply current VI=V

CC or GND;

VSW =GNDorV

VCC = 3.6 V - - 100 - 690 6000 nA

VCC = 4.3 V - - 150 - 800 7000 nA

Figure 9 Figure 15 Figure 8 \va \

Product data sheet Rev. 8 — 7 February 2013 6 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

11.1 Test circuits

11.2 ON resistance

CIinput

capacitance -1.0----pF

CS(OFF) OFF-state

capacitance -35----pF

CS(ON) ON-state

capacitance -110----pF

Table 7. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground 0 V).

Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit

Min Typ Max Min Max

(85 C) Max

(125 C)

VI=0.3VorV

CC 0.3 V; VO=V

CC  0.3 V or 0.3 V. VI=0.3VorV

CC 0.3 V; VO= open circuit.

Fig 6. Test circuit for measuring OFF-state leakage

current Fig 7. Test circuit for measuring ON-state leakage

current

001aaj221

VIL

VCC

GND

nYnZ

001aaj222

VIH

VCC

GND

nYnZ

Table 8. ON resistance

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15.

Symbol Parameter Conditions Tamb = 40 C to +85

CTamb = 40 C to

+125 CUnit

Min Typ[1] Max Min Max

RON(peak) ON resistance (peak) VI=GNDtoV

CC;

ISW = 100 mA;

see Figure 8

VCC = 1.4 V - 1.6 3.7 - 4.1 

VCC = 1.65 V - 1.0 1.6 - 1.7 

VCC = 2.3 V - 0.55 0.8 - 0.9 

VCC =2.7V - 0.5 0.75 - 0.9 

VCC =4.3V - 0.5 0.75 - 0.9 

Figure 9 Figure 15 mp, \

Product data sheet Rev. 8 — 7 February 2013 7 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

[1] Typical values are measured at Tamb = 25 C.

[2] Measured at identical VCC, temperature and input voltage.

[3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and

temperature.

RON ON resistance mismatch

between channels VI=GNDtoV

CC;

ISW = 100 mA

[2]

VCC = 1.4 V - 0.04 0.3 - 0.3 

VCC = 1.65 V - 0.04 0.2 - 0.3 

VCC = 2.3 V - 0.02 0.08 - 0.1 

VCC = 2.7 V - 0.02 0.075 - 0.1 

VCC = 4.3 V - 0.02 0.075 - 0.1 

RON(flat) ON resistance (flatness) VI=GNDtoV

CC;

ISW = 100 mA

[3]

VCC = 1.4 V - 1.0 3.3 - 3.6 

VCC = 1.65 V - 0.5 1.2 - 1.3 

VCC = 2.3 V - 0.15 0.3 - 0.35 

VCC = 2.7 V - 0.13 0.3 - 0.35 

VCC = 4.3 V - 0.2 0.4 - 0.45 

Table 8. ON resistance …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15.

Symbol Parameter Conditions Tamb = 40 C to +85

CTamb = 40 C to

+125 CUnit

Min Typ[1] Max Min Max

Product data sheet Rev. 8 — 7 February 2013 8 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

11.3 ON resistance test circuit and graphs

RON =V

SW / ISW.(1)V

CC =1.5V.

(2) VCC =1.8V.

(3) VCC =2.5V.

(4) VCC =2.7V.

(5) VCC =3.3V.

(6) VCC =4.3V.

Measured at Tamb =25C.

Fig 8. Test circuit for measuring ON resistance Fig 9. Typical ON resistance as a function of input

voltage

001aaj223

VIH

VCC

GND

nYnZ

VSW

ISW

VI (V)

054312

001aag564

0.8

0.4

1.2

1.6

RON

(Ω)

(1)

(2)

(5) (6)

(4)

(3)

Product data sheet Rev. 8 — 7 February 2013 9 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

(1) Tamb = 125 C.

(2) Tamb =85C.

(3) Tamb =25C.

(4) Tamb =40 C.

(1) Tamb = 125 C.

(2) Tamb =85C.

(3) Tamb =25C.

(4) Tamb =40 C.

Fig 10. ON resistance as a function of input voltage;

VCC =1.5V Fig 11. ON resistance as a function of input voltage;

VCC =1.8V

001aag565

VI (V)

0321

0.8

0.4

1.2

1.6

RON

(Ω)

(1)

(2)

(3)

(4)

001aag566

VI (V)

0321

0.4

0.6

0.2

0.8

1.0

RON

(Ω)

(1)

(2)

(3)

(4)

(1) Tamb = 125 C.

(2) Tamb =85C.

(3) Tamb =25C.

(4) Tamb =40 C.

(1) Tamb = 125 C.

(2) Tamb =85C.

(3) Tamb =25C.

(4) Tamb =40 C.

Fig 12. ON resistance as a function of input voltage;

VCC =2.5V Fig 13. ON resistance as a function of input voltage;

VCC =2.7V

001aag567

VI (V)

0321

0.4

0.6

0.2

0.8

1.0

RON

(Ω)

(1)

(2)

(3)

(4)

001aag568

VI (V)

0321

0.4

0.6

0.2

0.8

1.0

RON

(Ω)

(1)

(2)

(3)

(4)

Figure 17 Figure 16 Figure 16

Product data sheet Rev. 8 — 7 February 2013 10 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

12. Dynamic characteristics

[1] Typical values are measured at Tamb =25C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.

(1) Tamb = 125 C.

(2) Tamb =85C.

(3) Tamb =25C.

(4) Tamb =40 C.

(1) Tamb = 125 C.

(2) Tamb =85C.

(3) Tamb =25C.

(4) Tamb =40 C.

Fig 14. ON resistance as a function of input voltage;

VCC =3.3V Fig 15. ON resistance as a function of input voltage;

VCC =4.3V

VI (V)

04312

001aag569

0.4

0.6

0.2

0.8

1.0

RON

(Ω)

(1)

(2)

(3)

(4)

VI (V)

054231

001aaj896

0.4

0.6

0.2

0.8

1.0

RON

(Ω)

(1)

(2)

(3)

(4)

Table 9. Dynamic characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.

Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to +125 CUnit

Min Typ[1] Max Min Max

(85 C) Max

(125 C)

ten enable time nE to nZ or nY;

see Figure 16

VCC = 1.4 V to 1.6 V - 27 41 - 43 48 ns

VCC = 1.65 V to 1.95 V - 22 33 - 34 36 ns

VCC = 2.3 V to 2.7 V - 17 26 - 27 30 ns

VCC = 2.7 V to 3.6 V - 14 23 - 24 26 ns

VCC = 3.6 V to 4.3 V - 14 23 - 24 26 ns

tdis disable time nE to nZ or nY;

see Figure 16

VCC = 1.4 V to 1.6 V - 9 18 - 19 21 ns

VCC = 1.65 V to 1.95 V - 7 13 - 14 15 ns

VCC = 2.3 V to 2.7 V - 4 8 - 9 10 ns

VCC = 2.7 V to 3.6 V - 4 8 - 8 9 ns

VCC = 3.6 V to 4.3 V - 4 8 - 8 9 ns

Product data sheet Rev. 8 — 7 February 2013 11 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

12.1 Waveform and test circuits

Measurement points are given in Table 10.

Logic level: VOH is the typical output voltage level that occurs with the output load.

Fig 16. Enable and disable times

001aah376

nY output

OFF to HIGH

HIGH to OFF

nE input

VOH

GND

ten tdis

VXVX

switch

enabled

switch

disabled switch

disabled

Table 10. Measurement points

Supply voltage Input Output

VCC VMVX

1.4 V to 4.3 V 0.5VCC 0.9VOH

Test data is given in Table 11.

Definitions for test circuit:

RL = load resistance.

CL = load capacitance including jig and probe capacitance.

VEXT = external voltage for measuring switching times.

Fig 17. Test circuit for measuring switching times

001aaj224

nY/nZ nZ/nY

RLCL

VCC

VEXT = 1.5 V

VIVVO

Table 11. Test data

Supply voltage Input Load

VCC VItr, tfCLRL

1.4 V to 4.3 V VCC 2.5ns 35pF 50

ngure 18 Figure 19 ﬁgure 20 ﬁgure 21 ﬁgure 22 Figure 23 \ 7""? 0J—

Product data sheet Rev. 8 — 7 February 2013 12 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

12.2 Additional dynamic characteristics

[1] fi is biased at 0.5VCC.

12.3 Test circuits

Table 12. Additional dynamic characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise

specified); tr = tf



2.5 ns.

Symbol Parameter Conditions Tamb = 25 CUnit

Min Typ Max

THD total harmonic

distortion fi=20Hzto20 kHz; R

L=32; see Figure 18 [1]

VCC =1.4V; V

I= 1 V (p-p) - 0.15 - %

VCC =1.65V; V

I= 1.2 V (p-p) - 0.10 - %

VCC =2.3V; V

I= 1.5 V (p-p) - 0.02 - %

VCC =2.7V; V

I= 2 V (p-p) - 0.02 - %

VCC =4.3V; V

I= 2 V (p-p) - 0.02 - %

f(3dB) 3 dB frequency

response RL=50; see Figure 19 [1]

VCC = 1.4 V to 4.3 V - 60 - MHz

iso isolation (OFF-state) fi= 100 kHz; RL=50; see Figure 20 [1]

VCC = 1.4 V to 4.3 V - 90 - dB

Vct crosstalk voltage between digital inputs and switch;

fi= 1 MHz; CL= 50 pF; RL=50; see Figure 21

VCC = 1.4 V to 3.6 V - 0.2 - V

VCC = 3.6 V to 4.3 V - 0.2 - V

Xtalk crosstalk between switches;

fi= 100 kHz; RL=50;seeFigure 22

[1]

VCC = 1.4 V to 4.3 V - 90 - dB

Qinj charge injection fi= 1 MHz; CL= 0.1 nF; RL=1 M; Vgen =0V;

Rgen =0; see Figure 23

VCC = 1.5 V - 3 - pC

VCC = 1.8 V - 3 - pC

VCC =2.5V - 3 - pC

VCC =3.3V - 3 - pC

VCC =4.3V - 6 - pC

Fig 18. Test circuit for measuring total harmonic distortion

001aaj225

0.5V

nZ/nYnY/nZ

Product data sheet Rev. 8 — 7 February 2013 13 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3dB.

Fig 19. Test circuit for measuring the frequency response when channel is in ON-state

001aaj226

0.5V

nZ/nYnY/nZ

Adjust fi voltage to obtain 0 dBm level at input.

Fig 20. Test circuit for measuring isolation (OFF-state)

001aaj227

0.5V

nZ/nYnY/nZ

0.5V

Product data sheet Rev. 8 — 7 February 2013 14 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

a. Test circuit

b. Input and output pulse definitions

Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch

001aaj228

nY/nZ nZ/nY

RLCL

0.5V

Vct

001aaj231

off

logic

input (nE)

on off

20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).

Fig 22. Test circuit for measuring crosstalk between switches

001aah382

1Z or 1Y1Y or 1Z

fiCHANNEL

50 Ω

0.5VCC

VIH

VO1

2Z or 2Y

2Y or 2Z

CHANNEL

OFF

50 Ω

0.5VCC

VIL

VO2

Product data sheet Rev. 8 — 7 February 2013 15 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

a. Test circuit

b. Input and output pulse definitions

Definition: Qinj =VO CL.

VO = output voltage variation.

Rgen = generator resistance.

Vgen = generator voltage.

Fig 23. Test circuit for measuring charge injection

001aaj229

nY/nZ nZ/nY

GND

RLCL

VCC

Vgen

Rgen

VIVVO

001aaj232

offonoff

logic

input (nE)

3L3 EL© 3 3 3 3 3 ‘ 'T""'T'T'T""'T"' 77743777773734.7777377 3 3

Product data sheet Rev. 8 — 7 February 2013 16 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

13. Package outline

Fig 24. Package outline SOT833-1 (XSON8)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT833-1 - - -

MO-252

- - -

SOT833-1

07-11-14

07-12-07

DIMENSIONS (mm are the original dimensions)

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

e1e1

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 2.0

1.9 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

8×

(2)

4×

(2)

i 1 We 7,,i,TrirW L ‘\‘ .iElg. 4 JDF‘W 1% rmmmm 1 :Dmmm E© «9742—31»

Product data sheet Rev. 8 — 7 February 2013 17 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

Fig 25. Package outline SOT996-2 (XSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT996-2

sot996-2_po

07-12-21

12-11-20

Unit(1)

mm max

nom

min 0.5 0.05

0.00

2.1

1.9

3.1

2.9

0.5

0.3

0.15

0.05

0.6

0.4

0.5 1.5 0.05

Dimensions (mm are the original dimensions)

XSON8: plastic extremely thin small outline package; no leads;

8 terminals; body 3 x 2 x 0.5 mm SOT996-2

A1b

0.35

0.15

DEee

1LL

1L2v

0.1

0.05

0.1

0 1 2 mm

scale

terminal 1

index area

B A

detail X

AA1

eAC B

Product data sheet Rev. 8 — 7 February 2013 18 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

Fig 26. Package outline SOT902-2 (XQFN8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT902-2 - - -

MO-255

- - -

sot902-2_po

10-11-02

11-03-31

Unit(1)

mm max

nom

min

0.5 0.05

0.00

1.65

1.60

1.55

1.65

1.60

1.55 0.55 0.5 0.15

0.10

0.05 0.1 0.05

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

XQFN8: plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2

A1b

0.25

0.20

0.15

DEee

0.35

0.30

0.25

L1vw

0.05

0 1 2 mm

scale

terminal 1

index area

terminal 1

index area

AC B

metal area

not for soldering

detail X

Product data sheet Rev. 8 — 7 February 2013 19 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

14. Abbreviations

15. Revision history

Table 13. Abbreviations

Acronym Description

CDM Charged Device Model

CMOS Complementary Metal Oxide Semiconductor

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 14. Revision history

Document ID Release date Data sheet status Change notice Supersedes

NX3L2G66 v.8 20130207 Product data sheet - NX3L2G66 v.7

Modifications: •For type number NX3L2G66GD XSON8U has changed to XSON8.

NX3L2G66 v.7 20120613 Product data sheet - NX3L2G66 v.6

NX3L2G66 v.6 20111107 Product data sheet - NX3L2G66 v.5

NX3L2G66 v.5 20110107 Product data sheet - NX3L2G66 v.4

NX3L2G66 v.4 20090828 Product data sheet - NX3L2G66 v.3

NX3L2G66 v.3 20090409 Product data sheet - NX3L2G66 v.2

NX3L2G66 v.2 20090326 Product data sheet - NX3L2G66 v.1

NX3L2G66 v.1 20080131 Product data sheet - -

Product data sheet Rev. 8 — 7 February 2013 20 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

: hitE:I/www.nxg.com salesaddresses®nx9£0m

Product data sheet Rev. 8 — 7 February 2013 21 of 22

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors NX3L2G66

Dual low-ohmic single-pole single-throw analog switch

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 February 2013

Document identifier: NX3L2G66

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Functional description . . . . . . . . . . . . . . . . . . . 4

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

10 Recommended operating conditions. . . . . . . . 5

11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

11.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6

11.3 ON resistance test circuit and graphs. . . . . . . . 8

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 10

12.1 Waveform and test circuits . . . . . . . . . . . . . . . 11

12.2 Additional dynamic characteristics . . . . . . . . . 12

12.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17 Contact information. . . . . . . . . . . . . . . . . . . . . 21

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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