onsemi 的 DM74LS75 规格书

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© 2000 Fairchild Semiconductor Corporation DS006374 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS75 Quad Latch
DM74LS75
Quad Latch
General Description
These latches are ideally suited for use as temporary stor-
age for binary information between processing units and
input/output or indicator units. Information present at a data
(D) input is transferred to the Q output when the enable is
HIGH, and the Q output will follow the data input as long as
the enable remains HIGH. When the enable goes LOW, the
information (that was present at the data input at the time
the transition occurred) is retained at the Q output until the
enable is permitted to go HIGH.
These latches feature complementary Q and Q outputs
from a 4-bit latch, and are available in 16-pin packages.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
(Each Latch)
Function Table (Each Latch)
H = HIGH Level
L = LOW Level
X = Don't Care
Q0 = The Level of Q Before the HIGH-to-LOW Transition of ENABLE
Connection Diagram
Order Number Package Number Package Description
DM74LS75M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS75N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
D Enable Q Q
LHLH
HHHL
XLQ
0Q0
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DM74LS75
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at VCC = 5V, TA = 25°C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4: ICC is measured with all outputs open and all inputs grounded.
Note 5: TA = 25°C and VCC = 5V.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
tWEnable Pulse Width (Note 5) 20 ns
tSU Setup Time (Note 5) 20 ns
tHHold Time (Note 5) 0 ns
TAFree Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ Max Units
(Note 2)
VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max 2.7 3.5 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max 0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
IIInput Current @ Max VCC = Max, VI = 7V D 0.1 mA
Input Voltage Enable 0.4
IIH HIGH Level Input VCC = Max, VI = 2.7V D 20 µA
Current Enable 80
IIL LOW Level Input VCC = Max, VI = 0.4V D −0.4 mA
Current Enable −1.6
IOS Short Circuit Output Current VCC = Max (Note 2) −20 −100 mA
ICC Supply Current VCC = Max (Note 3) 6.3 12 mA
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DM74LS75
Switching Characteristics
at VCC = 5V and TA = 25°C
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
MinMaxMinMax
tPLH Propagation Delay Time D to Q 27 30 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time D to Q 17 25 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time D to Q 20 25 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time D to Q 15 20 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time Enable to Q 27 30 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time Enable to Q 25 30 ns
HIGH-to-LOW Level Output
tPLH Propagation Delay Time Enable to Q 30 30 ns
LOW-to-HIGH Level Output
tPHL Propagation Delay Time Enable to Q 15 20 ns
HIGH-to-LOW Level Output
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DM74LS75
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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DM74LS75 Quad Latch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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