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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

TMUX1119 5-V, Low-Leakage-Current, 2:1 Precision Switch

1 Features

1• Wide supply range: 1.08 V to 5.5 V

• Low leakage current: 3 pA

• Low on-resistance: 1.8 Ω

• Low charge injection: –6 pC

• -40°C to +125°C Operating temperature

•1.8 V Logic Compatible

•Fail-Safe Logic

•Rail to Rail Operation

•Bidirectional Signal Path

• Break-before-make switching

• ESD protection HBM: 2000 V

2 Applications

•Ultrasound scanners

•Patient monitoring & diagnostics

•Blood glucose monitors

•Optical module

•Optical transport

•Remote radio units

•Data acquisition systems

•Semiconductor test equipment

•Factory automation and industrial controls

•Flow transmitters

•Programmable logic controllers (PLC)

•Analog input modules

•Battery Test

3 Description

The TMUX1119 is a complementary metal-oxide

semiconductor (CMOS) single-pole double-throw

(2:1) switch. Wide operating supply of 1.08 V to 5.5 V

allows for use in a broad array of applications from

medical equipment to industrial systems. The device

supports bidirectional analog and digital signals on

the source (Sx) and drain (D) pins ranging from GND

to VDD. All logic inputs have 1.8 V logic compatible

thresholds, ensuring both TTL and CMOS logic

compatibility when operating in the valid supply

voltage range. Fail-Safe Logic circuitry allows

voltages on the control pins to be applied before the

supply pin, protecting the device from potential

damage.

The TMUX1119 is part of the precision switches and

multiplexers family of devices. These devices have

very low on and off leakage currents and low charge

injection, allowing them to be used in high precision

measurement applications. A low supply current of 3

nA and small package options enable use in portable

applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TMUX1119 SC70 (6) 2.00 mm × 1.25 mm

SOT-23 (6) 2.90 mm x 1.60 mm

(1) For all available packages, see the package option addendum

at the end of the data sheet.

SPACER

Application Example Block Diagram

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SCDS401B –DECEMBER 2018–REVISED MAY 2020

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics (VDD = 5 V ±10 %)............ 5

6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)......... 7

6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)......... 9

6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)....... 11

6.9 Typical Characteristics............................................ 13

7 Parameter Measurement Information ................ 16

7.1 On-Resistance ........................................................ 16

7.2 Off-Leakage Current ............................................... 16

7.3 On-Leakage Current ............................................... 17

7.4 Transition Time ....................................................... 17

7.5 Break-Before-Make................................................. 18

7.6 Charge Injection...................................................... 18

7.7 Off Isolation............................................................. 19

7.8 Crosstalk ................................................................. 19

7.9 Bandwidth ............................................................... 20

8 Detailed Description............................................ 21

8.1 Overview ................................................................. 21

8.2 Functional Block Diagram....................................... 21

8.3 Feature Description................................................. 21

8.4 Device Functional Modes........................................ 23

8.5 Truth Tables............................................................ 23

9 Application and Implementation ........................ 24

9.1 Application Information............................................ 24

9.2 Typical Application ................................................. 24

9.3 Design Requirements.............................................. 24

9.4 Detailed Design Procedure..................................... 25

9.5 Application Curve.................................................... 25

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 26

11.1 Layout Guidelines ................................................. 26

11.2 Layout Example .................................................... 26

12 Device and Documentation Support ................. 27

12.1 Documentation Support ........................................ 27

12.2 Related Links ........................................................ 27

12.3 Receiving Notification of Documentation Updates 27

12.4 Community Resources.......................................... 27

12.5 Trademarks........................................................... 27

12.6 Electrostatic Discharge Caution............................ 27

12.7 Glossary................................................................ 27

13 Mechanical, Packaging, and Orderable

Information ........................................................... 27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (November 2019) to Revision B Page

• Changed status of DBV package From: Product Preview To: Production Data .................................................................... 1

• Added Thermal information for DBV package........................................................................................................................ 4

Changes from Original (December 2018) to Revision A Page

• Changed the data sheet title From: Precision Analog Multiplexer To: Precision Switch........................................................ 1

• Changed the Applications list ................................................................................................................................................. 1

• Changed Thermal Information for DCK package ................................................................................................................... 4

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1SEL 6 S2

2VDD 5 D

3GND 4 S1

Not to scale

1SEL 6 S2

2VDD 5 D

3GND 4 S1

Not to scale

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5 Pin Configuration and Functions

DCK Package

6-Pin SC70

Top View

DBV Package

6-Pin SOT-23

Top View

(1) I = input, O = output, I/O = input and output, P = power

Pin Functions

PIN TYPE(1) DESCRIPTION

NAME NO.

SEL 1 I Select pin: controls state of the switch according to Table 1. (Logic Low = S1 to D, Logic High = S2 to D)

VDD 2 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect

a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.

GND 3 P Ground (0 V) reference

S1 4 I/O Source pin 1. Can be an input or output.

D 5 I/O Drain pin. Can be an input or output.

S2 6 I/O Source pin 2. Can be an input or output.

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(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)(2)

MIN MAX UNIT

VDD Supply voltage –0.5 6 V

VSEL or VEN Logic control input pin voltage (SEL) –0.5 6 V

ISEL or IEN Logic control input pin current (SEL) –30 30 mA

VSor VDSource or drain voltage (Sx, D) –0.5 VDD+0.5 V

ISor ID (CONT) Source or drain continuous current (Sx, D) –30 30 mA

Tstg Storage temperature –65 150 °C

TJJunction temperature 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins(2) ±750

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

MIN NOM MAX UNIT

VDD Supply voltage 1.08 5.5 V

VSor VDSignal path input and output voltage (source or drain pin) (Sx, D) 0 VDD V

VSEL Logic control input pin voltage (SEL) 0 5.5 V

TAAmbient temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

TMUX1119

UNITDCK (SC70) DBV (SOT-23)

6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 243.1 212.3 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 206.0 156.7 °C/W

RθJB Junction-to-board thermal resistance 128.3 96.5 °C/W

ΨJT Junction-to-top characterization parameter 107.8 80.7 °C/W

ΨJB Junction-to-board characterization parameter 128.0 96.2 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

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(1) When VSis 4.5 V, VDis 1.5 V, and vice versa.

6.5 Electrical Characteristics (VDD = 5 V ±10 %)

At TA= 25°C, VDD = 5 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

ANALOG SWITCH

RON On-resistance VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 1.8 4 Ω

–40°C to +85°C 4.5 Ω

–40°C to +125°C 4.9 Ω

ΔRON On-resistance matching between

channels

VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 0.13 Ω

–40°C to +85°C 0.4 Ω

–40°C to +125°C 0.5 Ω

RON

FLAT On-resistance flatness VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 0.85 Ω

–40°C to +85°C 1.4 Ω

–40°C to +125°C 1.6 Ω

IS(OFF) Source off leakage current(1)

VDD = 5 V

Switch Off

VD= 4.5 V / 1.5 V

VS= 1.5 V / 4.5 V

Refer to Off-Leakage Current

25°C –0.08 ±0.005 0.08 nA

–40°C to +85°C –0.3 0.3 nA

–40°C to +125°C –0.9 0.9 nA

ID(ON)

IS(ON) Channel on leakage current

VDD = 5 V

Switch On

VD= VS= 2.5 V

Refer to On-Leakage Current

25°C –0.025 ±0.003 0.025 nA

–40°C to +85°C –0.3 0.3 nA

–40°C to +125°C –0.95 0.95 nA

ID(ON)

IS(ON) Channel on leakage current

VDD = 5 V

Switch On

VD= VS= 4.5 V / 1.5 V

Refer to On-Leakage Current

25°C –0.1 ±0.01 0.1 nA

–40°C to +85°C –0.35 0.35 nA

–40°C to +125°C –2 2 nA

LOGIC INPUTS (SEL)

VIH Input logic high –40°C to +125°C 1.49 5.5 V

VIL Input logic low –40°C to +125°C 0 0.87 V

IIH

IIL Input leakage current 25°C ±0.005 µA

IIH

IIL Input leakage current –40°C to +125°C ±0.05 µA

CIN Logic input capacitance 25°C 1 pF

CIN Logic input capacitance –40°C to +125°C 2 pF

POWER SUPPLY

IDD VDD supply current Logic inputs = 0 V or 5.5 V 25°C 0.003 µA

–40°C to +125°C 1 µA

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Electrical Characteristics (VDD = 5 V ±10 %) (continued)

At TA= 25°C, VDD = 5 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

DYNAMIC CHARACTERISTICS

tTRAN Switching time between channels VS= 3 V

RL= 200 Ω, CL= 15 pF

Refer to Transition Time

25°C 12 ns

–40°C to +85°C 18 ns

–40°C to +125°C 19 ns

tOPEN

(BBM) Break before make time VS= 3 V

RL= 200 Ω, CL= 15 pF

Refer to Break-Before-Make

25°C 8 ns

–40°C to +85°C 1 ns

–40°C to +125°C 1 ns

QCCharge Injection VD= 1 V

RS= 0 Ω, CL= 1 nF

Refer to Charge Injection 25°C –6 pC

OISO Off Isolation

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Off Isolation 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Off Isolation 25°C –45 dB

XTALK Crosstalk

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Crosstalk 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Crosstalk 25°C –45 dB

BW Bandwidth RL= 50 Ω, CL= 5 pF

Refer to Bandwidth 25°C 250 MHz

CSOFF Source off capacitance f = 1 MHz 25°C 6 pF

CSON

CDON On capacitance f = 1 MHz 25°C 20 pF

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(1) When VSis 3 V, VDis 1 V, and vice versa.

6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)

At TA= 25°C, VDD = 3.3 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

ANALOG SWITCH

RON On-resistance VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 3.7 8.8 Ω

–40°C to +85°C 9.5 Ω

–40°C to +125°C 9.8 Ω

ΔRON On-resistance matching between

channels

VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 0.13 Ω

–40°C to +85°C 0.4 Ω

–40°C to +125°C 0.5 Ω

RON

FLAT On-resistance flatness VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 1.9 Ω

–40°C to +85°C 2 Ω

–40°C to +125°C 2.2 Ω

IS(OFF) Source off leakage current(1)

VDD = 3.3 V

Switch Off

VD= 3 V / 1 V

VS= 1 V / 3 V

Refer to Off-Leakage Current

25°C –0.05 ±0.001 0.05 nA

–40°C to +85°C –0.1 0.1 nA

–40°C to +125°C –0.5 0.5 nA

ID(ON)

IS(ON) Channel on leakage current

VDD = 3.3 V

Switch On

VD= VS= 3 V / 1 V

Refer to On-Leakage Current

25°C –0.1 ±0.005 0.1 nA

–40°C to +85°C –0.35 0.35 nA

–40°C to +125°C –2 2 nA

LOGIC INPUTS (SEL)

VIH Input logic high –40°C to +125°C 1.35 5.5 V

VIL Input logic low –40°C to +125°C 0 0.8 V

IIH

IIL Input leakage current 25°C ±0.005 µA

IIH

IIL Input leakage current -40°C to 125°C ±0.05 µA

CIN Logic input capacitance 25°C 1 pF

CIN Logic input capacitance –40°C to +125°C 2 pF

POWER SUPPLY

IDD VDD supply current Logic inputs = 0 V or 5.5 V 25°C 0.003 µA

–40°C to +125°C 0.8 µA

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Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)

At TA= 25°C, VDD = 3.3 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

DYNAMIC CHARACTERISTICS

tTRAN Switching time between channels VS= 2 V

RL= 200 Ω, CL= 15 pF

Refer to Transition Time

25°C 14 ns

–40°C to +85°C 20 ns

–40°C to +125°C 21 ns

tOPEN

(BBM) Break before make time VS= 2 V

RL= 200 Ω, CL= 15 pF

Refer to Break-Before-Make

25°C 9 ns

–40°C to +85°C 1 ns

–40°C to +125°C 1 ns

QCCharge Injection VD= 1 V

RS= 0 Ω, CL= 1 nF

Refer to Charge Injection 25°C –6 pC

OISO Off Isolation

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Off Isolation 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Off Isolation 25°C –45 dB

XTALK Crosstalk

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Crosstalk 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Crosstalk 25°C –45 dB

BW Bandwidth RL= 50 Ω, CL= 5 pF

Refer to Bandwidth 25°C 250 MHz

CSOFF Source off capacitance f = 1 MHz 25°C 6 pF

CSON

CDON On capacitance f = 1 MHz 25°C 20 pF

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(1) When VSis 1.62 V, VDis 1 V, and vice versa.

6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)

At TA= 25°C, VDD = 1.8 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

ANALOG SWITCH

RON On-resistance VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 40 Ω

–40°C to +85°C 80 Ω

–40°C to +125°C 80 Ω

ΔRON On-resistance matching between

channels

VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 0.4 Ω

–40°C to +85°C 1.5 Ω

–40°C to +125°C 1.5 Ω

IS(OFF) Source off leakage current(1)

VDD = 1.98 V

Switch Off

VD= 1.62 V / 1 V

VS= 1 V / 1.62 V

Refer to Off-Leakage Current

25°C –0.05 ±0.003 0.05 nA

–40°C to +85°C –0.1 0.1 nA

–40°C to +125°C –0.5 0.5 nA

ID(ON)

IS(ON) Channel on leakage current

VDD = 1.98 V

Switch On

VD= VS= 1.62 V / 1 V

Refer to On-Leakage Current

25°C –0.1 ±0.005 0.1 nA

–40°C to +85°C –0.5 0.5 nA

–40°C to +125°C –2 2 nA

LOGIC INPUTS (SEL)

VIH Input logic high –40°C to +125°C 1.07 5.5 V

VIL Input logic low –40°C to +125°C 0 0.68 V

IIH

IIL Input leakage current 25°C ±0.005 µA

IIH

IIL Input leakage current –40°C to +125°C ±0.05 µA

CIN Logic input capacitance 25°C 1 pF

CIN Logic input capacitance –40°C to +125°C 2 pF

POWER SUPPLY

IDD VDD supply current Logic inputs = 0 V or 5.5 V 25°C 0.001 µA

–40°C to +125°C 0.85 µA

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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)

At TA= 25°C, VDD = 1.8 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

DYNAMIC CHARACTERISTICS

tTRAN Transition time between channels VS= 1 V

RL= 200 Ω, CL= 15 pF

Refer to Transition Time

25°C 28 ns

–40°C to +85°C 44 ns

–40°C to +125°C 44 ns

tOPEN

(BBM) Break before make time VS= 1 V

RL= 200 Ω, CL= 15 pF

Refer to Break-Before-Make

25°C 16 ns

–40°C to +85°C 1 ns

–40°C to +125°C 1 ns

QCCharge Injection VD= 1 V

RS= 0 Ω, CL= 1 nF

Refer to Charge Injection 25°C –3 pC

OISO Off Isolation

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Off Isolation 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Off Isolation 25°C –45 dB

XTALK Crosstalk

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Crosstalk 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Crosstalk 25°C –45 dB

BW Bandwidth RL= 50 Ω, CL= 5 pF 25°C 250 MHz

CSOFF Source off capacitance f = 1 MHz 25°C 6 pF

CSON

CDON On capacitance f = 1 MHz 25°C 20 pF

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(1) When VSis 1 V, VDis 0.8 V, and vice versa.

6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)

At TA= 25°C, VDD = 1.2 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

ANALOG SWITCH

RON On-resistance VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 70 Ω

–40°C to +85°C 105 Ω

–40°C to +125°C 105 Ω

ΔRON On-resistance matching between

channels

VS= 0 V to VDD

ISD = 10 mA

Refer to On-Resistance

25°C 0.4 Ω

–40°C to +85°C 1.5 Ω

–40°C to +125°C 1.5 Ω

IS(OFF) Source off leakage current(1)

VDD = 1.32 V

Switch Off

VD= 1 V / 0.8 V

VS= 0.8 V / 1 V

Refer to Off-Leakage Current

25°C –0.05 ±0.003 0.05 nA

–40°C to +85°C –0.1 0.1 nA

–40°C to +125°C –0.5 0.5 nA

ID(ON)

IS(ON) Channel on leakage current

VDD = 1.32 V

Switch On

VD= VS= 1 V / 0.8 V

Refer to On-Leakage Current

25°C –0.1 ±0.005 0.1 nA

–40°C to +85°C –0.5 0.5 nA

–40°C to +125°C –2 2 nA

LOGIC INPUTS (SEL)

VIH Input logic high –40°C to +125°C 0.96 5.5 V

VIL Input logic low –40°C to +125°C 0 0.36 V

IIH

IIL Input leakage current 25°C ±0.005 µA

IIH

IIL Input leakage current –40°C to +125°C ±0.05 µA

CIN Logic input capacitance 25°C 1 pF

CIN Logic input capacitance –40°C to +125°C 2 pF

POWER SUPPLY

IDD VDD supply current Logic inputs = 0 V or 5.5 V 25°C 0.003 µA

–40°C to +125°C 0.7 µA

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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)

At TA= 25°C, VDD = 1.2 V (unless otherwise noted).

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT

DYNAMIC CHARACTERISTICS

tTRAN Transition time between channels VS= 1 V

RL= 200 Ω, CL= 15 pF

Refer to Transition Time

25°C 55 ns

–40°C to +85°C 190 ns

–40°C to +125°C 190 ns

tOPEN

(BBM) Break before make time VS= 1 V

RL= 200 Ω, CL= 15 pF

Refer to Break-Before-Make

25°C 28 ns

–40°C to +85°C 1 ns

–40°C to +125°C 1 ns

QCCharge Injection VD= 1 V

RS= 0 Ω, CL= 1 nF

Refer to Charge Injection 25°C –2 pC

OISO Off Isolation

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Off Isolation 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Off Isolation 25°C –45 dB

XTALK Crosstalk

RL= 50 Ω, CL= 5 pF

f = 1 MHz

Refer to Crosstalk 25°C –65 dB

RL= 50 Ω, CL= 5 pF

f = 10 MHz

Refer to Crosstalk 25°C –45 dB

BW Bandwidth RL= 50 Ω, CL= 5 pF 25°C 250 MHz

CSOFF Source off capacitance f = 1 MHz 25°C 6 pF

CSON

CDON On capacitance f = 1 MHz 25°C 20 pF

l TEXAS INSTRUMENTS (WV F 100

VS or VD - Source or Drain Voltage (V)

On-Leakage (pA)

0 0.5 1 1.5 2 2.5 3 3.5 4

-40

-30

-20

-10

VDD = 1.32 V VDD = 1.98 V VDD = 3.63 V

D005

VS or VD - Source or Drain Voltage (V)

On-Leakage (pA)

0 1 2 3 4 5

-100

-80

-60

-40

-20

100

D006

VS or VD - Source or Drain Voltage (V)

On Resistance (:)

0 0.5 1 1.5 2 2.5 3 3.5

TA = 25qC

TA = 125qC

TA = 85qC

TA = -40qC

D003

VS or VD - Source or Drain Voltage (V)

On Resistance (:)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VDD = 1.62 V

VDD = 1.98 V

VDD = 1.08 V

VDD = 1.32 V

D004

VS or VD - Source or Drain Voltage (V)

On Resistance (:)

0 1 2 3 4 5 5.5

VDD = 5.5 V

VDD = 4.5 V

VDD = 3.63 V

VDD = 3 V

D001

VS or VD - Source or Drain Voltage (V)

On Resistance (:)

0 1 2 3 4 5

0.5

1.5

2.5

3.5

4.5

TA = 25qC

TA = 125qC

TA = 85qC

TA = -40qC

D002

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

6.9 Typical Characteristics

at TA= 25°C, VDD = 5 V (unless otherwise noted)

TA= 25°C

Figure 1. On-Resistance vs Source or Drain Voltage

VDD = 5 V

Figure 2. On-Resistance vs Temperature

VDD = 3.3 V

Figure 3. On-Resistance vs Temperature

TA= 25°C

Figure 4. On-Resistance vs Source or Drain Voltage

TA= 25°C

Figure 5. On-Leakage vs Source or Drain Voltage

VDD = 5 V

Figure 6. On-Leakage vs Source or Drain Voltage

l TEXAS INSTRUMENTS // o 4 500 R2 4 we \

VD - Drain Voltage (V)

Charge Injection (pC)

0 1 2 3 4 5

-20

-15

-10

-5

VDD = 5 V

VDD = 3.3 V

D011

VD - Drain Voltage (V)

Charge Injection (pC)

0 0.5 1 1.5 2

-5

-3

-1

VDD = 1.8 V

VDD = 1.2 V

D012

Temperature (qC)

Supply Current (PA)

-40 -20 0 20 40 60 80 100 120 140

-0.1

0.1

0.2

0.3

0.4

VDD = 5 V

VDD = 3.3 V

VDD = 1.8 V

VDD = 1.2 V

D009

Logic Voltage (V)

Supply Current (PA)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

100

200

300

400

500

VDD = 5 VVDD = 3.3 V

D010

Temperature (qC)

Leakage Current (nA)

-40 -20 0 20 40 60 80 100 120

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

IS(OFF)

I(ON)

D007

Temperature (qC)

Leakage Current (nA)

-40 -20 0 20 40 60 80 100 120

-3

-2

-1

I(ON)

IS(OFF)

D008

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

Typical Characteristics (continued)

VDD = 3.3 V

Figure 7. Leakage Current vs Temperature

VDD = 5 V

Figure 8. Leakage Current vs Temperature

VSEL = 5.5 V

Figure 9. Supply Current vs Temperature

TA= 25°C

Figure 10. Supply Current vs Logic Voltage

TA= -40°C to 125°C

Figure 11. Charge Injection vs Drain Voltage

TA= -40°C to 125°C

Figure 12. Charge Injection vs Drain Voltage

l TEXAS INSTRUMENTS

Frequency (Hz)

Gain (dB)

-8

-7

-6

-5

-4

-3

-2

-1

1M 10M 100M

D015

VDD - Supply Voltage (V)

Time (ns)

0.5 1.5 2.5 3.5 4.5 5.5

Rising

Falling

D013

Frequency (Hz)

Magnitude (dB)

-90

-80

-70

-60

-50

-40

-30

-20

-10

100k 1M 10M 100M

D014

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

Typical Characteristics (continued)

TA= 25°C

Figure 13. Output TTRANSITION vs Supply Voltage

TA= 25°C

Figure 14. Xtalk and Off-Isolation vs Frequency

TA= 25°C

Figure 15. On Response vs Frequency

Qﬁwi

VDD

GND

Is (OFF)

ISD

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.

The measurement setup used to measure RON is shown in Figure 16. Voltage (V) and current (ISD) are measured

using this setup, and RON is computed with RON =V/ISD:

Figure 16. On-Resistance Measurement Setup

7.2 Off-Leakage Current

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol IS(OFF).

The setup used to measure off-leakage current is shown in Figure 17.

Figure 17. Off-Leakage Measurement Setup

‘5‘ TEXAS INSTRUMENTS

VIH VIL

tTRANSITION

10%

90%

OUTPUT

0 V

ADDRESS

DRIVE

(VSEL)

VDD

tTRANSITION

VSOUTPUT

RLCL

SEL

GND

VSEL

0 V

tr < 5ns tf < 5ns

VDD

0.1…F

VDD

GND

ID (ON)

VDD

GND

IS (ON)

N.C.

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol IS(ON).

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol ID(ON).

Either the source pin or drain pin is left floating during the measurement. Figure 18 shows the circuit used for

measuring the on-leakage current, denoted by IS(ON) or ID(ON).

Figure 18. On-Leakage Measurement Setup

7.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal

has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of

the device. System level timing can then account for the time constant added from the load resistance and load

capacitance. Figure 19 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.

Figure 19. Transition-Time Measurement Setup

l TEXAS INSTRUMENTS

VDD

VSS

OUTPUT

SEL

GND

0.1…F 0.1…F

VOUT

Output

VSQC = CL × VOUT

VOUT

VSEL

N.C.

0 V

VDD

VSEL

VDD

0 V

tBBM 1

90%

Output

0 V

tOPEN (BBM) = min ( tBBM 1, tBBM 2)

tBBM 2

ADDRESS

DRIVE

(VSEL)

tr < 5ns tf < 5ns VSOUTPUT

RLCL

SEL

GND

VSEL

VDD

0.1…F

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

7.5 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is

switching. The output first breaks from the on-state switch before making the connection with the next on-state

switch. The time delay between the break and the make is known as break-before-make delay. Figure 20 shows

the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).

Figure 20. Break-Before-Make Delay Measurement Setup

7.6 Charge Injection

The TMUX1119 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS

transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.

The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted

by the symbol QC.Figure 21 shows the setup used to measure charge injection from Drain (D) to Source (Sx).

Figure 21. Charge-Injection Measurement Setup

‘5‘ TEXAS INSTRUMENTS a?

OUT

Channel-to-Channel Crosstalk 20 Log V

§ ·

˜ ¨ ¸

NETWORK

ANALYZER

GND

VSIG

50Q

VOUT

50Q

VDD

0.1µF

OUT

Off Isolation 20 Log V

§ ·

˜ ¨ ¸

GND

NETWORK

ANALYZER

VOUT

50Q

VSIG

50Q

VDD

0.1µF

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

7.7 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the

source pin (Sx) of an off-channel. Figure 22 shows the setup used to measure, and the equation used to

calculate off isolation.

Figure 22. Off Isolation Measurement Setup

(1)

7.8 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. Figure 23 shows the setup used to measure, and the equation used to

calculate crosstalk.

Figure 23. Crosstalk Measurement Setup

(2)

l TEXAS INSTRUMENTS

GND

NETWORK

ANALYZER

VOUT

50Q

VSIG

50Q

VDD

0.1µF

50Q

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

7.9 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 24

shows the setup used to measure bandwidth.

Figure 24. Bandwidth Measurement Setup

l TEXAS INSTRUMENTS

TMUX1119

SEL

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

8 Detailed Description

8.1 Overview

The TMUX1119 is an 2:1, 1-ch. (SPDT), analog switch where the input is controlled with a single select (SEL)

control pin.

8.2 Functional Block Diagram

Figure 25. TMUX1119 Functional Block Diagram

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX1119 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). The device

has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail to Rail Operation

The valid signal path input/output voltage for TMUX1119 ranges from GND to VDD.

8.3.3 1.8 V Logic Compatible Inputs

The TMUX1119 has 1.8-V logic compatible control for the logic control input (SEL). The logic input threshold

scales with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level

inputs allow the TMUX1119 to interface with processors that have lower logic I/O rails and eliminates the need

for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic

implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches

8.3.4 Fail-Safe Logic

The TMUX1119 supports Fail-Safe Logic on the control input pin (SEL) allowing for operation up to 5.5 V,

regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the

supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by

removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic

feature allows the select pin of the TMUX1119 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature

enables operation of the TMUX1119 with VDD = 1.2 V while allowing the select pin to interface with a logic level

of another device up to 5.5 V.

l TEXAS INSTRUMENTS ‘41/

CGDP

CGDN

CGSN

CGSP

OFF ON

Temperature (qC)

Leakage Current (nA)

-40 -20 0 20 40 60 80 100 120

-3

-2

-1

I(ON)

IS(OFF)

D008

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

Feature Description (continued)

8.3.5 Ultra-low Leakage Current

The TMUX1119 provides extremely low on-leakage and off-leakage currents. The TMUX1119 is capable of

switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset

error because of the ultra-low leakage currents. Figure 26 shows typical leakage currents of the TMUX1119

versus temperature.

Figure 26. Leakage Current vs Temperature

8.3.6 Ultra-low Charge Injection

The TMUX1119 has a transmission gate topology, as shown in Figure 27. Any mismatch in the stray capacitance

associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

Figure 27. Transmission Gate Topology

l TEXAS INSTRUMENTS

VD - Drain Voltage (V)

Charge Injection (pC)

0 1 2 3 4 5

-20

-15

-10

-5

VDD = 5 V

VDD = 3.3 V

D011

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

Feature Description (continued)

The TMUX1119 has special charge-injection cancellation circuitry that reduces the drain-to-source charge

injection to -6 pC at VD= 1 V as shown in Figure 28.

Figure 28. Charge Injection vs Drain Voltage

8.4 Device Functional Modes

The select (SEL) pin of the TMUX1119 controls which switch is connected to the drain of the device. When a

given input is not selected, that source pin is in high impedance mode (HI-Z). The control pins can be as high as

5.5 V.

8.5 Truth Tables

Table 1. TMUX1119 Truth Table

CONTROL LOGIC (SEL) Selected Source (Sx) Connected To Drain (D) Pin

0 S1

1 S2

ADC

TX/RX

MUX

MOSI

32 kHz

MSP430FR599

8 MHz

OPA836

OPA835

TMUX1119

x2 SEL

SEL

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMUX11xx family offers ulta-low input and output leakage currents and low charge injection. These devices

operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX1119

has a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These

features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for low-

voltage applications.

9.2 Typical Application

Figure 29 shows an ultrasonic gas meter front end. The ultrasonic front end design utilizes time of flight (TOF)

measurement to determine the amount of gas flowing in a pipe. The circuit utilizes the MSP430FR5994, two ultra

low power operational amplifiers, OPA835 and OPA836, along with two TMUX1119, 2:1 precision switches.

Figure 29. Ultrasonic Gas Meter System

9.3 Design Requirements

For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

PARAMETERS VALUES

Supply (VDD) 5 V

I/O signal range 0 V to VDD (Rail to Rail)

Control logic thresholds 1.8 V compatible

Single-shot standard deviation (STD) <2 ns

Zero-flow drift (ZFD) <1 ns

TEXAS INSTRUMENTS

VS or VD - Source or Drain Voltage (V)

On Resistance (:)

0 1 2 3 4 5 5.5

VDD = 5.5 V

VDD = 4.5 V

VDD = 3.63 V

VDD = 3 V

D001

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

9.4 Detailed Design Procedure

The TMUX1119 can be operated without any external components except for the supply decoupling capacitors.

All inputs passing through the switch must fall within the recommend operating conditions of the TMUX1119,

including signal range and continuous current. For this design with a supply of 5 V the signal range can be 0 V to

5 V, and the max continuous current can be 30 mA.

The TMUX1119 device is a bidirectional, single-pole double-throw (SPDT) switch that offers low on-resistance,

low leakage, and low power. These features make this device suitable for portable and power sensitive

applications such as ultrasonic gas metering systems. The two TMUX1119 devices are used to switch the

transmission and reception signals from the MCU to the two transceivers in an efficient manner without distortion.

Exceptional on-resistance flatness, leakage performance, and charge injection allows the TMUX1119 to be

utilized in place of the TS5A9411 in Ultrasonic Gas Meter Front-End With MSP430™ Reference Design. For a

more detailed analysis of the entire system refer to the reference design.

9.5 Application Curve

The TMUX1119 is capable of switching signals with minimal distortion because of the ultra-low leakage currents

and excellent On-resistance flatness. Figure 30 shows how the on-resistance fo the TMUX1119 varies with

different supply voltages.

TA= 25°C

Figure 30. On-Leakage vs Source or Drain Voltage

10 Power Supply Recommendations

The TMUX1119 operates across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum

ratings because stresses beyond the listed ratings can cause permanent damage to the devices.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to

other components. Good power-supply decoupling is important to achieve optimum performance. For improved

supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.

Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance

connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series

resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive

systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to

the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall

inductance and is beneficial for connections to ground planes.

l TEXAS INSTRUMENTS WORST BETTER / $2 HEIU S

Via to

GND plane

Wide (low inductance)

trace for power

TMUX1119

WORST BETTER BEST

1W min.

TMUX1119

SCDS401B –DECEMBER 2018–REVISED MAY 2020

www.ti.com

Product Folder Links: TMUX1119

11 Layout

11.1 Layout Guidelines

11.1.1 Layout Information

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. Figure 31 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

Figure 31. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points, through-

hole pins are not recommended at high frequencies.

Figure 32 illustrates an example of a PCB layout with the TMUX1119. Some key considerations are:

• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the

capacitor voltage rating is sufficient for the VDD supply.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

Figure 32. TMUX1119 Layout Example

l TEXAS INSTRUMENTS Am

TMUX1119

www.ti.com

SCDS401B –DECEMBER 2018–REVISED MAY 2020

Product Folder Links: TMUX1119

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

Texas Instruments, Ultrasonic Gas Meter Front-End With MSP430™ Reference Design.

Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.

Texas Instruments, Improve Stability Issues with Low CON Multiplexers.

Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.

Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.

Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.

Texas Instruments, QFN/SON PCB Attachment.

Texas Instruments, Quad Flatpack No-Lead Logic Packages.

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TMUX1119DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26HT

TMUX1119DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 1DF

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TMUX1119DBVR SOT-23 DBV 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

TMUX1119DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jun-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TMUX1119DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0

TMUX1119DCKR SC70 DCK 6 3000 180.0 180.0 18.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jun-2020

Pack Materials-Page 2

MECHANICAL DATA DCK (R-PDSO-GS) PLASTIC SMALL-OUTLINE PACKAGE E 18’) 6 4 7 H Fl H ‘ﬁ «40 1233 \ ’i’ To enugemane Seanng Mane Pm 1/ ' ‘ ' ‘ ‘ maexArea Wm H m} j; / ‘ u / Um "4L 1—]; f Scamg Mane \\ \ / 31 409555574/8 U‘ /200/ , m m hmeters AH \mec' mmens‘mrs Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom ﬂcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m FuHs an JFDFC M07763 vunuhcn AB NO'FS Umm> INSrRUMEm-s www.1i.com

LAND PATTERN DATA 7PJSOiC6> PLASTC SMALL OU’LME NOTES' maop> Exc'm‘e Boc'd Luyum stem Openings Based or a stencﬂ hickncss uf 127mm (005mm) * 1* :E /23\\der Musk Cpen‘wg “ 2m Geometry M \meur dimensmns are m m'ﬂhrvete's Th's drawqu is sweat (a chc'vge mm: 'vuhce Custume's shoud p‘uce a new 01 We cvcmt buurd (abr'cahun c'awmg rm :0 uHer the ce'ﬂe' smder musk deﬁned and, ”Jbﬁcuhon \PC77351 is reco'n'nended (Dr uHernme designs Laser cumrg opc'mvcs mm "apczmda wuHs and mo rouncmq corners wm am bcncr aosxc recuscv mstomcrs show can thew Guard assemwy sue for gene design recommencnmons Exomme sxercu deswgw basec on a 50% vo‘umemc bad My paste M‘cr m M4523 var other new rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com

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PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.45 MAX

0.15

0.00 TYP

6X 0.50

0.25

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0006A

SMALL OUTLINE TRANSISTOR

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

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EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

6X (1.1)

6X (0.6)

(2.6)

2X (0.95)

(R0.05) TYP

4214840/C 06/2021

SOT-23 - 1.45 mm max heightDBV0006A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(2.6)

2X(0.95)

6X (1.1)

6X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0006A

SMALL OUTLINE TRANSISTOR

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments 的 TMUX1119 规格书

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