STMicroelectronics 的 STGAP2D 规格书
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STGAP2D
Datasheet - production data
Features
Applications
Description
SO-16
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Contents STGAP2D
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Testing and characterization information . . . . . . . . . . . . . . . . . . . . . . . 16
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block diagram STGAP2D
1 Block diagram
Figure 1. Block diagram
I
S
O
L
A
T
I
O
N
VH_A
GOUT_A
GNDISO_A
SD
VDD
GND
INA
INB
VDD2
BRAKE
Control
Logic
Floating
Section
Control
Logic
Floating ground A
UVLO
VH Level
Shifter
Floating
Section
Control
Logic
Floating ground B
UVLO
VH Level
Shifter
VH_B
GOUT_B
GNDISO_B
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STGAP2D Pin description and connection diagram
2 Pin description and connection diagram
Figure 2. Pin connection (top view)
Table 1. Pin description
Pin # Pin Name Type Function
9''
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,1$
*1'
*287B$
9+B$
9+B%
1&
1&
*287B%
9''
*1',62B$
1&
*1',62B%
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Electrical data STGAP2D
3 Electrical data
3.1 Absolute maximum ratings
3.2 Thermal data
3.3 Recommended operating conditions
Table 2. Absolute maximum ratings
Symbol Parameter Test
condition Min. Max. Unit
Table 3. Thermal data
Symbol Parameter Package Value Unit
Table 4. Recommended operating conditions
Symbol Parameter Test conditions Min. Max. Unit
STGAP2D Electrical data
Table 4. Recommended operating conditions
Symbol Parameter Test conditions Min. Max. Unit
(TJ
Electrical characteristics STGAP2D
4 Electrical characteristics
4.1 Electrical characteristics
Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 15 V, VDD = 5 V, unless otherwise specified)
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
Dynamic characteristics
Figure 9
Supply voltage
Logic inputs
STGAP2D Electrical characteristics
Ilogic_h
Vlogic = 5 V
Ilogic_I
Vlogic = 0 V
Driver buffer section
VH_x-0.14
Over-temperature protection
Standby
Section 5.6
Section 5.6
Section 5.6
Section 5.6
1. MT = max (|tDon(A) - tDon(B)|, |tDoff(A) - tDoff(B)|, |tDoff(A) - tDon(B)|, |tDoff(B) - tDon(A)|)
Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 15 V, VDD = 5 V, unless otherwise specified)
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit
Functional description STGAP2D
5 Functional description
5.1 Gate driving power supply and UVLO
Figure 3. Power supply configuration for unipolar and bipolar gate driving
5.2 Power-up, power-down and 'safe state'
I
S
O
L
A
T
I
O
N
VH_x
GNDISO_x
VDD
GND
INx
GOUT_x
+
VH
VDD
+
VH
+
VL
Unipolar gate driving Bipolar gate driving
I
S
O
L
A
T
I
O
N
VH_x
GNDISO_x
VDD
GND
INx
GOUT_x
1uF 100nF
VDD
1uF 100nF
1uF100nF 100nF 1uF
1uF
STGAP2D Functional description
5.3 Control inputs
Table 6
5.4 Watchdog
5.5 Thermal shutdown protection
5.6 Standby function
Table 6. Inputs truth table (applicable when device is not in UVLO or “safe state”)
Input pins(1) Output pins
SD BRAKE INA INB GOUT_A GOUT_B
HIGH
HIGH
HIGH
Interlocking
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Functional description STGAP2D
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Figure 4. Standby state sequences
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STGAP2D Typical application diagram
6 Typical application diagram
Figure 5. Typical application diagram - Half-bridge configuration
Figure 6. Typical application diagram - Half-bridge configuration with negative driving
VH_HS
HIN
LIN
VH_A
GOUT_A
GNDISO_A
SD
GND
INA
INB
VDD2
BRAKE
VH_B
GOUT_B
GNDISO_B
SD
BRAKE
C
filt
R
filt
GND_PWR
Load_Phase
HV_BUS
1uF100nF
VDD
VDD
1uF 100nF
VDD
MCU
1uF100nF
I
S
O
L
A
T
I
O
N
Control
Logic
Floating
Section
Control
Logic
Floating ground A
UVLO
VH Level
Shifter
Floating
Section
Control
Logic
Floating ground B
UVLO
VH Level
Shifter
VH_LS
GND_LS
GND_HS
C
filt
R
filt
C
filt
R
filt
VDD
VH_HS
HIN
LIN
VH_A
GOUT_A
GNDISO_A
SD
GND
INA
INB
VDD2
BRAKE
VH_B
GOUT_B
GNDISO_B
SD
BRAKE
C
filt
R
filt
GND_PWR
Load_Phase
HV_BUS
1uF100nF
VDD
VDD
1uF 100nF
VDD
MCU
100nF
I
S
O
L
A
T
I
O
N
Control
Logic
Floating
Section
Control
Logic
Floating ground A
UVLO
VH Level
Shifter
Floating
Section
Control
Logic
Floating ground B
UVLO
VH Level
Shifter
VH_LS
GND_LS
GND_HS
C
filt
R
filt
C
filt
R
filt
VDD
1uF
1uF
1uF
Layout STGAP2D
7 Layout
7.1 Layout guidelines and considerations
STGAP2D Layout
7.2 Layout example
Figure 7
Figure 7. Suggested PCB layout for Half-Bridge configuration
R
IN
R
IN
R
PU
R
IN
R
IN
C
IN
C
IN
C
IN
C
IN
R
PU
C
VDD
C
VDD
R
DT
C
VH_A
C
VH_A
C
VH_B
C
VH_B
R
OFF
R
OFF
R
ON
R
ON
D
OFF
D
OFF
D
BOOT
R
BOOT
C
G
C
G
G
HS
S
HS
D
HS
D
LS
G
LS
S
LS
C
VH_B
C
VH_A
GON
HHéOFF
GND‘SO 1
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Testing and characterization information STGAP2D
8 Testing and characterization information
Figure 8. Timings definition
Figure 9. CMTI test circuit
50%
50%
10%
90%
trtf
t
Don
90%
10%
GOUT_A
INB
INA
t
Doff
50%
50%
GOUT_B 10%
90%
trtf
t
Don
90%
10%
t
Doff
I
S
O
L
A
T
I
O
N
VH
GOFF
GNDISO
VDD
GND
IN+
IN-
GON
+
VH
Output V
out
monitoring node
S1
+
-
G1
+
VDD
STGAP2D Package information
9 Package information
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Table 7. SO-16 narrow package dimensions
Dim.
mm
Min. Typ. Max. NOTES
Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not
exceed 0.15 mm in total (both sides)
Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm
per side
Dimensions referred to the bottom side of the package.
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Package information STGAP2D
Figure 10. SO-16 narrow package outline
D
b
e
1
16 9
8
STGAP2D Suggested land pattern
10 Suggested land pattern
Figure 11. SO-16 narrow suggested land pattern
4.0
6.7
1.27
0.6 (x14)
3.21
Ordering information STGAP2D
11 Ordering information
12 Revision history
Table 8. Device summary
Order code Output
configuration
Package
marking Package Packaging
Table 9. Document revision history
Date Revision Changes
STGAP2D
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