Texas Instruments 的 THS7315 规格书

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FEATURES DESCRIPTION
APPLICATIONS
DAC/
Encoder
(DaVinci )
TM
CVBS
Y’
C’
75 W
Y’
OUT
75 W
C’
OUT
75 W
3.3V
+1.8V
75 W
75 W
SDTV
CVBS
S-Video Y’
S-VideoC’
480i/576i
Y’P’ P’
G’B’R’
B R
75 W
S-Video
500 W
500 W
500 W
5
8
7
6
1
2
3
4
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
CVBS
OUT
Gain=
5.2V/V
THS7315
SLOS532 – JUNE 2007
3-Channel SDTV Video Amplifier with 5th-Order Filters and 5.2-V/V Gain
•Three SDTV Video Amplifiers for CVBS,
Fabricated using the revolutionary complementaryS-Video, Y'P'
B
P'
R
480i/576i, Y'U'V', or G'B'R'
silicon-sermanium (SiGe) BiCom3 process, the(R'G'B')
THS7315 is a low-power, single-supply, 3-V to 5-V3-channel integrated video buffer. It incorporates a•Integrated Low-Pass Filters:
5th-order Butterworth filter that is useful as a– 5th-Order, 8.5-MHz (–3dB) Butterworth
digital-to-analog converter (DAC) reconstruction filter– –1dB Passband Bandwidth at 7 MHz
or an analog-to-digital converter (ADC) anti-aliasingfilter. The 8.5-MHz filter is a perfect choice for SDTV– 47 dB Attenuation at 27 MHz
video, including Composite Video Baseband Signals•Versatile Input Biasing:
(CVBS), S-Video, Y’U’V’, G’B’R’ (R’G’B’), and– DC-Coupled with 230-mV Output Shift
Y’P’
B
P’
R
480i/576i.– AC-Coupled with Sync-Tip Clamp
The THS7315 inputs can be either ac- or dc-coupled.– Allows AC-Coupled With DC-Biasing
The 230-mV output level shift allows for a full syncdynamic range at the output with 0 V input. The•Built-in 5.2 V/V Gain (14.3 dB)
ac-coupled modes include a transparent sync-tip•+3-V to +5-V Single Supply Operation
clamp option for CVBS, Y', and G'B'R' signals with•Rail-to-Rail Output:
bottom-level sync. AC-coupled biasing for C'/P'
B
/P'
Rchannels can easily be achieved by adding an– Output Swings Within 100 mV of the Rails,
external resistor to V
S+
.Allowing AC- or DC-Output Coupling
– Supports Driving Two Lines per Channel
The THS7315 is the perfect choice for all outputbuffer applications. Its rail-to-rail output stage with•Low Total Quiescent Current: 15.6 mA at 3.3 V
5.2-V/V gain allows for both ac and dc line driving,•Low Differential Gain/Phase of 0.2%/0.3 °
making it a perfect choice for DaVinci™ processors.•Lead-free, Green SOIC-8 Package
The ability for each channel to drive two video lines,or 75- Ωloading, allows for maximum flexibility as avideo line driver. The 15.6-mA quiescent current at3.3 V also makes it an excellent choice for•Set Top Box Output Video Buffering
USB-powered, portable, or other power-sensitive•PVR/DVDR Output Buffering
video applications•USB/Portable Low-Power Video Buffering
The THS7315 is available in a small SOIC-8package that is lead-free and compliant with greenrequirements.
3.3-V Single-Supply DC-Input/DC-Output Coupled Video Line Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DaVinci is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
THS7315
SLOS532 – JUNE 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
PACKAGING/ORDERING INFORMATION
(1)
PACKAGED DEVICES PACKAGE TYPE TRANSPORT MEDIA, QUANTITY
THS7315D Rails, 75SOIC-8THS7315DR Tape and reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
Over operating free-air temperature range (unless otherwise noted)
THS7315 UNIT
Supply voltage, V
S+
to GND 5.5 V
V
I
Input voltage –0.4 to V
S+
V
I
O
Output current ±90 mA
Continuous power dissipation See Dissipation Ratings Table
T
J
Maximum junction temperature, any condition
(2)
+150 °C
T
J
Maximum junction temperature, continuous operation, long term reliability
(3)
+125 °C
T
stg
Storage temperature range –65 to +150 °C
HBM 2000
ESD ratings CDM 1500 V
MM 200
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.(2) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.(3) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above thistemperature may result in reduced reliability and/or lifetime of the device.
POWER RATING
(1)
(T
J
= +125 °C)θ
JC
θ
JAPACKAGE ( °C/W) ( °C/W) T
A
= +25 °C T
A
= +85 °C
SOIC-8 (D) 16.8 130
(2)
769 mW 308 mW
(1) Power rating is determined with a junction temperature of +125 °C. This temperature is the point where performance starts to degradeand long-term reliability starts to be reduced. Thermal management of the final printed circuit board (PCB) should strive to keep thejunction temperature at or below +125 °C for best performance and reliability.(2) This data was taken with the JEDEC High-K test PCB. For the JEDEC low-K test PCB, the θ
JA
is 196 °C/W.
MIN NOM MAX UNIT
V
S+
Supply voltage 3 5 V
T
A
Ambient temperature –40 +85 °C
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ELECTRICAL CHARACTERISTICS: V
S+
= 3.3 V
THS7315
SLOS532 – JUNE 2007
R
L
= 150 Ωto GND, unless otherwise noted. See Figure 1 and Figure 2 .
TYP OVER TEMPERATURE
0°C to –40 °C to MIN/MAX/PARAMETER TEST CONDITIONS +25 °C +25 °C +70 °C +85 °C UNIT TYP
AC PERFORMANCE
Small-signal bandwidth (–3 dB) V
O
– 0.2 V
PP
(1)
8.5 6.8/10.4 6.7/10.5 6.6/10.6 MHz Min/Max
Large-signal bandwidth (–3 dB) V
O
–2V
PP
(1)
8.5 6.8/10.4 6.7/10.5 6.6/10.6 MHz Min/Max
Passband bandwidth (–1dB) 7.0 MHz Typ
f = 6 MHz
(2)
0.25 –0.3/2.4 –0.35/2.5 –0.4/2.6 dB Min/MaxAttenuation (with respect to 100 kHz)
f = 27 MHz
(2)
47 36 35 34 dB Min
Group delay f = 100 kHz 61 ns Typ
Group delay variation (with respect to
f = 5.1 MHz 12 ns Typ100 kHz)
Channel-to-channel delay 0.3 ns Typ
Differential gain NTSC/PAL 0.2/0.2 % Typ
Differential phase NTSC/PAL 0.25/0.35 degrees Typ
Total harmonic distortion f = 1 MHz, V
O
= 2 V
PP
, ac-coupled I/O –62 dB Typ
Signal-to-noise ratio NTC-7 weighting, 100 kHz to 4.2 MHz 73 dB Typ
Channel-to-channel crosstalk f = 1 MHz, output-referred –65 dB Typ
AC gain, all channels 14.3 14/14.6 14/14.6 14/14.6 dB Min/Max
Output impedance f = 1 MHz 0.8 ΩTyp
DC PERFORMANCE
Biased output voltage V
IN
= 0 V 230 80/390 68/415 48/420 mV Min/Max
Input voltage range DC input, limited by output –0.1/0.56 V Typ
Sync tip clamp charge current V
IN
= –0.1 V 200 μA Typ
Input resistance 800 k ΩTyp
Input capacitance 2 pF Typ
OUTPUT CHARACTERISTICS
R
L
= 150 Ωto 1.65 V 3.15 V Typ
R
L
= 150 Ωto GND 3.10 2.85 2.75 2.75 V MinHigh output voltage swing
R
L
= 75 Ωto 1.65 V 3.10 V Typ
R
L
= 75 Ωto GND 3.0 V Typ
R
L
= 150 Ωto 1.65 V (V
IN
= –0.15 V) 0.15 V Typ
R
L
= 150 Ωto GND (V
IN
= –0.15 V) 0.05 0.13 0.14 0.14 V MaxLow output voltage swing
R
L
= 75 Ωto 1.65 V (V
IN
= –0.15 V) 0.26 V Typ
R
L
= 75 Ωto GND (V
IN
= –0.15 V) 0.1 V Typ
Sourcing 80 mA TypOutput current R
L
= 10 Ωto 1.65 VSinking 70 mA Typ
POWER SUPPLY
Maximum operating voltage 3.3 5.5 5.5 5.5 V Max
Minimum operating voltage 3.3 2.85 2.85 2.85 V Min
Maximum quiescent current V
IN
= 0 V 15.6 20 22 24 mA Max
Minimum quiescent current V
IN
= 0 V 15.6 12 11.6 11 mA Min
Power supply rejection (+PSRR) 43 dB Typ
(1) The Min/Max values listed for this specification are specified by design and characterization only.(2) 3.3-V supply filter specifications are specified by 100% testing at 5-V supply along with design and characterization only.
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ELECTRICAL CHARACTERISTICS: V
S+
= 5 V
THS7315
SLOS532 – JUNE 2007
R
L
= 150 Ωto GND, unless otherwise noted. See Figure 1 and Figure 2 .
TYP OVER TEMPERATURE
0°C to –40 °C to MIN/MAX/PARAMETER TEST CONDITIONS +25 °C +25 °C +70 °C +85 °C UNIT TYP
AC PERFORMANCE
Small-signal bandwidth (–3 dB) V
O
– 0.2 V
PP
(1)
8.5 6.8/10.4 6.7/10.5 6.6/10.6 MHz Min/Max
Large-signal bandwidth (–3 dB) V
O
–2V
PP
(1)
8.5 6.8/10.4 6.7/10.5 6.6/10.6 MHz Min/Max
Passband bandwidth (–1dB) 7.0 MHz Typ
f = 6 MHz 0.25 –0.3/2.4 –0.35/2.5 –0.4/2.6 dB Min/MaxAttenuation (with respect to 100 kHz)
f = 27 MHz 47 36 35 34 dB Min
Group delay f = 100 kHz 61 ns Typ
Group delay variation (with respect to
f = 5.1 MHz 11 ns Typ100 kHz)
Channel-to-channel delay 0.3 ns Typ
Differential gain NTSC/PAL 0.2/0.2 % Typ
Differential phase NTSC/PAL 0.3/0.35 degrees Typ
Total harmonic distortion f = 1 MHz, V
O
= 2 V
PP
, ac-coupled I/O –61 dB Typ
Signal-to-noise ratio NTC-7 weighting, 100 kHz to 4.2 MHz 73 dB Typ
Channel-to-channel crosstalk f = 1 MHz, output-referred –65 dB Typ
AC gain, all channels 14.3 14/14.6 14/14.6 14/14.6 dB Min/Max
Output impedance f = 1 MHz 0.8 ΩTyp
DC PERFORMANCE
Bias output voltage V
IN
= 0 V 235 80/390 68/415 48/420 mV Min/Max
Input voltage range Limited by output –0.1/0.9 V Typ
Sync tip clamp charge current V
IN
= –0.1 V 200 μA Typ
Input resistance 800 k ΩTyp
Input capacitance 2 pF Typ
OUTPUT CHARACTERISTICS
R
L
= 150 Ωto 2.5 V 4.85 V Typ
R
L
= 150 Ωto GND 4.7 4.4 4.3 4.25 V MinHigh output voltage swing
R
L
= 75 Ωto 2.5 V 4.8 V Typ
R
L
= 75 Ωto GND 4.5 V Typ
R
L
= 150 Ωto 2.5 V (V
IN
= –0.15 V) 0.2 V Typ
R
L
= 150 Ωto GND (V
IN
= –0.15 V) 0.05 0.14 0.16 0.18 V MaxLow output voltage swing
R
L
= 75 Ωto 2.5 V (V
IN
= –0.15 V) 0.35 V Typ
R
L
= 75 Ωto GND (V
IN
= –0.15 V) 0.07 V Typ
Sourcing 90 mA TypOutput current R
L
= 10 Ωto 2.5 VSinking 85 mA Typ
POWER SUPPLY
Maximum operating voltage 5 5.5 5.5 5.5 V Max
Minimum operating voltage 5 2.85 2.85 2.85 V Min
Maximum quiescent current V
IN
= 0 V 16.5 22 24 25 mA Max
Minimum quiescent current V
IN
= 0 V 16.5 12.5 12 11.5 mA Min
Power supply rejection (+PSRR) 44 dB Typ
(1) The Min/Max values listed for this specification are specified by design and characterization only.
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PIN CONFIGURATION
5
8
7
6
1
2
3
4
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
THS7315
SLOS532 – JUNE 2007
SOIC-8 (D)(Top View)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNO.NAME (SOIC-8)
CH. 1 IN 1 I Video Input, Channel 1
CH. 2 IN 2 I Video Input, Channel 2
CH. 3 IN 3 I Video Input, Channel 3
V
S+
4 I Positive Power Supply Pin. Connect to 3 V to 5 V.
GND 5 I Ground pin for all internal circuitry.
CH. 3
6 O Video Output, Channel 3OUT
CH. 2
7 O Video Output, Channel 2OUT
CH. 1
8 O Video Output, Channel 1OUT
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FUNCTIONAL BLOCK DIAGRAM
+
-
+
-
+
-
+VS
+VS
+VS
Channel1
Input
Channel2
Input
Channel3
Input
800kW
800kW
800kW
gm
gm
gm
Sync-Tip
Clamp
(DCrestore)
Sync-Tip
Clamp
(DCrestore)
Sync-Tip
Clamp
(DCrestore)
Level
Shift
Level
Shift
Level
Shift
LPF
LPF
LPF
5-Pole
8.5MHz
5-Pole
8.5MHz
5-Pole
8.5MHz
5.2V/V
5.2V/V
5.2V/V
+3Vto+5V
Channel1
Output
Channel2
Output
Channel3
Output
TEST CIRCUITS
+
5
8
7
6
1
2
3
4
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
+VS
RTERM
RTERM
RTERM
RLOAD
RLOAD
RLOAD
RSOURCE
VSOURCE
100 Fm
0.1 Fm
+
+
+
+
5
8
7
6
1
2
3
4
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
CIN
CIN
CIN
+VS
RTERM
RTERM
RTERM
RLOAD
RLOAD
RLOAD
RSOURCE
VSOURCE
470 Fm
470 Fm
470 Fm
0.1 Fm
0.1 Fm
0.1 Fm
100 Fm
0.1 Fm
THS7315
SLOS532 – JUNE 2007
Figure 1. DC-Coupled Input and Output Test Circuit Figure 2. AC-Coupled Input and Output Test Circuit
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APPLICATION INFORMATION
OPERATING VOLTAGE
INPUT VOLTAGE
THS7315
SLOS532 – JUNE 2007
The THS7315 is targeted for standard definition (SD) video output buffer applications. Although it can be usedfor numerous other applications, the needs and requirements of the video signal are the most important designparameters of the THS7315. Built on the revolutionary complementary silicon-germanium (SiGe) BiCom3process, the THS7315 incorporates many features not typically found in integrated video parts while consumingvery low power.
The THS7315 has the following features:•Single-supply 3-V to 5-V operation with low total quiescent current of 15.6 mA at 3.3 V and 16.5 mA at 5 V.•Input configuration accepting dc + level-shift, ac sync-tip clamp, or ac bias selection; ac-biasing isaccomplished with the use of an external pull-up resistor to the positive power supply.•5th-order low-pass filter for DAC reconstruction or ADC image rejection:– 8.5-MHz for NTSC, PAL, SECAM, Composite (CVBS), S-Video Y'C', 480i/576i Y'P'
B
P'
R
, and G'B'R'(R'G'B') signals.•Internal fixed gain of 5.2 V/V (+14.3 dB) buffer that can drive up to two video lines per channel with dccoupling or traditional ac coupling.•Signal flow-through configuration using an 8-pin SOIC package that complies with the latest lead-free (RoHScompatible) and green manufacturing requirements.
The THS7315 is designed to operate from 3 V to 5 V over a –40 °C to +85 °C temperature range. The impact onperformance over the entire temperature range is negligible because of the implementation of thin film resistorsand high-quality, low temperature coefficient capacitors. The design of the THS7315 allows operation down to2.85 V, but for best results, the use of a 3 V or greater supply should be used to ensure there are no issues withheadroom or clipping.
A 0.1- μF to 0.01- μF capacitor should be placed as close as possible to the power-supply pins. Failure to do somay result in the THS7315 outputs ringing or oscillating. Additionally, a large capacitor, such as 22 μF to100 μF, should be placed on the power-supply line to minimize interference with 50-Hz/60-Hz line frequencies.
The THS7315 input range allows for an input signal range from –0.3 V to approximately (V
S+
– 1.5V). However,because of the internal fixed gain of 5.2 V/V (+14.3 dB) and the internal level shift that shifts the output by230 mV, the output is generally the limiting factor for the allowable linear input range. For example, with a 5-Vsupply, the linear input range is from –0.3 V to +3.5 V. As a result of the gain and level shift, the linear outputrange limits the allowable linear input range from about –0.1 V to +2.3 V.
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INPUT OVERVOLTAGE PROTECTION
TYPICAL CONFIGURATION and VIDEO TERMINOLOGY
DaVinci/
DM2xx/
DM3xx/
OMAPTM
CVBS
Y’
C’
75 W
Y’
OUT
75 W
C’
OUT
75 W
+1.8V
75 W
75 W
SDTV
CVBS
S-Video Y’
S-VideoC’
480i/576i
Y’P’ P’
G’B’R’
B R
75 W
S-Video
500 W
500 W
500 W
5
8
7
6
1
2
3
4
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
CVBS
OUT
+
+
+
+3.3V 22 Fm
0.1 Fm
0.1 Fm
330 Fm
330 Fm
Gain=
5.2V/V
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
The THS7315 is built using a very high-speed complementary bipolar and CMOS process. The internal junctionbreakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected inthe Absolute Maximum Ratings table. All input and output device pins are protected with internal ESD protectiondiodes to the power supplies, as shown in Figure 3 .
Figure 3. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. Theprotection diodes can typically support 30 mA of continuous current when overdriven.
A typical application circuit using the THS7315 as a video buffer is shown in Figure 4 . It shows a video DACoutput, such as the DaVinci, driving the three input channels of the THS7315. Although the S-Video Y’/C’channels and the composite video (CVBS) channel of an SD video system are shown, these channels can easilybe the Y’P’
B
P’
R
(sometimes labeled Y’U’V’ or incorrectly labeled Y’C’
B
C’
R
) signals of a 480i or 576i system.These signals can also be G’B’R’ (R'G'B') signals or other variations. Note that for computer signals, the syncshould be embedded within the signal for a system with only three outputs. This configuration is sometimeslabeled as R’G’sB’ (sync on green) or R’sG’sB’s (sync on all signals).
Figure 4. Typical SDTV CVBS/Y'/C' Inputs From DC-Coupled Encoder/DACWith AC-Coupled Line Driving
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INPUT MODE OF OPERATION—DC
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
Note that the Y' term is used for the luma channels throughout this document rather than the more commonluminance (Y) term. The reason for this usage is to account for the definition of luminance as stipulated by theCIE (International Commission on Illumination). Video departs from true luminance because a nonlinear term,gamma, is added to the true RGB signals to form R'G'B' signals. These R'G'B' signals are then used tomathematically create luma (Y'). Therefore, true luminance (Y) is not maintained, and thus a difference interminology arises.
This rationale is also used for the chroma (C') term. Chroma is derived from the nonlinear R'G'B' terms andtherefore it is also nonlinear. True chominance (C) is derived from linear RGB, and thus the difference betweenchroma (C') and chrominance (C) exists. The color difference signals (P'
B
/ P'
R
/U'/V') are also referenced this wayto denote the nonlinear (gamma-corrected) signals.
R'G'B' (commonly mislabeled RGB) is also called G'B'R' (again commonly mislabeled as GBR) in professionalvideo systems. The SMPTE component standard stipulates that the luma information is placed on the firstchannel, the blue color difference is placed on the second channel, and the red color difference signal is placedon the third channel. This approach is consistent with the Y'P'
B
P'
R
nomenclature. Because the luma channel (Y')carries the sync information and the green channel (G') also carries the sync information, it makes logical sensethat G' be placed first in the system. Since the blue color difference channel (P'
B
) is next and the red colordifference channel (P'
R
) is last, then it also makes logical sense to place the B' signal on the second channeland the R' signal on the third channel, respectively. Thus, hardware compatibility is better achieved when usingG'B'R' rather than R'G'B'. Note that for many G'B'R' systems, sync is embedded on all three channels; thisconfiguration may not always be the case for all systems.
The THS7315 allows for both ac-coupled and dc-coupled inputs. Many DACs or video encoders can bedc-connected to the THS7315. One of the drawbacks to dc-coupling, however, occurs when 0 V is applied to theinput. Although the THS7315 allows for a 0-V input signal with no issues, the output swing of a traditionalamplifier cannot yield a 0-V signal, resulting in possible clipping. This condition is true for any single-supplyamplifier because of the output transistor limitations. Both CMOS and bipolar transistors cannot go to 0 V whilesinking current. This transistor characteristic is also the same reason why the highest output voltage is alwaysless than the power-supply voltage when sourcing current.
This output clipping can reduce both the horizontal and vertical sync amplitudes on the video signal. A problemoccurs if the video signal receiver uses an AGC loop to account for losses in the transmission line. Some videoAGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on the sync amplitude, then theAGC circuit can increase the gain too much—resulting in too much luma and/or chroma amplitude gaincorrection. This effect may result in a picture with an overly bright display and too much color saturation.
Other AGC circuits use the chroma burst amplitude for amplitude control, and a reduction in the sync signalsdoes not alter the proper gain setting. However, it is good engineering design practice to ensure that saturationand/or clipping does not take place. Transistors always take a finite amount of time to come out of saturation.This saturation could possibly result in timing delays or other signal aberrations.
To eliminate saturation or clipping problems, the THS7315 has a 230 mV output level shift feature. This featuretakes the input voltage and adds an internal level shift to the signal. The THS7315 rail-to-rail output stage cancreate this output level while connected to a typical video load. This process ensures that no saturation orclipping of the sync signal occurs. This level shift is constant, regardless of the input signal. For example, if a0.5-V input is applied, the output is at (0.5 V ×5.2 V/V) + 0.23 V = 2.92 V.
The fixed internal gain of 5.2 V/V (14.3 dB) dictates what the allowable linear input voltage range can be withoutclipping concerns. For example, if the power supply is set to 3 V, the maximum output is about 2.9 V whiledriving a significant amount of current. Thus, to avoid clipping, the allowable input will be [ (3.1 V – 0.23 V) / 5.2V/V) ] = 0.55 V. This relationship holds true up to the maximum recommended 5 V power supply that allows anapproximate input range of [ (4.9 V – 0.23 V) / 5.2 V/V) ] = 0.9 V while avoiding clipping on the output.
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+
-
800kW
Input
Internal
Circuitry
InternalLevel
Shifter
+VS
INPUT MODE OF OPERATION —AC SYNC-TIP CLAMP
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
The THS7315 input impedance in this operating mode is dictated by the internal 800-k Ωpull-down resistor, asshown in Figure 5 . Note that the internal voltage shift does not appear at the input pin, but only at the output pin.
Figure 5. Equivalent DC Input Mode Circuit
Some video DACs or encoders are not referenced to ground but rather to the positive power supply. TheseDACs typically only sink current, rather than the more traditional current-sourcing DAC where the resistor isreferenced to ground. The resulting video signal voltages can be too high for a dc-coupled video buffer tofunction properly. To account for this scenario, the THS7315 incorporates a sync-tip clamp (STC) circuit. Thisfunction requires a capacitor (nominally 0.1 μF) to be placed in series with the input. Note that while the termsync-tip clamp or STC is used throughout this document, it should be noted that the THS7315 is better termedas a dc-restoration circuit based on how this function is performed. The STC circuit is an active clamp circuit andnot a passive diode clamp function.
The input to the THS7315 has an internal control loop that sets the lowest input-applied voltage to clamp atground (0 V). By setting the reference at 0 V, the THS7315 allows a dc-coupled input to also function. Therefore,the STC is considered transparent because it does not operate unless the input signal goes below ground. Thesignal then goes through the same internal level shifter, resulting in an output voltage low level of 230 mV. If theinput signal tries to go below 0 V, the internal control loop of the THS7315 will source up to 2 mA of current toincrease the THS7315 input voltage level on the input side of the coupling capacitor. As soon as the voltagegoes above 0 V, the loop will stop sourcing current and become very high impedance.
One of the concerns about the STC level is how the clamp reacts to a sync edge that has overshoot—acommon effect in VCR signals or reflections found in poor PCB layouts. Ideally, the STC should not react to theovershoot voltage of the input signal. Otherwise, this effect could result in clipping on the rest of the video signalbecause it may raise the bias voltage too much.
To help minimize this input signal overshoot problem, the control loop in the THS7315 has an internal low-passfilter as shown in Figure 6 . This filter reduces the response time of the STC circuit. This delay is a function ofhow far the voltage is below ground, but generally, it is about a 100-ns delay. The effect of this filter is to slowdown the response of the control loop so as not to clamp on the input overshoot voltage, but rather the flatportion of the sync signal.
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+
-
STCLPF
Comparator
+
-
Input
Pin
Input
0.1 Fm
Internal
Circuitry
InternalLevel
Shifter
+VS+VS
800kW
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
Figure 6. Equivalent AC Sync-Tip Clamp Input Circuit
As a result of the delay, the sync may have an apparent voltage shift. The amount of shift depends on theamount of droop in the signal as dictated by the input capacitor and the STC current flow. Because the sync isprimarily for timing purposes—with syncs occurring on the edge of the sync signal—this shift is transparent inmost systems.
While this feature may not fully eliminate overshoot issues on the input signal in cases of extreme overshootand/or ringing, the STC system should help minimize improper clamping levels. As an additional way tominimize this problem, an external capacitor (for example, 10 pF to 47 pF) to ground in parallel with the externaltermination resistors can help filter overshoot problems.
It should be noted that the STC system is dynamic and does not rely upon timing in any way. It only depends onthe voltage appearing at the input pin at any given point in time. The STC filtering helps minimize level shiftproblems associated with switching noises or very short spikes on the signal line, ensuring a very robust STCsystem.
When using the ac sync-tip clamp operation, there must also be some finite amount of discharge bias current.As previously discussed, if the input signal goes below the 0 V clamp level, the THS7315 internal loop willsource current to increase the voltage appearing at the input pin. As the difference between the signal level andthe 0 V reference level increases, the amount of source current increases proportionally—supplying up to 2 mAof current. As a result, the time to re-establish the proper STC voltage can be very short. If this difference is verysmall, then the source current will also be very small to account for minor voltage droop.
What happens if the input signal goes above the 0 V input level? The problem is that the video signal will alwaysbe above this level and must not be altered in any way. If the sync level of the input signal is above 0 V,however, then the internal discharge (sink) current will reduce the ac-coupled bias signal to the proper 0 V level.
This discharge current must not be large enough to significantly alter the video signal, or picture quality issuesmay arise. This effect is often seen by looking at the tilt (or droop) of a constant luma signal being applied andobserving the resulting output level. The associated change in luma level from the beginning of the video line tothe end of the video line is the amount of droop.
If the discharge current is very small, the amount of tilt (or droop) is very low, which is a generally a good thing.Unfortunately, the amount of time for the system to capture the sync signal could be too long. This effect is alsotermed hum rejection. Hum arises from the ac line voltage frequency of 50 Hz or 60 Hz. The values of thedischarge current and the ac-coupling capacitor combine to dictate the hum rejection and the amount of line tilt.
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INPUT MODE OF OPERATION —AC BIAS
+
-
Input
Pin
800kW
Input
CIN
Internal
Circuitry
InternalLevel
Shifter
+3.3V +3.3V
9.31MW
VDC +VSǒ800k
800k )RPUǓ
(1)
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
To allow for both dc-coupling and ac-coupling in the same part, the THS7315 incorporates an 800-k Ωresistor toground. Although a true constant current sink is preferred over a resistor, there are significant issues when thevoltage is near ground. (For example, voltage near ground can cause the current sink transistor to saturate andproduce potential signal problems.) This resistor is large enough to not impact a dc-coupled DAC termination.For discharging an ac-coupled source, Ohm's Law is utilized. If the video signal is 0.5 V, then there will be 0.5 V/ 800 k Ω= 0.625 μA of discharge current. If more hum rejection is desired or there is a loss of sync occurring,simply decrease the 0.1 μF input coupling capacitor. A decrease from 0.1 μF to 0.047 μF increases the humrejection by a factor of 2:1. Alternatively, an external pull-down resistor to ground may be added, decreasing theoverall resistance and ultimately increasing the discharge current.
To ensure proper stability of the ac STC control loop, the source impedance must be less than 1 k Ωwith theinput capacitor in place. Otherwise, there is a possibility of the control loop ringing. This ringing may appear onthe THS7315 output. Because most DACs or encoders use resistors that are typically ≤500 Ωto establish thevoltage, meeting the < 1 k Ωrequirement is easily done. However, if the source impedance looking from theTHS7315 input is very high, then simply adding a 1-k Ωresistor to GND will ensure proper operation of theTHS7315.
Sync-tip clamps work very well for signals that have horizontal and/or vertical syncs associated with them. Somevideo signals, on the other hand, do not have a sync embedded within the signal. If ac-coupling of these signalsis desired, then a dc bias is required to properly set the dc operating point within the THS7315. This function iseasily accomplished with the THS7315 by simply adding an external pull-up resistor to the positive powersupply, as shown in Figure 7 .
Figure 7. AC-Bias Input Mode Circuit Configuration
The dc voltage appearing at the input pin is approximately equal to:
The allowable input range of the THS7315 is very wide: approximately (+V
S
– 1.5 V). The input range is limitedby the allowable output voltage range and the internal gain. As such, the input dc bias point is very flexible, withthe output dc bias point being the primary factor. For example, if the desired output dc bias point is 1.6 V on a3.3-V supply, then the input dc bias point should be (1.6 V – 230 mV) / 5.2 = 0.263 V. Consequently, the pull-upresistor calculates to be about 9.31 M Ω, resulting in 0.261 V. If the desired input dc-bias point is 2.4 V with a 5-Vpower supply, then the pull-up resistor calculates to be about 8.66 M Ω.
Keep in mind that the internal 800-k Ωresistor has approximately a ±20% variance. As such, the calculationsshould account for this variance. For the 0.261 V example above, using an ideal 9.31-M Ωresistor, the input dcbias voltage is about 0.261 V ±0.05 V, which translates to an output bias voltage of about 1.64 V ±0.26 V.
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OUTPUT MODE OF OPERATION—DC-COUPLED
DAC/Encoder
(DaVinciTM)CVBS
Y’
C’
75 W
Y’
OUT
75 W
C’
OUT
75 W
+1.8V
75 W
75 W
SDTV
CVBS
S-Video Y’
S-VideoC’
480i/576i
Y’P’ P’
G’B’R’
B R
75 W
S-Video
500 W
500 W
500 W
5
8
7
6
1
2
3
4
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
THS7315
CVBS
OUT
+
+3.3V 22 Fm
0.1 Fm
Gain=
5.2V/V
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
One other issue that must be taken into account is the dc-bias point. The dc-bias point is a function of the powersupply. As such, there is as a low-pass filter. Additionally, the time to charge the capacitor to the final dc biaspoint is also a function of the pull-up resistor and the input capacitor. Lastly, the input capacitor forms ahigh-pass filter with the parallel impedance of the pull-up resistor and the 800-k Ωresistor. Generally, it is good tohave this high-pass filter at about 3 Hz to minimize any potential droop on a P'
B
, P'
R
, or non-sync B' or R' signal.A 0.1- μF input capacitor with a 9.31-M Ωpull-up resistor equals about a 2.2-Hz high-pass corner frequency.
This mode of operation is recommended for use with chroma (C'), P’
B
, P'
R
, U', V', and non-sync B' and/or R'signals.
The THS7315 incorporates a rail-to-rail output stage that can be utilized to drive the line directly without theneed for large ac-coupling capacitors, as shown in Figure 8 . This architecture offers the best line tilt and field tilt(or droop) performance because no ac coupling occurs. Keep in mind that if the input is ac-coupled, then theresulting tilt arising from the input ac coupling is still seen on the output, regardless of the output coupling. The80-mA output current drive capability of the THS7315 was designed to drive two video lines per channelsimultaneously—essentially, a 75- Ωload—while keeping the output dynamic range as wide as possible.
Figure 8. Typical SDTV CVBS/Y'/C' System with DC-Coupled Line Driving
One concern about dc coupling arises when the line is terminated to ground. If the ac-bias input configuration isused, the THS7315 output has a dc bias on the output. With two lines terminated to ground, this configurationcreates a dc current path, resulting in a slightly decreased high output voltage swing as well as an increase indevice power dissipation. While the THS7315 was designed to operate with junction temperatures of up to+125 °C, care must be taken to ensure that the junction temperature does not exceed this level; otherwise,long-term reliability could suffer. Although this configuration only adds less than 10 mW of power dissipation perchannel, the overall low power dissipation of the THS7315 design minimizes potential thermal issues even whenusing the SOIC package at high ambient temperatures.
Note that the THS7315 can drive the line with dc coupling regardless of the input mode of operation. The onlyrequirement is to verify that the video line has proper termination in series with the output (typically 75 Ω). Thistermination also helps isolate capacitive loading effects from the THS7315 output. Failure to isolate capacitiveloads may result in instabilities with the output buffer, potentially causing ringing or oscillating to appear. Thestray capacitance appearing directly at the THS7315 output pins should be kept below 25 pF.
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OUTPUT MODE OF OPERATION—AC-COUPLED
75 W
+
75 W
+
75 W
+
75 W
+
Y’
OUT2
OUT2
OUT2
75 W
+
Y’
OUT1
OUT1
OUT1
75 W
75 W
75 W
75 W
75 W
75 W
75 W
+
5
8
7
6
1
2
3
4
Y’
P’B
P’R
+
R
R
+1.8V
R
+1.8V
+3.3V
+3.3V
9.31MW
9.31MW
0.1 Fm
0.1 Fm
0.1 Fm0.1 Fm
22 Fm
VS+ GND
CH.2IN
CH.3IN
CH.1IN
CH.3OUT
CH.2OUT
CH.1OUT
DAC/
Encoder
+3.3V
+1.8V
+1.8V
330 Fm(1)
330 Fm(1)
330 Fm(1)
330 Fm(1)
330 Fm(1)
330 Fm(1)
SDTV
480i/576i
Y’P’ P’
G’B’R’
B R
THS7315
P’B
P’B
P’R
P’R
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
The most common method of coupling the video signal to the line is through the use of a large capacitor. Thiscapacitor is typically between 220 μF and 1000 μF, although 330 μF is very common. The value of this capacitormust be this large to minimize the line tilt (droop) and/or field tilt associated with ac coupling as discussedpreviously in this document. AC coupling is done for several reasons; generally, it is done to ensure fullinteroperability with the receiving video system. This coupling eliminates possible ground loops. It also ensuresthat regardless of the reference dc voltage used on the transmit side, the receive side will re-establish the dcreference voltage to its own requirements.
In the same way that the dc output mode of operation is configured (as discussed earlier), each line should havea 75- Ωsource termination resistor in series with the ac-coupling capacitor. If driving two lines, it is best to haveeach line use its own capacitor and resistor rather than sharing these components, as Figure 9 shows. Thisconfiguration helps ensure line-to-line dc isolation and avoids the potential problems discussed earlier. Using asingle 1000- μF capacitor for two lines can be done, but there is a chance for ground loops and additionalinterference to be created between the two receivers.
(1) As a result of the high frequency content of the video signal, it is recommended, but not required, to add a 0.1- μF or0.01- μF capacitor in parallel with these large capators.
(2) Current sinking DAC / Encoder shown. See the application notes.
Figure 9. Typical 480i/576i Y'P'
B
P'
R
AC-Input System Driving Two AC-Coupled Video Lines
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LOW-PASS FILTER
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
Lastly, because of the edge rates and frequencies of operation, it is recommended (but not required) to place a0.1- μF to 0.01- μF capacitor in parallel with the large 220- μF to 1000- μF capacitor. These large-value capacitorsare generally aluminum electrolytic. It is well-known that these types of capacitors have significantly largeequivalent series resistance, or ESR, and the respective impedances at high frequencies is rather large as aresult of the associated inductances involved with the leads and construction. The small 0.1- μF to 0.01- μFcapacitors help to pass these high-frequency ( greater than 1 MHz) signals with much lower impedance than thelarge capacitors.
Although it is common to use the same capacitor values for all the video lines, the frequency bandwidth of thechroma signal in an S-Video system is not required to go to as low (or as high) a frequency as the lumachannels. Therefore, the capacitor values of the chroma line(s) can be smaller, such as 0.1 μF.
Each channel of the THS7315 incorporates a 5th-order low-pass filter. These video reconstruction filtersminimize DAC images from passing on to the video receiver. Depending on the receiver design, failure toeliminate these DAC images can cause picture quality problems that result from ADC aliasing. Another benefit ofthe filter is that it smooths out aberrations in the signal that some DACs can demonstrate if the internal filtering isnot good. These benefits help with picture quality and ensure that the signal meets video bandwidthrequirements.
Each filter has an associated Butterworth characteristic. The benefit of the Butterworth response is that thefrequency response is flat, with a relatively steep initial attenuation at the corner frequency. The problem with theButterworth filter, however, is that the group delay also rises near the corner frequency. Group delay is definedas the change in phase (radians/second) divided by a change in frequency. An increase in group delaycorresponds to a time-domain pulse response that has overshoot (and possible ringing associated with theovershoot).
Other filter types (such as elliptic or chebyshev) are not recommended for video applications because of the verylarge group delay variations that occur near the corner frequency, also resulting in significant overshoot andringing. While elliptic or chebyshev filters may help meet the video standard specifications with respect toamplitude attenuation, the group delay is well beyond the standard specifications. Combined with the fact thatvideo can switch from a white pixel to a black pixel over and over again, ringing can easily occur. Ringingtypically causes a display to have ghosting or fuzziness on the edges of a sharp transition. On the other hand, aBessel filter has ideal group delay response, but the rate of attenuation is typically too low for acceptable imagerejection. Consequently, the Butterworth filter is a respectable compromise for both attenuation and group delay.
The THS7315 filters have a nominal corner (–3 dB) frequency at 8.5 MHz and a –1 dB passband, typically at 7MHz. This 8.5-MHz filter is ideal for SDTV, NTSC, PAL, and SECAM composite video (CVBS) signals. It is alsouseful for S-Video signals (Y'C'), 480i/576i Y'P'
B
P'
R
, Y'U'V', broadcast G'B'R' signals, and computer R'G'B' videosignals. The 8.5-MHz, –3-dB corner frequency was designed to allow a maximally flat video signal whileachieving 47 dB of attenuation at 27 MHz—a common sampling frequency between the DAC/ADC 2nd and 3rdNyquist zones that is found in many video systems. This feature is important because any signal appearingaround this frequency can appear in the baseband because of aliasing effects of an ADC found in a receiver.
Keep in mind that images do not stop at 27 MHz; they continue around the sampling frequencies of 54 MHz, 81MHz, 108 MHz, and so forth. Because of these multiple images that an ADC can fold down into the basebandsignal, the low-pass filter must also eliminate these higher-order images. The THS7315 has over 70-dBattenuation at 54 MHz and 81 MHz, along with over 65-dB attenuation at 108 MHz. Attenuation above 108 MHzis at least 55 dB, ensuring that images do not affect the desired video baseband signal.
The 8.5-MHz filter frequency was chosen to account for process variations in the THS7315. To ensure therequired video frequencies are effectively passed, the filter corner frequency must be high enough to allowcomponent variations. The other filter design consideration is the attenuation. It must be large enough to ensurethat anti-aliasing/reconstruction filtering is enough to meet the system demands. Thus, the filter frequencyselection was not arbitrary; it is a good compromise that should meet the demands of most systems.
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ADVANTAGES OVER PASSIVE FILTERING
THS7315
SLOS532 – JUNE 2007
APPLICATION INFORMATION (continued)
Two key benefits of using an integrated filter system such as the THS7315 over a passive system are PCB areaand filter variations. For overall board area, the small SOIC-8 package for 3-video channels is much smaller overa passive RLC network, especially a 5-pole passive network. As for filter variations, consider that inductorsgenerally have 10% tolerances (normally 15% to 20%) and capacitors typically have 10% tolerances. A MonteCarlo analysis shows that the desired filter corner frequency (–3 dB), flatness (–1 dB), Q-factor (or peaking), andchannel-to-channel delay will have wide variations. These variations can lead to potential performance andquality issues in mass-production environments. The THS7315 solves most of these problems with the cornerfrequency being the only variable.
One concern about using an active filter in an integrated circuit is the variation of the filter characteristics whenthe ambient temperature and the subsequent die temperature change. To minimize temperature effects, theTHS7315 uses low temperature coefficient resistors and high quality/low temperature coefficient capacitorsfound in the BiCom3 process. The filters have been specified by design to account for process and temperaturevariations to maintain proper filter characteristics. This design guideline maintains a low channel-to-channel timedelay that is required for proper video signal performance.
The input and output impedances are another benefit of the THS7315 over a passive RLC filter. The inputimpedance presented to the DAC varies significantly with a passive network and may cause voltage variationsover frequency. The THS7315 input impedance is 800 k Ω; only the 2-pF input capacitance plus the PCB tracecapacitance affect this value. As such, the voltage variation appearing at the DAC output is better controlled withthe THS7315.
On the output side of the filter, a passive filter again has an impedance variation over frequency. The THS7315is an operational amplifier that approximates an ideal voltage source. A voltage source is desirable because theoutput impedance is very low and can source and sink current. To properly match the transmission linecharacteristic impedance of a video line, a 75- Ωseries resistor is placed on the output. To minimize reflectionsand to maintain a good return loss, this output impedance must maintain a 75- Ωimpedance. A passive filterimpedance variation cannot specify this condition, while the THS7315 has about 0.8 Ωof output impedance at 1MHz. Thus, the system is matched much better with a THS7315 when compared to a passive filter.
One final benefit of the THS7315 over a passive filter is power dissipation. A DAC driving a video line must beable to drive a 37.5- Ωload—the receiver 75- Ωresistor and the 75- Ωimpedance-matching resistor next to theDAC to maintain the source impedance requirement. This design requirement forces the DAC to drive at least1.25 V
PP
(100% saturation CVBS) / 37.5 Ω= 33.3 mA. A DAC is a current-steering element, and this amount ofcurrent flows internally to the DAC even if the output is 0 V. Thus, power dissipation in the DAC may be veryhigh, especially when six channels are being driven. Using the THS7315, with a high input impedance and thecapability to drive up to two video lines, can reduce the DAC power dissipation significantly. This reductionoccurs because the resistance that the DAC is driving can be substantially increased. It is common to set thisincrease in a DAC by a current-setting resistor on the device. Thus, the resistance can be 300 Ωormore—significantly reducing the current drive demands from the DAC and saving a substantial amount of power.For example, a 3.3-V, six-channel DAC dissipates 660 mW just for the steering current capability (6 channels ×33.3 mA ×3.3 V) if it needs to drive 37.5- Ωload. With a 300- Ωload, the DAC power dissipation as a result ofcurrent steering current would only be 82.5 mW (6 channels ×4.16 mA ×3.3 V).
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EVALUATION MODULE
THS7315
SLOS532 – JUNE 2007
To evaluate the THS7315, an evaluation module (EVM) is available. The EVM allows for testing the THS7315 inmany different systems. Inputs and outputs include RCA connectors for consumer grade interconnections, orBNC connectors for higher-level lab grade connections. Several unpopulated component pads are found on theEVM to allow for different input and output configurations as dictated by the user.
Figure 10 shows the THS7315EVM schematic. Figure 11 and Figure 12 illustrate the top layer and bottom layer(respectively) of the EVM PCB, incorporating standard high-speed layout practices. Table 1 lists the bill ofmaterials as supplied from Texas Instruments.
Figure 10. THS7315D EVM Schematic
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THS7315
SLOS532 – JUNE 2007
EVALUATION MODULE (continued)
Figure 11. THS7315D EVM PCB Top Layer
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THS7315
SLOS532 – JUNE 2007
EVALUATION MODULE (continued)
Figure 12. THS7315D EVM PCB Bottom Layer
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THS7315EVM Bill of Materials
THS7315
SLOS532 – JUNE 2007
EVALUATION MODULE (continued)
Table 1. THS7315D EVM
MANUFACTURER DISTRIBUTORITEM REF DES QTY DESCRIPTION SMD SIZE PART NUMBER PART NUMBER
1 FB1 1 Bead, Ferrite, 2.5A, 330 Ω0805 (TDK) MPZ2012S331A (Digi-Key) 445-1569-1-ND
Capacitor, 100 μF, Tantalum, 10V, 10%, (AVX)2 C16 1 C (Digi-Key) 478-1765-1-NDLow-ESR TPSC107K010R0100
3 C17, C18, C19 3 Open 0603
(Garrett)4 C15 1 Capacitor, 0.1 μF, Ceramic, 16V, X7R 0603 (AVX) 0603YC104KAT2A
0603YC104KAT2A
C1, C2, C3, C12,5 6 OPEN 0805C13, C14
6 C5 1 Capacitor, 0.01 μF, Ceramic, 100V, X7R 0805 (AVX) 08051C103KAT2A (Digi-Key) 478-1358-1-ND
7 C7, C9, C11 3 Capacitor, 0.1 μF, Ceramic, 50V, X7R 0805 (AVX) 08055C104KAT2A (Digi-Key) 478-1395-1-ND
8 C4 1 Capacitor, 1 μF, Ceramic, 16V, X7R 0805 (TDK) C2012X7R1C105K (Digi-Key) 445-1358-1-ND
(Cornell)9 C6, C8, C10 3 Capacitor, Aluminum, 470 μF, 10V, 20% F (Newark) 97C7597AFK477M10F24B
10 RX1–RX6 6 Open 0603
(Digi-Key)11 R4–R9, Z1, Z2, Z3 9 Resistor, 0 Ω0805 (ROHM) MCR10EZHJ000
RHM0.0ACT-ND
R1, R2, R3, R10, (Digi-Key)12 6 Resistor, 75 Ω, 1/8W, 1% 0805 (ROHM) MCR10EZHF75.0R11, R12 RHM75.0CCT-ND
Jack, Banana Receptance, 0.25" dia.13 J9, J10 2 (SPC) 813 (Newark) 39N867hole
J1, J2, J3, J6, J7, (Amphenol)14 6 Connector, BNC, Jack, 75 Ω(Newark) 93F7554J8 31-5329-72RFX
15 J4, J5 2 Connector, RCA, Jack, R/A (CUI) RCJ-32265 (Digi-Key) CP-1446-ND
16 TP1, TP2, TP3 3 Test Point, Red (Keystone) 5000 (Digi-Key) 5000K-ND
17 TP4, TP5 2 Test Point, Black (Keystone) 5001 (Digi-Key) 5001K-ND
18 U1 1 IC, THS7315 D (TI) THS7315D
19 4 Standoff, 4-40 Hex, 0.625" Length (Keystone) 1808 (Newark) 89F1934
20 4 Screw, Phillips, 4-40, .250" (BF) PMS 440 0031 PH (Digi-Key) H343-ND
21 1 Printed circuit board Edge # 6483760 REV. A
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OREVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for generalconsumer use. Persons handling the product(s) must have electronics training and observe good engineeringpractice standards. As such, the goods being provided are not intended to be complete in terms of requireddesign-, marketing-, and/or manufacturing-related protective considerations, including product safety andenvironmental measures typically found in end products that incorporate such semiconductor components orcircuit boards. This evaluation board/kit does not fall within the scope of the European Union directivesregarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, andtherefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may bereturned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THEEXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY ORFITNESS FOR ANY PARTICULAR PURPOSE.
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THS7315
SLOS532 – JUNE 2007
EVALUATION BOARD/KIT IMPORTANT NOTICE (continued)
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the userindemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of theproduct, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostaticdischarge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLETO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is notexclusive.
TI assumes no liability for applications assistance, customer product design, software performance, orinfringement of patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide priorto handling the product. This notice contains important safety information about temperatures and voltages. Foradditional information on TI’s environmental and/or safety programs, please contact the TI application engineeror visit www.ti.com/esh .
No license is granted under any patent right or other intellectual property right of TI covering or relating to anymachine, process, or combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OREVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for generalconsumer use. It generates, uses, and can radiate radio frequency energy and has not been tested forcompliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed toprovide reasonable protection against radio frequency interference. Operation of this equipment in otherenvironments may cause interference with radio communications, in which case the user at his own expensewill be required to take whatever measures may be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 2.85 V to 5.5 V single supply and theoutput voltage range of 0 V to 5.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.If there are questions concerning the input range, please contact a TI field representative prior to connectingthe input power.
Applying loads outside of the specified output range may result in unintended operation and/or possiblepermanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVMoutput. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +85 ＝C. TheEVM is designed to operate properly with certain components above +85 ＝C as long as the input and outputranges are maintained. These components include but are not limited to linear regulators, switching transistors,pass transistors, and current sense resistors. These types of devices can be identified using the EVMschematic located in the EVM User's Guide. When placing measurement probes near these devices duringoperation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2007, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
THS7315D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 7315
THS7315DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 7315
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Addendum-Page 2
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS7315DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS7315DR SOIC D 8 2500 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
THS7315D D SOIC 8 75 506.6 8 3940 4.32
Pack Materials-Page 3
‘J
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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