Texas Instruments 的 TAS5132 规格书

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FEATURES
APPLICATIONS
DESCRIPTION
PVDD − Supply Voltage − V
0
5
10
15
20
25
30
0 5 10 15 20
PO − Output Power − W
8 Ω
TC = 75°C
THD+N @ 10%
6 Ω
G002
TAS5132
SLES190 – DECEMBER 2006
STEREO DIGITAL AMPLIFIER POWER STAGE
A low-cost, high-fidelity audio system can be builtusing a TI chipset, comprising a modulator (e.g.,•2×20 W at 10% THD+N Into 8- ΩBTL
TAS5086) and the TAS5132. This system only•2×25 W at 10% THD+N Into 6- ΩBTL
requires a simple passive LC demodulation filter todeliver high-quality, high-efficiency audio•>100-dB SNR (A-Weighted)
amplification with proven EMI compliance. This•<0.1% THD+N at 1 W
device requires two power supplies, at 12 V for•Thermally Enhanced Package:
GVDD and VDD, and at 18 V for PVDD. The– DDV (44-pin HTSSOP)
TAS5132 does not require power-up sequencing dueto internal power-on reset. The efficiency of this•High-Efficiency Power Stage (>90%) With
digital amplifier is greater than 90% into 8 Ω, which140-m ΩOutput MOSFETs
enables the use of smaller power supplies and•Power-On Reset for Protection on Power Up
heatsinks.Without Any Power-Supply Sequencing
The TAS5132 has an innovative protection system•Integrated Self-Protection Circuits Including
integrated on chip, safeguarding the device against aUndervoltage, Overtemperature, Overload,
wide range of fault conditions that could damage theShort Circuit
system. These safeguards are short-circuit•PWM Activity Detector to detect stopped PWM protection, overcurrent protection, undervoltageprotection, and overtemperature protection. Theinputs and protect the system
TAS5132 has a new proprietary current-limiting•Error Reporting
circuit that reduces the possibility of device shutdown•EMI Compliant When Used With
during high-level music transients.Recommended System Design
BTL OUTPUT POWER vs SUPPLY VOLTAGE•Intelligent Gate Drive•Pin Compatible With the TAS5142DDV
•Televisions
•Mini/Micro Audio Systems•DVD Receivers
•Home Theaters
The TAS5132 is an integrated stereo digital amplifierpower stage with an advanced protection system.The TAS5132 is capable of driving a 6- Ωbridge-tiedload (BTL) at up to 25 W per channel with lowintegrated noise at the output, low THD+Nperformance, and low idle power dissipation.
PurePath Digital™
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PurePath Digital, PowerPAD are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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GENERAL INFORMATION
Terminal Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GVDD_B
OTW
NC
NC
SD
PWM_A
RESET_AB
PWM_B
OC_ADJ
GND
AGND
VREG
M3
M2
M1
PWM_C
RESET_CD
PWM_D
NC
NC
VDD
GVDD_C
DDV PACKAGE
(TOP VIEW)
GVDD_A
BST_A
NC
PVDD_A
PVDD_A
OUT_A
GND_A
GND_B
OUT_B
PVDD_B
BST_B
BST_C
PVDD_C
OUT_C
GND_C
GND_D
OUT_D
PVDD_D
PVDD_D
NC
BST_D
GVDD_D
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P0016-02
TAS5132
SLES190 – DECEMBER 2006
The TAS5132 is available in a thermally enhanced package:•44-pin HTSSOP PowerPAD™ package (DDV)
This package type contains a heat slug that is located on the top side of the device for convenient thermalcoupling to the heatsink.
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MODE Selection Pins
Package Heat Dissipation Ratings
(1)
TAS5132
SLES190 – DECEMBER 2006
GENERAL INFORMATION (continued)
MODE PINS
PWM INPUT OUTPUT CONFIGURATION PROTECTION SCHEMEM3 M2 M1
0 0 0 2N
(1)
AD/BD modulation 2 channels BTL output BTL mode
(2)
0 0 1 Reserved
0 1 0 1N
(1)
AD modulation 2 channels BTL output BTL mode
(2)
0 1 1 1N
(1)
AD modulation 1 channel PBTL output PBTL mode. Only PWM_A input is used.
Protection works similarly to BTL mode
(2)
. Onlydifference in SE mode is that OUT_X is Hi-Z1 0 0 1N
(1)
AD modulation 4 channels SE output
instead of a pulldown through internal pulldownresistor.
1 0 1 Protection system work similarly to BTL mode(2)
(0, 0, 0); however the PWM input protection2N
(1)
AD/BD modulation 2 channels BTL output
is disabled. Also, overcurrent detection will bemore sensitive and will latch if an error occurs.
1 1 0
Reserved1 1 1
(1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specificmode.
(2) An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errorslike overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.
PARAMETER TAS5132DDV
R
θJC
(°C/W)—2 BTL or 4 SE channels (8 transistors) 1.4
R
θJC
(°C/W)—1 BTL or 2 SE channel(s) (4 transistors) 2.6
R
θJC
(°C/W)—(1 transistor) 8.7
Pad area
(2)
15 mm
2
(1) JC is junction-to-case, CH is case-to-heatsink.(2) R
θCH
is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. TheR
θCH
with this condition is 2.5 °C/W for the DDV package.
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ABSOLUTE MAXIMUM RATINGS
(1)
TAS5132
SLES190 – DECEMBER 2006
over operating free-air temperature range (unless otherwise noted)
VDD to AGND –0.3 V to 13.2 V
GVDD_X to AGND –0.3 V to 13.2 V
PVDD_X to GND_X
(2)
–0.3 V to 30 V
OUT_X to GND_X
(2)
–0.3 V to 30 V
BST_X to GND_X
(2)
–0.3 V to 43.2 V
VREG to AGND –0.3 V to 4.2 V
GND_X to GND –0.3 V to 0.3 V
GND_X to AGND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
RESET_X, SD, OTW to AGND –0.3 V to 7 V
Maximum continuous sink current ( SD, OTW) 9 mA
Maximum operating junction temperature range, T
J
0°C to 150 °C
Storage temperature range –40 °C to 125 °C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
Minimum pulse duration, low 50 ns
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION
T
A
PACKAGE DESCRIPTION
0°C to 70 °C TAS5132DDV 44-pin HTSSOP
For the most current specification and package information, see the TI Web site at www.ti.com.
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TAS5132
SLES190 – DECEMBER 2006
Terminal Functions
TERMINAL
FUNCTION
(1)
DESCRIPTIONNAME NO.
AGND 11 P Analog ground
BST_A 43 P HS bootstrap supply (BST). External capacitor to OUT_A required.
BST_B 34 P HS bootstrap supply (BST). External capacitor to OUT_B required.
BST_C 33 P HS bootstrap supply (BST). External capacitor to OUT_C required.
BST_D 24 P HS bootstrap supply (BST). External capacitor to OUT_D required.
GND 10 P Ground
GND_A 38 P Power ground for half-bridge A
GND_B 37 P Power ground for half-bridge B
GND_C 30 P Power ground for half-bridge C
GND_D 29 P Power ground for half-bridge D
GVDD_A 44 P Gate-drive voltage supply. Requires 0.1- µF capacitor to GND.
GVDD_B 1 P Gate-drive voltage supply. Requires 0.1- µF capacitor to GND.
GVDD_C 22 P Gate-drive voltage supply. Requires 0.1- µF capacitor to GND.
GVDD_D 23 P Gate-drive voltage supply. Requires 0.1- µF capacitor to GND.
M1 15 I Mode selection 1
M2 14 I Mode selection 2
M3 13 I Mode selection 3
3, 4, 19, 20,NC – No connect. Pins may be grounded.25, 42
OC_ADJ 9 O Analog overcurrent programming. Requires resistor to ground.
OTW 2 O Overtemperature warning signal, open drain, active low
OUT_A 39 O Output, half-bridge A
OUT_B 36 O Output, half-bridge B
OUT_C 31 O Output, half-bridge C
OUT_D 28 O Output, half-bridge D
Power supply input for half-bridge A. Requires close decoupling of 0.1- µF capacitorPVDD_A 40, 41 P
to GND_A.
Power supply input for half-bridge B. Requires close decoupling of 0.1- µF capacitorPVDD_B 35 P
to GND_B.
Power supply input for half-bridge C. Requires close decoupling of 0.1- µF capacitorPVDD_C 32 P
to GND_C.
Power supply input for half-bridge D. Requires close decoupling of 0.1- µF capacitorPVDD_D 26, 27 P
to GND_D.
PWM_A 6 I Input signal for half-bridge A
PWM_B 8 I Input signal for half-bridge B
PWM_C 16 I Input signal for half-bridge C
PWM_D 18 I Input signal for half-bridge D
RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active low
RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active low
SD 5 O Shutdown signal, open-drain, active-low
Power supply for digital voltage regulator. Requires 0.1- µF capacitor in parallel with aVDD 21 P
10- µF capacitor to GND.
VREG 12 P Digital regulator supply filter. Requires 0.1- µF capacitor to AGND.
(1) I = input, O = output, P = power
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2nd-Order L-C
Output Filter
for Each
Half-Bridge
Bootstrap
Capacitors
2-Channel
H-Bridge
BTL Mode
System
Microcontroller
OUT_A
OUT_B
OUT_C
OUT_D
BST_A
BST_B
BST_C
BST_D
RESET_AB
RESET_CD
System
Power
Supply
Hardwire
Mode
Control
PVDD
GVDD (12 V)/VDD (12 V)
GND
Hardwire
OC Limit
M1
M3
PVDD
Power
Supply
Decoupling
18 V
12 V
GND
VAC
PWM_A
PWM_C
PWM_D
PWM_B
VALID
M2
Left-
Channel
Output
Right-
Channel
Output
Input
H-Bridge 1
Input
H-Bridge 2
GVDD
VDD
VREG
Power Supply
Decoupling
4
PVDD_A, B, C, D
GND_A, B, C, D
GVDD_A, B, C, D
4 4
VDD
GND
VREG
AGND
OC_ADJ
Bootstrap
Capacitors
2nd-Order L-C
Output Filter
for Each
Half-Bridge
SD
OTW
Output
H-Bridge 2
Output
H-Bridge 1
OTW
SD
TAS5508
B0047-01
TAS5132
SLES190 – DECEMBER 2006
SYSTEM BLOCK DIAGRAM
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Temp.
Sense
M1
M2
RESET_AB
SD
OTW
AGND
OC_ADJ
VREG VREG
VDD
M3
Power
On
Reset
Under-
voltage
Protection
GND
PWM_D OUT_D
GND_D
PVDD_D
BST_D
Gate
Drive
PWM
Rcv.
Overload
Protection Isense
GVDD_D
RESET_CD
4
Protection
and
I/OLogic
PWM_C OUT_C
GND_C
PVDD_C
BST_C
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_C
PWM_B OUT_B
GND_B
PVDD_B
BST_B
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_B
PWM_A OUT_A
GND_A
PVDD_A
BST_A
Timing Gate
Drive
Ctrl.
PWM
Rcv.
GVDD_A
Ctrl.
BTL/PBTL−Configuration
Pulldown Resistor
BTL/PBTL−Configuration
PulldownResistor
BTL/PBTL−Configuration
PulldownResistor
BTL/PBTL−Configuration
PulldownResistor
InternalPullup
ResistorstoVREG
B0034-02
4
Timing
TAS5132
SLES190 – DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
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RECOMMENDED OPERATING CONDITIONS
AUDIO SPECIFICATIONS (BTL)
TAS5132
SLES190 – DECEMBER 2006
MIN TYP MAX UNIT
PVDD_X Half-bridge supply DC supply voltage 0 18 19 V
Supply for logic regulators and gate-driveGVDD_X DC supply voltage 10.8 12 13.2 Vcircuitry
VDD Digital regulator input DC supply voltage 10.8 12 13.2 V
R
L
(BTL) 6-8Output filter: L = 10 µH, C = 470 nF.R
L
(SE) Load impedance Output AD modulation, switching 3-4 Ωfrequency > 350 kHzR
L
(PBTL) 3-4
L
Output
(BTL) 10Minimum output inductance underL
Output
(SE) Output-filter inductance 10 µHshort-circuit conditionL
Output
(PBTL) 10
F
PWM
PWM frame rate 192 384 432 kHz
T
J
Junction temperature 0 125 °C
PVDD_X = 18 V, GVDD = VDD = 12 V, BTL mode, R
L
= 8 Ω, R
OC
= 22 K Ω, C
BST
= 33-nF, audio frequency = 1 kHz, AES17filter, F
PWM
= 384 kHz, case temperature = 75 °C (unless otherwise noted). Audio performance is recorded as a chipset, usingTAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance withrecommended operating conditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
L
= 6 Ω, 10% THD, clipped input signal 26
R
L
= 8 Ω, 10% THD, clipped input signal 20P
O
Power output per channel, DDV package WR
L
= 6 Ω, 0 dBFS, unclipped input signal 20
R
L
= 8 Ω, 0 dBFS, unclipped input signal 16
0 dBFS <0.1%THD+N Total harmonic distortion + noise
1 W <0.06%
V
n
Output integrated noise A-weighted 50 200 µV
SNR Signal-to-noise ratio
(1)
A-weighted 94 105 dB
A-weighted, input level = –60 dBFS usingDNR Dynamic range 94 105 dBTAS5086 modulator
Power dissipation due to idle lossesP
idle
P
O
= 0 W, 4 channels switching
(2)
.6 W(IPVDD_X)
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
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AUDIO SPECIFICATIONS (Single-Ended Output)
AUDIO SPECIFICATIONS (PBTL)
TAS5132
SLES190 – DECEMBER 2006
PVDD_X = 18 V, GVDD = VDD = 12 V, SE mode, R
L
= 3 Ω, R
OC
= 22 K Ω, C
BST
= 33-nF, audio frequency = 1 kHz, AES17filter, F
PWM
= 384 kHz, case temperature = 75 °C (unless otherwise noted). Audio performance is recorded as a chipset, usingTAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance withrecommended operating conditions, unless otherwise specified.
PARAMETER TEST CONDITIONS TYP UNIT
R
L
= 3 Ω, 10% THD, clipped input signal 12.5
R
L
= 4 Ω, 10% THD, clipped input signal 10.0P
O
Power output per channel, DDV package WR
L
= 3 Ω, 0 dBFS, unclipped input signal 9.5
R
L
= 4 Ω, 0 dBFS, unclipped input signal 7.5
0 dBFS, 4 Ω.09THD+N Total harmonic distortion + noise %1 W, 4 Ω.05
V
n
Output integrated noise A-weighted 18 µV
SNR Signal-to-noise ratio
(1)
A-weighted 100 dB
A-weighted, input level = –60 dBFS usingDNR Dynamic range 100 dBTAS5086 modulator
P
idle
Power dissipation due to idle losses (IPVDD_X) P
O
= 0 W, 4 channels switching
(2)
.6 W
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
PVDD_X = 18 V, GVDD = VDD = 12 V, PBTL mode, R
L
= 3 Ω, R
OC
= 22 K Ω, C
BST
= 33-nF, audio frequency = 1 kHz, AES17filter, F
PWM
= 384 kHz, case temperature = 75 °C (unless otherwise noted). Audio performance is recorded as a chipset, usingTAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance withrecommended operating conditions, unless otherwise specified.
PARAMETER TEST CONDITIONS TYP UNIT
R
L
= 3 Ω, 10% THD, clipped input signal 50
R
L
= 4 Ω, 10% THD, clipped input signal 40P
O
Power output per channel, DDV package WR
L
= 3 Ω, 0 dBFS, unclipped input signal 37
R
L
= 4 Ω, 0 dBFS, unclipped input signal 30
0 dBFS, 3 Ω.14THD+N Total harmonic distortion + noise %1 W, 3 Ω.02
V
n
Output integrated noise A-weighted 30 µV
SNR Signal-to-noise ratio
(1)
A-weighted 105 dB
A-weighted, input level = –60 dBFS using TAS5086
105DNR Dynamic range dBmodulator
P
idle
Power dissipation due to idle losses (IPVDD_X) P
O
= 0 W, 1 channel switching
(2)
.6 W
(1) SNR is calculated relative to 0-dBFS input level.(2) Actual system idle losses are affected by core losses of output inductors.
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ELECTRICAL CHARACTERISTICS
TAS5132
SLES190 – DECEMBER 2006
R
L
= 8 Ω, F
PWM
= 384 kHz (unless otherwise noted). All performance is in accordance with recommended operatingconditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as aVREG VDD = 12 V 3 3.3 3.6 Vreference node
Operating, 50% duty cycle 6 9IVDD VDD supply current mAIdle, reset mode 5.5 8
50% duty cycle 3.6 5.5IGVDD_X Gate supply current per half-bridge mAReset mode 1.0 2.0
50% duty cycle, without output filter or load 9 15 mAIPVDD_X Half-bridge idle current
Reset mode, no switching .1 .2 mA
Output Stage MOSFETs
T
J
= 25 °C, includes metallization resistance,R
DSon,LS
Drain-to-source resistance, LS 140 155 m ΩGVDD = 12 V
T
J
= 25 °C, includes metallization resistance,R
DSon,HS
Drain-to-source resistance, HS 140 155 m ΩGVDD = 12 V
I/O Protection
Undervoltage protection limit,V
uvp,G
9.6 VGVDD_X, voltage rising
Undervoltage protection limit,V
uvp,G
9.2 VGVDD_X, voltage falling
Puts device into RESET when BSTBST
uvpF
6.2 Vvoltage falls below limit
Brings device out of RESET whenBST
uvpR
6.6 VBST voltage rises above limit
OTW
(1)
Overtemperature warning 125 °C
Temperature drop needed belowOTW
HYST
(1)
OTW temperature for OTW to be 25 °Cinactive after the OTW event
OTE
(1)
Overtemperature error 155 °C
OTE-
OTE-OTW differential 30 °COTW
differential
(1)
A reset event must occur for SD toOTE
HYST
(1)
be released following an OTE 30 °Cevent.
OLPC Overload protection counter F
PWM
= 384 kHz 1.25 ms
Resistor—programmable, max. current,I
OC
Overcurrent limit protection 4.0 5.0 6.0 AR
OCP
= 22 k Ω
I
OCT
Overcurrent response time 150 ns
R
OCP
OC programming resistor range Resistor tolerance = 5% for typical value; the k Ωminimum resistance should not be less than 20 2220k Ω.
Connected when RESET is active to provideInternal pulldown resistor at theR
PD
bootstrap capacitor charge. Not used in SE 3.0 k Ωoutput of each half-bridge
mode
PWM Activity Detector, causes
PWM stopped and time measured for devicePAD device reset when PWM input 10 25 µSto go into RESET (Output switching stopped)signal is stopped.
(1) Specified by design
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
PVDD − Supply Voltage − V
0
5
10
15
20
25
30
0 5 10 15 20
PO − Output Power − W
8 Ω
TC = 75°C
THD+N @ 10%
6 Ω
G002
TAS5132
SLES190 – DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
R
L
= 8 Ω, F
PWM
= 384 kHz (unless otherwise noted). All performance is in accordance with recommended operatingconditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Digital Specifications
V
IH
High-level input voltage 2 VPWM_A, PWM_B, PWM_C, PWM_D, M1,M2, M3, RESET_AB, RESET_CDV
IL
Low-level input voltage 0.8 V
Static, High PWM_A, PWM_B, PWM_C,PWM_D, M1, M2, M3, RESET_AB, 100RESET_CDI
lkg
Input leakage current µAStatic, Low PWM_A, PWM_B, PWM_C,PWM_D, M1, M2, M3, RESET_AB, –10 10RESET_CD
OTW/Shutdown (SD)
Internal pullup resistance, OTW toR
INT_PU
20 26 32 k ΩVREG, SD to VREG
Internal pullup resistor 3 3.3 3.6V
OH
High-level output voltage VExternal pullup of 4.7 k Ωto 5 V 5.5
V
OL
Low-level output voltage I
O
= 4 mA 0.25 0.5 V
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 1. Figure 2.
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PVDD − Supply Voltage − V
0
5
10
15
20
25
0 5 10 15 20
PO − Output Power − W
8 Ω
TC = 75°C
6 Ω
G003
PO − Output Power − W
60
65
70
75
80
85
90
95
100
0 10 20 30 40 50 60
Efficiency − %
6 Ω
TC = 25°C
G004
8 Ω
0
1
2
3
4
5
6
7
0 10 20 30 40 50 60
PO − Output Power − W
Power Loss − W
6 Ω
8 Ω
TC = 25°C
G005
TC − Case Temperature − °C
0
5
10
15
20
25
30
0 20 40 60 80 100 120
PO − Output Power − W
8 Ω
THD+N @ 10%
6 Ω
G006
TAS5132
SLES190 – DECEMBER 2006
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCYvs vsSUPPLY VOLTAGE OUTPUT POWER
Figure 3. Figure 4.
SYSTEM POWER LOSS SYSTEM OUTPUT POWERvs vsOUTPUT POWER CASE TEMPERATURE
Figure 5. Figure 6.
12
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TYPICAL CHARACTERISTICS, SE CONFIGURATION
PO − Output Power − W
10.01
THD+N − Total Harmonic Distortion + Noise − %
0.01
0.1
10
1
TC = 75°C
Digital Gain = 3 dB
3 Ω
4 Ω
G008
0.1 10
PVDD − Supply Voltage − V
0
3
6
9
12
15
0 5 10 15 20
PO − Output Power − W
4 Ω
TC = 75°C
THD+N @ 10%
3 Ω
G009
TAS5132
SLES190 – DECEMBER 2006
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
NOISE AMPLITUDE
vsFREQUENCY
Figure 7.
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 8. Figure 9.
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M TEXAS INSTRUMENTS www.|l.cnm 15 12 .\ 3 . 3 9 '\ a n. 5 §‘ 0 s . o n. 3 o \ \ o 20 40 an an Inn 12 Tc - Case Temperature » °C :**+7 30 \// m, // 1° / 0 5 10 15 20 .33“ PVDD — Supply Voltage - V Po — Oulpul Power .w
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TC − Case Temperature − °C
0
3
6
9
12
15
0 20 40 60 80 100 120
PO − Output Power − W
4 Ω
THD+N @ 10%
3 Ω
G010
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
PO − Output Power − W
100.1
THD+N − Total Harmonic Distortion + Noise − %
0.01
0.1
10
1
G011
TC = 75°C
Digital Gain = 3 dB
1
3 Ω
4 Ω
60
PVDD − Supply Voltage − V
0
10
20
30
40
50
60
0 5 10 15 20
PO − Output Power − W
4 Ω
TC = 75°C
THD+N @ 10%
3 Ω
G012
TAS5132
SLES190 – DECEMBER 2006
TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued)
OUTPUT POWER
vsCASE TEMPERATURE
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWERvs vsOUTPUT POWER SUPPLY VOLTAGE
Figure 11. Figure 12.
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0
10
20
30
40
50
60
0 20 40 60 80 100 120
TC − Case Temperature − °C
PO − Output Power − W
THD+N @ 10%
3 Ω
4 Ω
G013
TAS5132
SLES190 – DECEMBER 2006
TYPICAL CHARACTERISTICS, PBTL CONFIGURATION (continued)
SYSTEM OUTPUT POWER
vsCASE TEMPERATURE
Figure 13.
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PVDD
VALID
GVDD
10 Ω(A)
10 mF
GVDD
1 Ω
Shutdown
PWM1_P
PWM1_M
PWM2_P
PWM2_M
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
BST_D
GVDD_D
44
43
42
41
31
23
24
25
26
32
33
34
35
36
40
39
38
37
GND_D
GVDD_A
13
14
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
22kΩ
100nF
33nF
33nF
33nF
33nF
100nF
25V
100nF
25V
220 mF
25V
PVDD
470nF
63V
10 mH@6 A
10nF
25V
10nF
25V
3.3 Ω
3.3 Ω
100nF
25V
100nF
25V
3.3 Ω
10nF
25V
100nF
25V
47 Fm
25V
47 mF
25V
10 mF100nF
100nF(A)
100nF(A)
10 H@6 Am
TAS5132DDV
0 Ω
Optional
TAS5508
10 Ω(A)
47 mF
25V
470nF
63V
10 H@6 Am
10nF
25V
10nF
25V
3.3 Ω
3.3 Ω
100nF
25V
100nF
25V
10 H@6 Am
10nF
25V
220 Fm
25V
3.3 Ω
S0070-06
RESET_CD OUT_D
PVDD_D
27
28
29
30
NC
15
16
17
18
NC
NC
NC
NC NC
PVDD_A
PVDD_D
100nF
25V
47 Fm
25V
PVDD
TAS5132
SLES190 – DECEMBER 2006
A. Optional component, GVDD_A and GVDD_B can potentially share the same decoupling components. Also, GVDD_Cand GVDD_D can potentially share the same decoupling components.
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
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PVDD
10 mH@6 A
10 mH@6 A
100nF
25V
47 mF
25V
VALID
GVDD
10 Ω(A)
10 mF
GVDD
1 Ω
Shutdown
PWM1_P
PWM2
PWM_A
PWM_C
OTW
RESET_AB
M2
M3
VDD
GVDD_C
GVDD_B
PWM_D
VREG
M1
SD
AGND
PWM_B
OC_ADJ
GND
GND_C
OUT_A
BST_A
OUT_B
BST_B
PVDD_B
PVDD_A
BST_C
PVDD_C
OUT_C
GND_A
GND_B
BST_D
GVDD_D
44
43
42
41
31
23
24
25
26
32
33
34
35
36
40
39
38
37
GND_D
GVDD_A
13
14
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Microcontroller
22kΩ
100nF
33nF
33nF
33nF
33nF
100nF
25V
100nF
25V
220 Fm
25V
PVDD
470nF
63V
10 mH@6 A
10nF
25V
10nF
25V
3.3 Ω
3.3 Ω
100nF
25V
100nF
25V
3.3 Ω
10nF
25V
10nF
25V
220 mF
25V
3.3 Ω
47 mF
25V
10 mF100nF
100nF(A)
100nF(A)
10 mH@6 A
TAS5132DDV
0 Ω
Optional
TAS5508
10 Ω(A)
47 mF
25V
470nF
63V
10nF
25V
10nF
25V
3.3 Ω
3.3 Ω
100nF
25V
100nF
25V
RESET_CD OUT_D
PVDD_D
27
28
29
30
NC
15
16
17
18
NC
NC
NC
NC NC
PVDD_A
PVDD_D
100nF
25V
47 mF
25V
S0070-07
TAS5132
SLES190 – DECEMBER 2006
A. Optional component, GVDD_A and GVDD_B can potentially share the same decoupling components. Also, GVDD_Cand GVDD_D can potentially share the same decoupling components.
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
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THEORY OF OPERATION
POWER SUPPLIES
SYSTEM POWER-UP/POWER-DOWN
Powering Up
Powering Down
TAS5132
SLES190 – DECEMBER 2006
ceramic capacitor placed as close as possible toeach supply pin. It is recommended to follow thePCB layout of the TAS5132 reference design. ForTo facilitate system design, the TAS5132 needs only
additional information on recommended powera 12-V supply in addition to the (typical) 18-V
supply and required components, see the applicationpower-stage supply. An internal voltage regulator
diagrams given previously in this data sheet.provides suitable voltage levels for the digital and
The 12-V supply should be from a low-noise,low-voltage analog circuitry. Additionally, all circuitry
low-output-impedance voltage regulator. Likewise,requiring a floating voltage supply, e.g., the high-side
the 18-V power-stage supply is assumed to have lowgate drive, is accommodated by built-in bootstrap
output impedance and low noise. The power-supplycircuitry requiring only a few external capacitors.
sequence is not critical as facilitated by the internalIn order to provide outstanding electrical and
power-on-reset circuit. Moreover, the TAS5132 isacoustical characteristics, the PWM signal path
fully protected against erroneous power-stage turnonincluding gate drive and output stage is designed as
due to parasitic gate charging.identical, independent half-bridges. For this reason,each half-bridge has separate gate drive supply(GVDD_X), bootstrap pins (BST_X), and
SEQUENCEpower-stage supply pins (PVDD_X). Furthermore, anadditional pin (VDD) is provided as supply for allcommon circuits. These RC filters provide therecommended high-frequency isolation. Special The TAS5132 does not require a power-upattention should be paid to placing all decoupling sequence. The outputs of the H-bridges remain in acapacitors as close to their associated pins as low-impedance state until the gate-drive supplypossible. In general, inductance between the power voltage (GVDD_X) and VDD voltage are above thesupply pins and decoupling capacitors must be undervoltage protection (UVP) voltage threshold (seeavoided. (See reference board documentation for the Electrical Characteristics section of this dataadditional information.) sheet). Although not specifically required, it isrecommended to hold RESET_AB and RESET_CDFor a properly functioning bootstrap circuit, a small
in a low state while powering up the device. Thisceramic capacitor must be connected from each
allows an internal circuit to charge the externalbootstrap pin (BST_X) to the power-stage output pin
bootstrap capacitors by enabling a weak pulldown of(OUT_X). When the power-stage output is low, the
the half-bridge output. The output impedance isbootstrap capacitor is charged through an internal
approximately 3K Ωunder this condition, unlessdiode connected between the gate-drive power--
mode 1, 0, 0 (Single-ended Mode), is used. Thissupply pin (GVDD_X) and the bootstrap pin. When
means that the TAS5132 should be held in reset forthe power-stage output is high, the bootstrap
at least 200 µS to ensure that the bootstrapcapacitor potential is shifted above the output
capacitors are charged. This also assumes that thepotential and thus provides a suitable voltage supply
recommended 0.033- µF bootstrap capacitors arefor the high-side gate driver. In an application with
used. Changes to bootstrap capacitor values willPWM switching frequencies in the range from 352
change the bootstrap capacitor charge time.kHz to 384 kHz, it is recommended to use 33-nFceramic capacitors, size 0603 or 0805, for the When the TAS5132 is being used with TI PWMbootstrap supply. These 33-nF capacitors ensure modulators such as the TAS5086, no specialsufficient energy storage, even during minimal PWM attention to the state of RESET_AB and RESET_CDduty cycles, to keep the high-side power stage FET is required, provided that the chipset is configured as(LDMOS) fully turned on during the remaining part of recommended.the PWM cycle. In an application running at areduced switching frequency, generally 192 kHz, thebootstrap capacitor might need to be increased in
The TAS5132 does not require a power-downvalue.
sequence. The device remains fully operational asSpecial attention should be paid to the power-stage long as the gate-drive supply voltage and VDDpower supply; this includes component selection, voltage are above the undervoltage protection (UVP)PCB placement, and routing. As indicated, each voltage threshold (see the Electrical Characteristicshalf-bridge has independent power-stage supply pins section of this data sheet). Although not specifically(PVDD_X). For optimal electrical performance, EMI required, it is a good practice to hold RESET_ABcompliance, and system reliability, it is important that and RESET_CD low during power down, thuseach PVDD_X pin is decoupled with a 100-nF preventing audible artifacts, including pops or clicks.
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ERROR REPORTING
Use of TAS5132 in High-Modulation-Index
Overcurrent (OC) Protection With Current
DEVICE PROTECTION SYSTEM
TAS5132
SLES190 – DECEMBER 2006
When the TAS5132 is being used with TI PWM PWM inputs that will detect the condition when amodulators such as the TAS5086, no special PWM input is continuously high or low. This functionattention to the state of RESET_AB and RESET_CD is named PWM Activity Detector (PAD). Without thisis required, provided that the chipset is configured as protection circuitry, if a PWM input is continuouslyrecommended. high or low, the PVDD power supply voltage couldappear on the associated output pin. This conditioncould damage either the output load (loudspeaker) orthe device. If a PWM input remains either high or lowThe SD and OTW pins are both active-low,
for over 10 µS, the device's outputs will be set into aopen-drain outputs. Their function is for
Hi-Z state. If this error condition occurs, SD will notprotection-mode signaling to a PWM controller or
be asserted low.other system-control device.
Any fault resulting in device shutdown is signaled by
Capable Systemsthe SD pin going low. Likewise, OTW goes low whenthe device junction temperature exceeds 125 °C (see
This device requires at least 50 ns of low time on thethe following table).
output per 384-kHz PWM frame rate in order to keepthe bootstrap capacitors charged. As an example, ifSD OTW DESCRIPTION
the modulation index is set to 99.2% in the TAS5086,0 0 Overtemperature (OTE) or overload (OLP) or
this setting allows PWM pulse durations down to 20undervoltage (UVP)
ns. This signal, which does not meet the 50-ns0 1 Overload (OLP) or undervoltage (UVP)
requirement, is sent to the PWM_X pin, and this1 0 Junction temperature higher than 125 °C
low-state pulse time does not allow the bootstrap(overtemperature warning)
capacitor to stay charged. In this situation, the low1 1 Junction temperature lower than 125 °C and no
voltage across the bootstrap capacitor can cause theOLP or UVP faults (normal operation)
bootstrap UVP circuitry to avtivate and shutdown thedevice. The TAS5132 device requires limiting theNote that asserting either RESET_AB or RESET_CD
TAS5086 modulation index to 96.1% to keep thelow forces the SD signal high, independent of faults
bootstrap capacitor charged under all signals andbeing present. TI recommends monitoring the OTW
loads.signal using the system microcontroller andresponding to an overtemperature warning signal by,
Therefore, TI strongly recommends using a TI PWMe.g., turning down the volume to prevent further
processor, such as TAS5508 or TAS5086, with theheating of the device, resulting in device shutdown
modulation index set at 96.1% to interface with(OTE).
TAS5132. This is done by writing 0x04 to theModulation Limit Register (0x10) in the TAS5086 orTo reduce external component count, an internal
0x04 to the Modulation Limit Register (0x16) in thepullup resistor to 3.3 V is provided on both SD and
TAS5508.OTW outputs. Level compliance for 5-V logic can beobtained by adding external pullup resistors to 5 V(see the Electrical Characteristics section of this data
Limiting and Overload Detectionsheet for further specifications).
The device has independent, fast-reacting currentdetectors with on all high-side and low-sidepower-stage FETs. See the following table forThe TAS5132 contains advanced protection circuitry
OC-adjust resistor values. The detector outputs arecarefully designed to facilitate system integration and
closely monitored by two protection systems. Theease of use, as well as to safeguard the device from
first protection system controls the power stage inpermanent failure due to a wide range of fault
order to prevent the output current from furtherconditions such as short circuits, overload,
increasing, i.e., it performs a current-limiting function,overtemperature, and undervoltage. The TAS5132
rather than prematurely shutting down duringresponds to a fault by immediately setting the power
combinations of high-level music transients andstage in a high-impedance (Hi-Z) state and asserting
extreme speaker load impedance drops. If thethe SD pin low. In situations other than overload and
high-current situation persists, i.e., the power stageovertemperature, the device automatically recovers
is being overloaded, a second protection systemwhen the fault condition has been removed. For
triggers a latching shutdown, resulting in the powerhighest possible reliability, recovering from an
stage being set in the high-impedance (Hi-Z) state.overload fault requires external reset of the device(see the Device Reset section of this data sheet) nosooner than 1 second after the shutdown.
The TAS5132 contains circuitry associated with its
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DEVICE RESET
Overtemperature Protection
Undervoltage Protection (UVP) and Power-On
TAS5132
SLES190 – DECEMBER 2006
Current limiting and overload protection are that all circuits are fully operational when theindependent for half-bridges A and B and, GVDD_X and VDD supply voltages reach 9.6 Vrespectively, C and D. That is, if the bridge-tied load (typical). Although GVDD_X and VDD arebetween half-bridges A and B causes an overload independently monitored, a supply voltage dropfault, only half-bridges A and B are shut down. below the UVP threshold on any VDD or GVDD_Xpin results in all half-bridge outputs immediatelyOC-Adjust Resistor Values Max. Current Before OC
being set in the high-impedance (Hi-Z) state and SD(k Ω) Occurs (A)
being asserted low. The device automatically22 5.2
resumes operation when all supply voltages have27 4.6
increased above the UVP threshold.30 4.2
33 3.8
42 3.2
Two reset pins are provided for independent control47 2.9
of half-bridges A/B and C/D. When RESET_AB is56 2.5 asserted low, all four power-stage FETs in half--bridges A and B are forced into a high-impedance69.8 2.0
(Hi-Z) state. Likewise, asserting RESET_CD lowforces all four power-stage FETs in half-bridges Cand D into a high-impedance state. Thus, both resetpins are well suited for hard-muting the power stageThe TAS5132 has a two-level temperature-protection
if needed.system that asserts an active-low warning signal( OTW) when the device junction temperature
In BTL modes, to accommodate bootstrap chargingexceeds 125 °C (nominal) and, if the device junction
prior to switching start, asserting the reset inputs lowtemperature exceeds 155 °C (nominal), the device is
enables weak pulldown of the half-bridge outputs. Input into thermal shutdown, resulting in all half-bridge
the SE mode, the weak pulldowns are not enabled,outputs being set in the high-impedance (Hi-Z) state
and it is therefore recommended to ensure bootstrapand SD being asserted low. OTE is latched in this
capacitor charging by providing a low pulse on thecase. To clear the OTE latch, both RESET_AB and
PWM inputs when reset is asserted high.RESET_CD must be asserted. Thereafter, the deviceresumes normal operation.
Asserting either reset input low removes any faultinformation to be signalled on the SD output, i.e., SDis forced high.Reset (POR)
A rising-edge transition on either reset input allowsThe UVP and POR circuits of the TAS5132 fully
the device to resume operation after an overloadprotect the device in any power-up/down and
fault.brownout situation. While powering up, the PORcircuit resets the overload circuit (OLP) and ensures
20
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TAS5132DDV ACTIVE HTSSOP DDV 44 35 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TAS5132
TAS5132DDVG4 ACTIVE HTSSOP DDV 44 35 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TAS5132
TAS5132DDVR ACTIVE HTSSOP DDV 44 2000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 TAS5132
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5132DDVR HTSSOP DDV 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5132DDVR HTSSOP DDV 44 2000 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TAS5132DDV DDV HTSSOP 44 35 530 11.89 3600 4.9
TAS5132DDVG4 DDV HTSSOP 44 35 530 11.89 3600 4.9
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 3
GENERIC PACKAGE VIEW DDV 44 PowerPADT"| TSSOP - 1.2 mm max heigm PLASTIC SMALL OUTLINE Images above are jusl a represenlalion of the package family, aclual package may vary Refel lo the product dala sheel for package details. 4206011/H I TEXAS INSTRI IMFNTS
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