MAX3942 规格书

[VI/JXI/VI a 7 fig H MM :3 MM : HE; :E H £1 £3“ LQTrC [VI/JXI/VI
Typical Application Circuit
General Description
The MAX3942 is designed to drive high-speed optical
modulators at data rates up to 10.7Gbps. It functions as
a modulation circuit, with an integrated control op amp
externally programmed by a DC voltage.
A high-bandwidth, fully differential signal path is inter-
nally implemented to minimize jitter accumulation. When
a clock signal is available, the integrated data-retiming
function can be selected to reject input-signal jitter.
The MAX3942 receives differential CML signals (ground-
referenced) with on-chip line terminations of 50Ω. Each
of the differential outputs has an on-chip 50Ωresistor for
back termination. The driver is able to deliver a modula-
tion current of 40mAP-P to 120mAP-P, with an edge
speed of 23ps (typical 20% to 80%). This modulation
current reflects a modulation voltage of 1.0VP-P to 3.0VP-
Psingle ended or 2.0VP-P to 6.0VP-P differential.
The MAX3942 also includes an adjustable pulse-width
control circuit to precompensate for asymmetrical mod-
ulator characteristics. It is available in a compact 4mm
✕4mm, 24-pin thin QFN package and operates over
the -40°C to +85°C temperature range.
Features
♦23ps Edge Speed
♦Single-Ended Modulation Voltage Up to 3VP-P
♦Differential Modulation Voltage Up to 6VP-P
♦Selectable Data-Retiming Latch
♦Up to 10.7Gbps Operation
♦50ΩOn-Chip Input and Output Terminations
♦Pulse-Width Adjustment
♦Enable and Polarity Controls
♦ESD Protection
Applications
Mach Zehnder Modulators
Packaged Direct-Modulated Lasers
SONET OC-192 and SDH STM-64 Transmission
Systems
DWDM Systems
Long/Short-Reach Optical Transmitters
10Gbps Ethernet
MAX3942
10Gbps Modulator Driver
________________________________________________________________
Maxim Integrated Products
1
MAX3952
0.01μF
DATA+ DATA+
PLRT GND
50Ω
0.01μF
DATA- DATA-
50Ω
0.01μF
CLK+ CLK+
OUT+
50Ω
0.01μF
CLK- CLK-
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
-5.2V
50Ω
10Gbps
SERIALIZER
2kΩ
PWC+ PWC- VEE
MODSET
+
VMODSET
-
1000pF
-5.2V
-5.2V 0.1μF
-5.2V
MODEN RTEN
50Ω
OUT- 50Ω
MAX3942
L2
L1
50Ω
50Ω
0.01μF
0.01μF
MACH ZEHNDER
MODULATOR
L1 AND L2 ARE HIGH-FREQUENCY FERRITE BEADS
19-2934; Rev 1; 6/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX3942ETG -40°C to +85°C 24 Thin QFN (4mm 4mm)
MAX3942ETG+ -40°C to +85°C 24 Thin QFN (4mm 4mm)
Pin Configuration appears at end of data sheet.
+
Denotes a lead-free package.
[VI/J XI [VI
MAX3942
10Gbps Modulator Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage VEE ..............................................-6.0V to +0.5V
Voltage at MODEN,
RTEN, PLRT, MODSET............................(VEE - 0.5V) to +0.5V
Voltage at DATA+, DATA-, CLK+, and CLK-……-1.65V to +0.5V
Voltage at OUT+, OUT- ................................……….-4V to +0.5V
Voltage at PWC+, PWC- ...................(VEE - 0.5V) to (VEE + 1.7V)
Continuous Power Dissipation (TA= +85°C)
24-Pin Thin QFN (derate 20.8mW/° above +85°C) ....1354mW
Current into or out of OUT+, OUT-.................……………...80mA
Storage Temperature Range .....................……-55°C to +150°C
Operating Temperature Range ....................……-40°C to +85°C
Lead Temperature (soldering, 10s)............………………+300°C
ELECTRICAL CHARACTERISTICS
(VEE = -5.5V to -4.9V, TA= -40°C to +85°C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Voltage VEE -5.5 -4.9 V
Retime disabled 125 175
Supply Current IEE Excluding IMOD
(Note 1) Retime enabled 140 200 mA
Power-Supply Noise Rejection PSNR f 2MHz (Note 2); see Figure 3 15 dB
SIGNAL INPUT (Note 3)
Input Data Rates NRZ 10.7 Gbps
Single-Ended Input Resistance RIN Input to GND 42.5 50 58.5
DC-coupled, Figure 1a -1 0
Single-Ended Input Voltage VIS AC-coupled, Figure 1b -0.4 +0.4 V
DC-coupled (Note 4) 0.2 2.0
Differential Input Voltage VID AC-coupled (Note 4) 0.2 1.6 VP-P
Differential Input Return Loss RLIN 15GHz 15 dB
MODULATION (Note 5)
Maximum Modulation Current 112 120 mAP-P
Minimum Modulation Current VMODSET = VEE 37 41 mAP-P
MODSET Voltage Range VMODSET V
EE VEE + V
Equivalent Modulation RMODEQV (Note 7) 11.1
Modulation Set Bandwidth Modulation depth 10%, 50 driver load 5 MHz
MODSET Input Resistance 20 k
Modulation-Current
Temperature Stability (Note 6) -980 0 ppm/°C
Modulation-Current-Setting Error 50 driver load, TA = +25°C -10 +10 %
Output Resistance ROUT OUT+ and OUT- to GND 42.5 50 58.5
[VIIJXI [VI
MAX3942
10Gbps Modulator Driver
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.5V to -4.9V, TA= -40°C to +85°C. Typical values are at VEE = -5.2V, IMOD = 100mA, and TA= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Off Current MODEN = VEE, MODSET = VEE, DATA+ =
high, DATA- = low 1.6 mA
Differential Output Return Loss RLOUT IMOD = 50mA 10GHz 10 dB
Output Edge Speed 20% to 80% (Notes 6, 8) 23 32 ps
Setup/Hold Time tSU, tHD Figure 2 (Note 6) 25 ps
Pulse-Width Adjustment Range (Notes 6, 8) ±30 ±50 ps
Pulse-Width Control Input
Range (Single Ended) For PWC+ and PWC- VEE +
0.5
VEE +
1.5 V
Pulse-Width Control Input
Range (Differential) (PWC+) - (PWC-) -0.5 +0.5 V
Output Overshoot (Notes 6, 8) 5 %
Driver Random Jitter RJDR (Note 6) 0.3 0.8 psRMS
Driver Deterministic Jitter DJDR PWC- = GND (Notes 6, 9) 8 13 psP-P
CONTROL INPUTS
Input High Voltage VIH (Note 10) VEE +
2.0 V
Input Low Voltage VIL (Note 10) VEE +
0.8 V
Input Current (Note 10) -80 +200 μA
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply
current after the retiming function has been disabled.
Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) / ΔVOUT). VOUT is the voltage across a 50Ωload.
Vnoise (on Vcc) = 100mVP-P.
Note 3: For DATA+, DATA-, CLK+, and CLK-.
Note 4: CLK input characterized at 10.7Gbps.
Note 5: Minimum voltage on OUT+ and OUT- is VEE + 1.9V.
Note 6: Guaranteed by design and characterization using the circuit shown in Figure 3.
Note 7: RMODEQV = (VMODSET - VEE) / (IMOD - 37mA).
Note 8: 50Ωload, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).
Measured with a 10.7Gbps 27- 1 PRBS pattern with 80 zeros and 80 ones inserted in the data pattern.
Note 10: For MODEN and PLRT.
fi JUUUL‘ r—‘r—Ir—Ir—r' gl—l|_l|_ll, [VIIJXIIM
MAX3942
10Gbps Modulator Driver
4 _______________________________________________________________________________________
Figure 1. Definition of Single-Ended Input Voltage Range
100mV
100mV
800mV
1.0V
0V
-0.5V
-1.0V
0.4V
0V
-0.4V
(a) DC-COUPLED SINGLE-ENDED CML INPUT
(b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT
Figure 2. Setup and Hold Timing Definition
CLK+
CLK-
DATA-
DATA+
(DATA+) - (DATA-)
tSU tHD
IOUT-
IOUT+
VIS = 0.1VP-P TO 1VP-P
DC-COUPLED
0.1VP-P TO 0.8VP-P
AC-COUPLED
VID = 0.2VP-P TO 2VP-P
DC-COUPLED
0.2VP-P TO 1.6VP-P
AC-COUPLED
IMOD = 40mAP-P TO 120mAP-P
NOTE: IOUT+ AND IOUT- RELATE TO RETIMED DATA. SEE FIGURE 3 FOR POLARITY.
Test Circuits and Timing Diagrams
[VI/JXI [VI
MAX3942
10Gbps Modulator Driver
_______________________________________________________________________________________ 5
Figure 3. AC Characterization Circuit
CLK+
PLRT PWC+ PWC-
50Ω
CLK-
50Ω
DATA+
OUT-
IOUT-
IOUT+
OUT+
50Ω
DATA-
-5.2V
50Ω
PATTERN
GENERATOR
VEE
VMODSET
VEE
GNDMODSET
1000pF
0.1μF
MODEN
RTEN
50Ω
OSCILLOSCOPE
MAX3942
ZL
50Ω
50Ω
Test Circuits and Timing Diagrams (continued)
‘Hms‘um us) [MAXI/VI
MAX3942
10Gbps Modulator Driver
6 _______________________________________________________________________________________
DIFFERENTIAL VMOD vs. VMODSET
(ZL = 50Ω ON OUT+ AND OUT-)
MAX3942 toc06
VMODSET (V)
DIFFERENTIAL VMOD (VP-P)
0.750.500.25
1
2
3
4
5
6
7
0
0 1.00
VMODSET IS RELATIVE TO VEE
MAX3942 toc08
FREQUENCY (GHz)
IS11I (dB)
1293 6
-35
-30
-25
-20
-15
-10
-5
0
-40
015
DIFFERENTIAL S11 vs. FREQUENCY
(DEVICE POWERED)
Typical Operating Characteristics
(Typical values are at VEE = -5.2V, IMOD = 100mA, TA= +25°C, unless otherwise noted.)
10.7Gbps ELECTRICAL EYE DIAGRAM
(VMOD = 2VP-P DIFFERENTIAL, 231 - 1 PRBS)
MAX3942 toc01
16ps/div
10.7Gbps ELECTRICAL EYE DIAGRAM
(VMOD = 6VP-P DIFFERENTIAL, 231 - 1 PRBS)
MAX3942 toc02
16ps/div
SUPPLY CURRENT vs. TEMPERATURE
(50Ω LOAD, EXCLUDES IMOD)
MAX3942 toc03
TEMPERATURE (°C)
IEE (mA)
80706050403020100-10-20-30
110
120
130
140
150
160
170
100
-40 90
RETIMING ENABLED
RETIMING DISABLED
0
0.6
0.4
0.2
1.0
0.8
1.8
1.6
1.4
1.2
2.0
-50 -30 -10 10 30 50 70 90
PULSE-WIDTH DISTORTION
vs. TEMPERATURE
MAX3942 toc05
TEMPERATURE (°C)
PULSE-WIDTH DISTORTION (ps)
DIFFERENTIAL S22 vs. FREQUENCY
(DEVICE POWERED)
MAX3942 toc09
FREQUENCY (GHz)
|S22| (dB)
12963
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
-30
015
0
110 10k
POWER-SUPPLY NOISE REJECTION
vs. FREQUENCY
10
5
15
25
20
30
MAX3942 toc07
FREQUENCY (Hz)
PSNR (dB)
100 1k
PULSE WIDTH vs. RPWC
MAX3942 toc04
RPWC- (Ω)
PULSE-WIDTH POSITIVE PULSE (ps)
2505001000 7501500 12501750
760
770
780
790
800
810
820
830
840
850
750
2000 0
RPWC+ (Ω)
175015001000 1250500 7502500 2000
MEASURED AT 1.25Gbps
WITH A 1010 PATTERN
[VIIJXI [VI
MAX3942
10Gbps Modulator Driver
_______________________________________________________________________________________ 7
Detailed Description
The MAX3942 modulator driver accepts differential
clock and data inputs that are compatible with PECL
and CML logic levels.
The modulation output stage is composed of a high-
speed differential pair and a programmable current
source with a maximum modulation current of 120mA.
The rise and fall times are typically 23ps. The modulation
current is designed to produce a modulation voltage up
to 3.0VP-P single endedly, or 6.0VP-P differentially when
driving a 50Ωmodule. The 3.0VP-P results from 120mAP-P
through the parallel combination of the 50Ωmodulator
load and the internal 50Ωback termination.
Polarity Switch
The MAX3942 includes a polarity switch. When the
PLRT pin is high or left floating, the outputs maintain the
polarity of the input data. When the PLRT pin is low, the
outputs are inverted relative to the input data.
Clock/Data Input Logic Levels
The MAX3942 is directly compatible with ground-refer-
ence CML. Either DC- or AC-coupling may be used for
CML referenced to ground. For all other logic types,
AC-coupling should be used.
Optional Data Input Latch
To reject pattern-dependent jitter in the input data, a syn-
chronous differential clock signal should be connected to
the CLK+ and CLK- inputs, and the RTEN control input
should be connected to VEE.
PIN NAME FUNCTION
1 DATA+ Noninverting Data Input, with 50Ω On-Chip Termination
2 DATA- Inverting Data Input, with 50Ω On-Chip Termination
3, 4, 14, 17 GND Ground. All pins must be connected to board ground.
5 CLK+ Noninverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
6 CLK- Inverting Clock Input for Data Retiming, with 50Ω On-Chip Termination
7, 11, 12, 13,
18, 19, 21, 24 VEE Negative Supply Voltage. All pins must be connected to board VEE.
8 PWC+ Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section).
9 PWC- Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width
adjustment feature (see the Design Procedure section).
10 MODSET Modulation Current Set. Apply a voltage to set the modulation current of the driver output.
15 OUT- Inverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current when
PLRT is high and when differential data is high.
16 OUT+ Noninverting Driver Output. Provides modulation output with 50Ω back termination. Sinks current
when PLRT is high and when differential data is low.
20 PLRT Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the
differential signal polarity. Contains an internal 100kΩ pullup to GND.
22 MODEN TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM
in the absorption (logic 0) state. Contains an internal 100kΩ pulldown to VEE.
23 RTEN Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch.
EP Exposed
Pad
Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance.
See the Layout Considerations section.
Pin Description
[VI/JXIIVI
MAX3942
10Gbps Modulator Driver
8 _______________________________________________________________________________________
The input data is retimed on the rising edge of CLK+. If
RTEN is connected to ground, the retiming function is dis-
abled and the input data is directly connected to the out-
put stage. Leave CLK+ and CLK- open when retiming is
disabled.
Pulse-Width Control
The pulse-width control circuit can be used to compen-
sate for pulse-width distortion introduced by the modu-
lator. The differential voltage between PWC+ and PWC-
adjusts the pulse-width compensation. The adjustment
range is typically ±50ps. Optional single-ended opera-
tion is possible by forcing a voltage on the PWC+ pin
while leaving the PWC- pin unconnected. When PWC-
is connected to ground, the pulse-width control circuit
is automatically disabled.
Modulation Output Enable
The MAX3942 incorporates a modulation current-
enable input. When MODEN is low or floating, the mod-
ulation outputs OUT+ and OUT- are enabled. When
MODEN is high, the drive current is switched to OUT+.
The typical enable time is 2ns and the typical disable
time is 2ns.
Design Procedure
Programming the Modulation Voltage
The modulation voltage results from IMOD passing
through the load impedance (ZL) in parallel with the
internal 50Ωtermination resistor (ROUT):
To program the desired modulation current, force a
voltage at the MODSET pin (see the
Typical Application
Circuit
). The resulting IMOD current can be calculated
by the following equation:
An internal, independent current source drives a constant
37mA to the modulation circuitry and any voltage above
VEE on the MODSET pin adds to this. The input imped-
ance of the MODSET pin is typically 20kΩ. Note that the
minimum output voltage is VEE + 1.9V.
Programming the Pulse-Width Control
Three methods of control are possible when pulse predis-
tortion is desired to minimize distortion at the receiver.
The pulse width may be set with a 2kΩpotentiometer with
the center tapped to VEE (or equivalent fixed resistors), or
by applying a voltage to the PWC+ pin, or by applying a
differential voltage across the PWC+ and PWC- pins. See
Table 1 for the desired effect of the pulse-width setting.
Pulse width is defined as (positive pulse width)/((positive
pulse width + negative pulse width)/2).
Input Termination Requirement
The MAX3942 data and clock inputs are CML compati-
ble. However, it is not necessary to drive the IC with a
standard CML signal. As long as the specified input volt-
age swings are met, the MAX3942 operates properly.
Applications Information
Layout Considerations
To minimize loss and crosstalk, keep the connections
between the MAX3942 output and the modulator as
short as possible. Use good high-frequency layout
techniques and multilayer boards with an uninterrupted
ground plane to minimize EMI and crosstalk. Circuit
boards should be made using low-loss dielectrics. Use
controlled-impedance lines for the clock and data
inputs, as well as for the data output.
IV
11.1
MOD MODSET
≈+
Ω37mA
VI ZR
ZR
MOD MOD L OUT
L OUT
≈×
×
+
Table 1. Pulse-Width Control
PULSE
WIDTH
(%)
RPWC+, RPWC- FOR
RPWC+ + RPWC- = 2kΩ
VPWC+
(
PWC- OPEN
)
(V)
VPWC+ -
VPWC-
(V)
100 RPWC+ = RPWC- VEE + 1 0
>100 RPWC+ > RPWC- > VEE + 1 >0
<100 RPWC+ < RPWC- < VEE + 1 <0
MAXIM yrr chi PWDr 2m vms VEE Figure 4 Functional Diagram Interface Schematics Figures 5 and 6 show simplified input and output cir- cuits of the MAX3942 modulator driver. To minimize inductancei keep the connections irom OUT, GNDi and VEE as short as possible, This is crucial for optimal periormance Laser Safety and IEC 825 Using the MAX3942 EAM driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered, Each customer must determine the level of fault tolerance required by their application, recogniz- ing that Maxim products are not designed or authorized for use as components in systems intended for surgical implant into the body for applications intended to sup- port or sustain life or tor any other application where the failure oi a Maxim product could create a situation where personal iniury or death may occur, [VI/JXI [VI END uAiAuatKi ll/l/lXI/VI DAlAq’CLVr i ; afii ‘ l Figure 5 Slmpl
MAX3942
10Gbps Modulator Driver
_______________________________________________________________________________________ 9
Interface Schematics
Figures 5 and 6 show simplified input and output cir-
cuits of the MAX3942 modulator driver.
To minimize inductance, keep the connections from
OUT, GND, and VEE as short as possible. This is crucial
for optimal performance.
Laser Safety and IEC 825
Using the MAX3942 EAM driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections must
be considered. Each customer must determine the level
of fault tolerance required by their application, recogniz-
ing that Maxim products are not designed or authorized
for use as components in systems intended for surgical
implant into the body, for applications intended to sup-
port or sustain life, or for any other application where the
failure of a Maxim product could create a situation where
personal injury or death may occur.
Figure 5. Simplified Input Circuit
MAX3942
DATA+/CLK+
50Ω50Ω
GND
VEE
DATA-/CLK-
Figure 4. Functional Diagram
50Ω50Ω
50Ω50Ω
50Ω50Ω
CLK+
CLK-
DATA-
DATA+
0
1
MUX
DQ
PWC
POLARITY
IMOD
VEE
VEE
VMODSET
MODENRTEN PLRT
OUT-
OUT+
-
+
PWC+ PWC-
VEE
50Ω50Ω
2kΩ
VEE
MAX3942
MODSET
[MAXI/III www.ma com/packages MAXIM
MAX3942
10Gbps Modulator Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Revision History
Pages changed at Rev 1: 1, 2, 10.
Exposed-Pad Package
The exposed pad on the 24-pin QFN provides a very
low thermal resistance path for heat removal from the
IC. The pad is also electrical ground on the MAX3942
and must be soldered to the circuit board ground for
proper thermal and electrical performance. Refer to
Maxim Application Note
HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages
for additional information.
Figure 6. Simplified Output Circuit
MAX3942
50Ω50Ω
OUT+
GND
VEE
OUT-
GND
VEE
GND GND
Chip Information
TRANSISTOR COUNT: 1918
PROCESS: SiGe Bipolar
24
23
22
21
20
19
7
8
9
10
11
12
13
14
15
16
17
18
6
5
4
3
2
1
MAX3942
24 THIN QFN (4mm x 4mm)
TOP VIEW
DATA+
DATA-
GND
GND
CLK+
CLK-
EXPOSED PAD CONNECTED TO GROUND
VEE
RTEN
MODEN
VEE
PLRT
VEE
VEE
GND
OUT+
OUT-
GND
VEE
VEE
VEE
MODSET
PWC-
PWC+
VEE.
Pin Configuration
PART PACKAGE TYPE PACKAGE CODE
MAX3942ETG 24 Thin QFN
(4mm ✕ 4mm ✕ 0.8mm) T2444-1