Texas Instruments 的 SN74S1051 规格书

] ] ] Dos[ 4 13 ] This Schonky barrier diode busrtermination array 004': 5 ‘2 J is designed to reduce reflection noise on memory 005[ 5 ii ] bus lines. This device consists of a 12bit DOBI: 7 ‘0 ] highrspeed Schottky diode array suitable for GNDI: a 9 ] ciamping to VCC and/or GND. ORDERING INFORMATION TA PACKAGE‘ £335.33; 133'; PDIP 7 N Tube SN74s1051 N SN7ASiO Tube SN74s1051 D SOIC 7 D 51051 one to 70°C Tape and reei SN74s1051 DR SOP 7 Ns Tape and reei SN74s1051NSR 7451051 TSSOP 7 PW Tape and reei SN74s1051PWR $1051 1 Package drawings, avariapie ai www.ii com/sc/package schematic diagrams standard packing quantities, mermai data, symboiizaiion and PCB design an D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 Dll D12 Vc 2 3 4 5 6 7 10 11 12 13 14 15 1 8 SN Piease be aware ihai an rmperiani notice concerning avaliabllily‘ siandard warranty, and use Texas insirumenis semiconductor products and disciaimers mereio appears a: the end p1 (his data s PRODMCHON nan . In Products mninrm m .pe mud-rd win-my Pmmn: Lenin-g a! nil mm”. i n r: current a m nunlmmn me n. pal we rem one“; inxlmmenrs processing does nainenesuriiy include *5 TEXAS INSTRUMENTS POST omca eox $55303 - DALLAS rExAs 752s5 cepyngm zoos,
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Designed to Reduce Reflection Noise
Repetitive Peak Forward Current to 200 mA
12-Bit Array Structure Suited for
Bus-Oriented Systems
description/ordering information
This Schottky barrier diode bus-termination array
is designed to reduce reflection noise on memory
bus lines. This device consists of a 12-bit
high-speed Schottky diode array suitable for
clamping to VCC and/or GND.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N Tube SN74S1051N SN74S1051N
SOIC D
Tube SN74S1051D
S1051
0°C to 70°C
SOIC
–
D
Tape and reel SN74S1051DR
S1051
SOP – NS Tape and reel SN74S1051NSR 74S1051
TSSOP – PW Tape and reel SN74S1051PWR S1051
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
schematic diagrams
D01
2D02
3D03
4D04
5D05
6D06
7D07
10 D08
11 D09
12 D10
13 D11
14 D12
15
8
GND 9
GND
VCC
1VCC
16
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
D01
D02
D03
D04
D05
D06
GND
VCC
D12
D11
D10
D09
D08
D07
GND
Slam: mrward vnnage Slam: reverse current rarer eapacmanee mtemal cresstatk current mA *9 TEXAS INSTRUMENTS
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Steady-state reverse voltage, VR 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous forward current, IF: Any D terminal from GND or to VCC 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Total through all GND or VCC terminals 170 mA. . . . . . . . . . . . . . . . . . . . . . .
Repetitive peak forward current‡, IFRM: Any D terminal from GND or VCC 200 mA. . . . . . . . . . . . . . . . . . . . .
Total through all GND or VCC terminals 1 A. . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡These values apply for tw ≤ 100 µs, duty cycle ≤ 20%.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
single-diode operation (see Note 2)
PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT
To VCC
IF = 18 mA 0.85 1.05
VF
Static forward voltage
To
V
CC IF = 50 mA 1.05 1.3
V
V
F
Static
forward
voltage
From GND
IF = 18 mA 0.75 0.95
V
From
GND
IF = 50 mA 0.95 1.2
VFM Peak forward voltage IF = 200 mA 1.45 V
IR
Static reverse current
To VCC
VR=7V
5
µA
I
R
Static
reverse
current
From GND
V
R =
7
V
5µ
A
Ct
Total ca
p
acitance
VR = 0 V, f = 1 MHz 8 16 p
F
C
t
Total
capacitance
VR = 2 V, f = 1 MHz 4 8
pF
§All typical values are at VCC = 5 V, TA = 25°C.
NOTE 2: Test conditions and limits apply separately to each of the diodes. The diodes not under test are open-circuited during the measurement
of these characteristics.
multiple-diode operation
PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT
I
Total IF current = 1 A, See Note 3 0.8 2
mA
I
x
Total IF current = 198 mA, See Note 3 0.02 0.2
mA
§All typical values are at VCC = 5 V, TA = 25°C.
NOTE 3: Ix is measured under the following conditions with one diode static, all others switching:
Switching diodes: tw = 100 µs, duty cycle = 20%
Static diode: VR = 5 V
The static diode input current is the internal crosstalk current, Ix.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trr Reverse recovery time IF = 10 mA, IRM(REC) = 10 mA, IR(REC) = 1 mA, RL = 100 Ω8 16 ns
,7 Pulse (599 "“9 A) Generalor DUT lnpul Pulse (See Nole A) Pulse (See ane A) Generalol ‘f 4,} ‘47 \ 10% 7, ‘ 0qu Inpul Pulse ‘ Wavelo (See Note A) 1 (See Mme 90% 777 *5 TEXAS INSTRUMENTS p057 OFFICE aox $553133 - DALLAS IEXAS 7
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
90%
10%
DUT
tr
VFM
(See Note A) (See Note B)
50 Ω450 Ω
Pulse
Generator
VF
Sampling
Oscilloscope
Input Pulse
(See Note A)
Output
Waveform
(See Note B)
NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: tr = 20 ns, ZO = 50 Ω, freq = 500 Hz,
duty cycle = 1%.
B. The output waveform is monitored by an oscilloscope having the following characteristics: tr ≤ 350 ps, Ri = 50 Ω, Ci ≤ 5 pF.
Figure 1. Forward Recovery Voltage
IF
DUT
90%
10%
tfIf
Pulse
Generator
(See Note A) (See Note B)
IR(REC)
trr
IRM(REC)
Sampling
Oscilloscope
Input Pulse
(See Note A)
Output
Waveform
(See Note B)
0
NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: tf = 0.5 ns, ZO = 50 Ω, tw ≥ 50 ns,
duty cycle = 1%.
B. The output waveform is monitored by an oscilloscope having the following characteristics: tr ≤ 350 ps, Ri = 50 Ω, Ci ≤ 5 pF.
Figure 2. Reverse Recovery Time
*9 TEXAS INSTRUMENTS
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Large negative transients at the inputs of memory devices (DRAMs, SRAMs, EPROMs, etc.) or on the CLOCK lines
of many clocked devices can result in improper operation of the devices. The SN74S1051 diode termination array
helps suppress negative transients caused by transmission-line reflections, crosstalk, and switching noise.
Diode terminations have several advantages when compared to resistor termination schemes. Split-resistor or
Thevenin-equivalent termination can cause a substantial increase in power consumption. The use of a single resistor
to ground to terminate a line usually results in degradation of the output high level, resulting in reduced noise immunity.
Series damping resistors placed on the outputs of the driver reduce negative transients, but they also can increase
propagation delays down the line because a series resistor reduces the output drive capability of the driving device.
Diode terminations have none of these drawbacks.
The operation of the diode arrays in reducing negative transients is explained in the following figures. The diode
conducts current when the voltage reaches a negative value large enough for the diode to turn on. Suppression of
negative transients is tracked by the current-voltage characteristic curve for that diode. Typical
current-versus-voltage curves for the SN74S1051 are shown in Figures 3 and 4.
To illustrate how the diode arrays act to reduce negative transients at the end of a transmission line, the test setup
in Figure 5 was evaluated. The resulting waveforms with and without the diode are shown in Figure 6.
The maximum effectiveness of the diode arrays in suppressing negative transients occurs when the diode arrays are
placed at the end of a line and/or the end of a long stub branching off a main transmission line. The diodes can also
reduce the negative transients that occur due to discontinuities in the middle of a line. An example of this is a slot in
a backplane that is provided for an add-on card.
– Forward Current – mA
VI – Forward Voltage – V
II
DIODE FORWARD CURRENT
vs
DIODE FORWARD VOLTAGE
–50
–40
–20
–10
0
–90
–30
0 0.2 0.4 0.6 0.8 1 1.2
–70
–60
–80
–100
1.4 1.6 1.8 2
TA = 25°C
Figure 3. Typical Input Current vs Input Voltage
(Lower Diode)
*5 TEXAS INSTRUMENTS
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
– Forward Current – mA
VI – Forward Voltage – V
II
DIODE FORWARD CURRENT
vs
DIODE FORWARD VOLTAGE
50
40
20
10
0
90
30
0 0.2 0.4 0.6 0.8 1 1.2
70
60
80
100
1.4 1.6 1.8 2
TA = 25°C
Figure 4. Typical Input Current vs Input Voltage
(Upper Diode)
x f *9 TEXAS INSTRUMENTS p057 OFFICE aox $553133 - DALLAS IEXAS 752%
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
ZO = 50 Ω
Length = 36 in.
Figure 5. Diode Test Setup
31.500 ns
Ch 2 = 1.880 V/div
Timebase = 5.00 ns/V
Memory 1 = 1.880 V/div
Vmarker 1 = –1.353 V
Vmarker 2 = –3.647 V
Offset = 0.000 V
Delay = 56.500 ns
Delta V = –2.293 V
56.500 ns 81.500 ns
End-of-Line With Diode
End-of-
Line
Without
Diode
Vmarker 1
Vmarker 2
Figure 6. Reduction of Negative Transients at the End of a Transmission Line
I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74S1051D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 S1051
SN74S1051DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 S1051
SN74S1051N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74S1051N
SN74S1051NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74S1051
SN74S1051PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 S1051
SN74S1051PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 S1051
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74S1051DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74S1051NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74S1051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74S1051DR SOIC D 16 2500 340.5 336.1 32.0
SN74S1051NSR SO NS 16 2000 356.0 356.0 35.0
SN74S1051PWR TSSOP PW 16 2000 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74S1051D D SOIC 16 40 507 8 3940 4.32
SN74S1051N N PDIP 16 25 506 13.97 11230 4.32
SN74S1051N N PDIP 16 25 506 13.97 11230 4.32
SN74S1051PW PW TSSOP 16 90 530 10.2 3600 3.5
Pack Materials-Page 3
MECHANICAL DATA D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘ gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘ fimmamfl J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
MECHANICAL DATA NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE 14-PINS SHOWN HHFHHFH j j t t H H j, A jfi/—\ % lgLLLLLiLLL/fiif A MAX 1060 1060 1290 1530 A MW 990 9,90 1230 14‘70 4040062/0 03/03 VOTES: A. AH Hneur dimenswons are m mHHmetevs a, Tm: druwmg 5 subject to change wmom name. 0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15 INSTRUMEN'IS www.li.m
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
www.ti.com
PACKAGE OUTLINE
C
8.2
7.4 TYP
14X 1.27
16X 0.51
0.35
2X
8.89
0.15 TYP
0 - 10
0.3
0.1
2.00 MAX
(1.25)
0.25
GAGE PLANE
1.05
0.55
A
10.4
10.0
NOTE 3
B5.4
5.2
NOTE 4
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
116
0.25 C A B
9
8
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.500
£353 RE Vi“““‘ ““““““ WEECE = Era ,MQL 1"
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
14X (1.27)
(R0.05) TYP
(7)
16X (1.85)
16X (0.6)
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:7X
SYMM
1
89
16
SEE
DETAILS
SYMM
Efimfifij v¢\‘\‘\‘\
www.ti.com
EXAMPLE STENCIL DESIGN
(7)
(R0.05) TYP
16X (1.85)
16X (0.6)
14X (1.27)
4220735/A 12/2021
SOP - 2.00 mm max heightNS0016A
SOP
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
89
16
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