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SN74LVC2G14

SCES200O –APRIL 1999–REVISED AUGUST 2015

SN74LVC2G14 Dual Schmitt-Trigger Inverter

1 Features 3 Description

This dual Schmitt-trigger inverter is designed for

1• Available in the TI NanoFree™ Package 1.65-V to 5.5-V VCC operation.

• Supports 5-V VCC Operation NanoFree™ package technology is a major

• Inputs Accept Voltages to 5.5 V breakthrough in IC packaging concepts, using the die

• Max tpd of 5.4 ns at 3.3 V as the package.

• Low-Power Consumption, 10-μA Maximum ICC The SN74LVC2G14 device contains two inverters

• ±24-mA Output Drive at 3.3 V and performs the Boolean function Y = A. The device

• Typical VOLP (Output Ground Bounce) functions as two independent inverters, but because

of Schmitt action, it may have different input threshold

<0.8 V at VCC = 3.3 V, TA= 25°C levels for positive-going (VT+) and negative-going

• Typical VOHV (Output VOH Undershoot) (VT–) signals.

>2 V at VCC = 3.3 V, TA= 25°C This device is fully specified for partial-power-down

• Ioff Supports Live Insertion, Partial-Power-Down applications using Ioff. The Ioff circuitry disables the

Mode, and Back-Drive Protection outputs, preventing damaging current backflow

• Support Translation Down through the device when it is powered down.

(5 V to 3.3 V; 3.3 V to 1.8 V)

• Latch-Up Performance Exceeds 100 mA Device Information(1)

Per JESD 78, Class II PART NUMBER PACKAGE BODY SIZE (NOM)

SN74LVC2G14DBV SOT-23 (6) 2.90 mm × 1.60 mm

2 Applications SN74LVC2G14DCK SC70 (6) 2.00 mm × 1.25 mm

SN74LVC2G14YZP DSBGA (6) 1.41 mm × 0.91 mm

• Body Control Modules

(1) For all available packages, see the orderable addendum at

• Engine Control Modules the end of the data sheet.

• Arcade, Casino, and Gambling Machines

• Servers and High-Performance Computing

• EPOS, ECR, and Cash Drawer

• Routers

• Desktop PC

Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

l TEXAS INSTRUMENTS

SN74LVC2G14

SCES200O –APRIL 1999–REVISED AUGUST 2015

www.ti.com

Table of Contents

8.1 Overview ................................................................... 8

1 Features.................................................................. 18.2 Functional Block Diagram......................................... 8

2 Applications ........................................................... 18.3 Feature Description................................................... 8

3 Description ............................................................. 18.4 Device Functional Modes.......................................... 8

4 Revision History..................................................... 29 Application and Implementation .......................... 9

5 Pin Configuration and Functions......................... 39.1 Application Information.............................................. 9

6 Specifications......................................................... 49.2 Typical Application ................................................... 9

6.1 Absolute Maximum Ratings ..................................... 410 Power Supply Recommendations ..................... 10

6.2 ESD Ratings ............................................................ 411 Layout................................................................... 10

6.3 Recommended Operating Conditions ...................... 411.1 Layout Guidelines ................................................. 10

6.4 Thermal Information.................................................. 511.2 Layout Example .................................................... 11

6.5 Electrical Characteristics........................................... 512 Device and Documentation Support ................. 12

6.6 Switching Characteristics, –40°C to 85°C ................ 612.1 Community Resources.......................................... 12

6.7 Switching Characteristics, –40°C to 125°C............... 612.2 Trademarks........................................................... 12

6.8 Operating Characteristics.......................................... 612.3 Electrostatic Discharge Caution............................ 12

6.9 Typical Characteristics.............................................. 612.4 Glossary................................................................ 12

7 Parameter Measurement Information .................. 713 Mechanical, Packaging, and Orderable

8 Detailed Description.............................................. 8Information ........................................................... 12

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision N (June 2015) to Revision O Page

• Added TJjunction temperature spec to Abs Max Ratings...................................................................................................... 4

Changes from Revision M (November 2013) to Revision N Page

• Added Applications,Device Information table, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Product Folder Links: SN74LVC2G14

l TEXAS INSTRUMENTS WWW HEB HRH HHH

GND

5VCC

1A 1Y

GND

VCC

1A 1Y

GND

VCC

SN74LVC2G14

www.ti.com

SCES200O –APRIL 1999–REVISED AUGUST 2015

5 Pin Configuration and Functions

DBV Package DCK Package

6-Pin SOT-23 6-Pin SC70

Top View Top View

YZP Package

6-Pin DSBGA

Bottom View

See mechanical drawing for dimensions.

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

1A 1 I Gate 1 logic signal

1Y 6 O Gate 1 inverted signal

2A 3 I Gate 2 logic signal

2Y 4 O Gate 2 inverted signal

GND 2 — Ground

VCC 5 — Supply/Power Pin

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SCES200O –APRIL 1999–REVISED AUGUST 2015

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage –0.5 6.5 V

VIInput voltage(2) –0.5 6.5 V

VOVoltage applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V

VOVoltage applied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V

IIK Input clamp current VI< 0 –50 mA

IOK Output clamp current VO< 0 –50 mA

IOContinuous output current ±50 mA

Continuous current through VCC or GND ±100 mA

TJJunction temperature –65 150 °C

Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

V(ESD) Electrostatic discharge V

Charged-device model (CDM), per JEDEC specification JESD22- ±1000

C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions. Pins listed as ±YYY V may actually have higher performance.

6.3 Recommended Operating Conditions

See (1)

MIN MAX UNIT

Operating 1.65 5.5

VCC Supply voltage V

Data retention only 1.5

VIInput voltage 0 5.5 V

VOOutput voltage 0 VCC V

VCC = 1.65 V –4

VCC = 2.3 V –8

IOH High-level output current –16 mA

VCC = 3 V –24

VCC = 4.5 V –32

VCC = 1.65 V 4

VCC = 2.3 V 8

IOL Low-level output current 16 mA

VCC = 3 V 24

VCC = 4.5 V 32

TAOperating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs,SCBA004.

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SCES200O –APRIL 1999–REVISED AUGUST 2015

6.4 Thermal Information

SN74LVC2G14

THERMAL METRIC(1) DBV (SOT23) DCK (SC70) YZP (DSBGA) UNIT

6 PINS 6 PINS 6 PINS

RθJA Junction-to-ambient thermal resistance 215 259 139 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 55 87 18 °C/W

RθJB Junction-to-board thermal resistance 57 89 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

–40°C to 85°C –40°C to 125°C

PARAMETER TEST CONDITIONS VCC UNIT

MIN TYP(1) MAX MIN TYP(1) MAX

1.65 V 0.7 1.4 0.7 1.4

2.3 V 1 1.7 1 1.7

VT+

Positive-going input 3 V 1.3 2.2 1.3 2.2 V

threshold voltage 4.5 V 1.9 3.1 1.9 3.1

5.5 V 2.2 3.7 2.2 3.7

1.65 V 0.3 0.7 0.3 0.7

2.3 V 0.4 1 0.4 1

VT–

Negative-going input 3 V 0.6 1.3 0.6 1.3 V

threshold voltage 4.5 V 1.1 2 1.1 2

5.5 V 1.4 2.5 1.4 2.5

1.65 V 0.3 0.8 0.3 0.8

2.3 V 0.4 0.9 0.4 0.9

ΔVT

Hysteresis 3 V 0.4 1.1 0.4 1.1 V

(VT+ – VT–)4.5 V 0.6 1.3 0.6 1.3

5.5 V 0.7 1.4 0.7 1.4

IOH = –100 μA 1.65 V to 4.5 V VCC – 0.1 VCC – 0.1

IOH = –4 mA 1.65 V 1.2 1.2

IOH = –8 mA 2.3 V 1.9 1.9

VOH V

IOH = –16 mA 3 V 2.4 2.4

IOH = –24 mA 3 V 2.3 2.3

IOH = –32 mA 4.5 V 3.8 3.8

IOL = 100 μA 1.65 V to 4.5 V 0.1 0.1

IOL = 4 mA 1.65 V 0.45 0.45

IOL = 8 mA 2.3 V 0.3 0.3

VOL V

IOL = 16 mA 3 V 0.4 0.4

IOL = 24 mA 3 V 0.55 0.55

IOL = 32 mA 4.5 V 0.55 0.55

IIA input VI= 5.5 V or GND 0 to 5.5 V ±5 ±5 μA

Ioff VIor VO= 5.5 V 0 ±10 ±10 μA

ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 10 μA

One input at VCC – 0.6 V,

ΔICC 3 V to 5.5 V 500 500 μA

Other inputs at VCC or GND

CIVI= VCC or GND 3.3 V 4 pF

(1) All typical values are at VCC = 3.3 V, TA= 25°C.

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l TEXAS INSTRUMENTS 4 00 750 0 50 1 00 1 50

TPD (ns)

Temperature (°C)

VCC (V)

TPD (ns)

0 1 2 3 4 5 6

D002

TPD

SN74LVC2G14

SCES200O –APRIL 1999–REVISED AUGUST 2015

www.ti.com

6.6 Switching Characteristics, –40°C to 85°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V

PARAMETER UNIT

(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 3.9 9.5 1.9 5.7 2 5.4 1.5 4.3 ns

6.7 Switching Characteristics, –40°C to 125°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V

PARAMETER UNIT

(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 3.9 10.5 1.9 6.5 2 6 1.5 4.7 ns

6.8 Operating Characteristics

TA= 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V

PARAMETER TEST CONDITIONS UNIT

TYP TYP TYP TYP

Cpd Power dissipation capacitance f = 10 MHz 16 17 18 21 pF

6.9 Typical Characteristics

Figure 2. TPD Across VCC at 25°C

Figure 1. TPD Across Temperature at 3.3 V VCC

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*9 TEXAS INSTRUMENTS «H ; H; ‘ll‘ 1

tsu

FromOutput

UnderTest

(seeNote A)

LOADCIRCUIT

VLOAD

Open

GND

DataInput

TimingInput

0V

Input

0V

Input

Output

Waveform1

S1atV

(seeNoteB)

LOAD

Output

Waveform2

S1atGND

(seeNoteB)

VOL

VOH

0V

»0V

Output

TEST S1

t /t

PLH PHL Open

Output

Control

VMVM

1.8V 0.15V±

2.5V 0.2V±

3.3V 0.3V±

5V 0.5V±

1kW

500 W

VCC RL

2× VCC

6V

2× VCC

VLOAD CL

30pF

50pF

0.15V

0.3V

3V

VCC/2

1.5V

VCC/2

£2ns

£2.5ns

INPUTS

t /t

r f

VCC

VLOAD

t /t

PLZ PZL

GND

t /t

PHZ PZH

VOLTAGEWAVEFORMS

ENABLE ANDDISABLETIMES

LOW- ANDHIGH-LEVEL ENABLING

VOLTAGEWAVEFORMS

PROPAGATIONDELAY TIMES

INVERTING ANDNONINVERTINGOUTPUTS

NOTES: A. C includesprobeandjigcapacitance.

B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.

Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.

C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .

D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.

E. t andt arethesameast .

F. t andt arethesameast .

G. t andt arethesameast .

H. Allparametersandwaveformsarenotapplicabletoalldevices.

PLZ PHZ dis

PZL PZH en

PLH PHL pd

£ W

VOLTAGEWAVEFORMS

PULSEDURATION

VOLTAGEWAVEFORMS

SETUP ANDHOLDTIMES

V /2

LOAD

tPZL tPLZ

tPHZ

tPZH

V – V

OH D

V +V

OL D

VMVM

VOL

VOH

VOL

tPLH tPHL

tPLH

tPHL

SN74LVC2G14

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SCES200O –APRIL 1999–REVISED AUGUST 2015

7 Parameter Measurement Information

Figure 3. Load Circuit and Voltage Waveforms

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1A 1Y

1 6

2A 2Y

3 4

SN74LVC2G14

SCES200O –APRIL 1999–REVISED AUGUST 2015

www.ti.com

8 Detailed Description

8.1 Overview

The SN74LVC2G14 device contains two Schmitt Trigger Inverter and performs the Boolean function Y = A. The

device functions as an independent inverter, but because of Schmitt Trigger action, it will have different input

threshold levels for a positive-going (Vt+) and negative-going (Vt-) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuit disables the output,

preventing damaging current back-flow through the device when it is powered down.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Support Translation Down (5 V to 3.3 V; 3.3 V to 1.8 V)

As the inputs are 5.5-V tolerant, the device can be used as a down translator. When the input voltage exceeds

VT+ (Max), the output will follow VCC, performing down-translation if the input voltage exceeds VCC.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SN74LVC2G14.

Table 1. Functional Table

(Each Inverter)

INPUT OUTPUT

A Y

H L

L H

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~2.2M

16 pF

~32 pF ~32pF

50 pF

SN74LVC2G14

(one channel)

SN74LVC2G14

www.ti.com

SCES200O –APRIL 1999–REVISED AUGUST 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC2G14 device is a high-drive CMOS device that can be used for a multitude of buffer type functions

where the input is slow or noisy. The device can produce 24 mA of drive current at 3.3 V, making it Ideal for

driving multiple outputs and good for high-speed applications up to 100 MHz. The inputs are 5.5-V tolerant

allowing it to translate down to VCC.

9.2 Typical Application

Figure 4. Typical Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus

contention because it can drive currents that would exceed maximum limits. The high drive will also create fast

edges into light loads so routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions

– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.

– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.

– Inputs are overvoltage tolerant allowing them to go as high as (VImax) in the Recommended Operating

Conditions table at any valid VCC .

2. Recommend Output Conditions

– Load currents should not exceed (IOmax) per output and should not exceed (continuous current through

VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.

– Outputs should not be pulled above VCC.

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Frequency - MHz

Icc - mA

0 20 40 60 80

D003

Icc 1.8V

Icc 2.5V

Icc 3.3V

Icc 5V

SN74LVC2G14

SCES200O –APRIL 1999–REVISED AUGUST 2015

www.ti.com

Typical Application (continued)

9.2.3 Application Curve

Figure 5. ICC vs Frequency

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a

single supply, TI recommends a 0.1-μF capacitor. If there are multiple VCC pins, then TI recommends a 0.01-μF

or 0.022-μF capacitor for each power pin. It is ok to parallel multiple bypass capacitors to reject different

frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be

installed as close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions

of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only

3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined

voltages at the outside connections result in undefined operational states. The following rules must be observed

under all circumstances:

• All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from

floating.

• The logic level that should be applied to any particular unused input depends on the function of the device.

Generally they will be tied to GND or VCC whichever make more sense or is more convenient.

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SN74LVC2G14 VCC

1Y1A

GND

0.1µF

VDD

Unused inputs connected to

GND or VCC to prevent

floating

Keep signal traces as short as

possible

SN74LVC2G14

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SCES200O –APRIL 1999–REVISED AUGUST 2015

11.2 Layout Example

Figure 6. Layout Schematic

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SCES200O –APRIL 1999–REVISED AUGUST 2015

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12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.2 Trademarks

NanoFree, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser based versions of this data sheet, refer to the left hand navigation.

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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN74LVC2G14DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C145, C14F, C14K,

C14R)

SN74LVC2G14DBVRE4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C14F, C14R)

SN74LVC2G14DBVRG4 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C14F, C14R)

SN74LVC2G14DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C145, C14F, C14K,

C14R)

SN74LVC2G14DBVTG4 ACTIVE SOT-23 DBV 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (C14F, C14R)

SN74LVC2G14DCK3 ACTIVE SC70 DCK 6 3000 RoHS &

Non-Green SNBI Level-1-260C-UNLIM -40 to 125 (CFF, CFZ)

SN74LVC2G14DCKR ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CF5, CFF, CFJ, CF

K, CFR)

SN74LVC2G14DCKRE4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF5

SN74LVC2G14DCKRG4 ACTIVE SC70 DCK 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF5

SN74LVC2G14DCKT ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CF5, CFF, CFJ, CF

K, CFR)

SN74LVC2G14DCKTG4 ACTIVE SC70 DCK 6 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CF5

SN74LVC2G14YZPR ACTIVE DSBGA YZP 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 (CF7, CFN)

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

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PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC2G14 :

•Automotive: SN74LVC2G14-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I‘KO '«Pt» Reel DlameIer AD Dimension designed to accommodate the component wIdlh ED Dimension designed to accommodate the component Iength K0 Dimension designed to accommodate the component thickness 7 w Overau Width onhe carrier tape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE C) O O D O O D O iSDrockeIHuIes —> User DIreCIIDn 0' Feed \i/ Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74LVC2G14DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3

SN74LVC2G14DBVR SOT-23 DBV 6 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

SN74LVC2G14DBVRG4 SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

SN74LVC2G14DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

SN74LVC2G14DBVT SOT-23 DBV 6 250 178.0 9.2 3.3 3.23 1.55 4.0 8.0 Q3

SN74LVC2G14DBVTG4 SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3

SN74LVC2G14DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

SN74LVC2G14DCKR SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3

SN74LVC2G14DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3

SN74LVC2G14DCKRG4 SC70 DCK 6 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3

SN74LVC2G14DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3

SN74LVC2G14DCKT SC70 DCK 6 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3

SN74LVC2G14DCKTG4 SC70 DCK 6 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3

SN74LVC2G14YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC2G14DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0

SN74LVC2G14DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0

SN74LVC2G14DBVRG4 SOT-23 DBV 6 3000 180.0 180.0 18.0

SN74LVC2G14DBVT SOT-23 DBV 6 250 202.0 201.0 28.0

SN74LVC2G14DBVT SOT-23 DBV 6 250 180.0 180.0 18.0

SN74LVC2G14DBVTG4 SOT-23 DBV 6 250 180.0 180.0 18.0

SN74LVC2G14DCKR SC70 DCK 6 3000 180.0 180.0 18.0

SN74LVC2G14DCKR SC70 DCK 6 3000 202.0 201.0 28.0

SN74LVC2G14DCKRG4 SC70 DCK 6 3000 180.0 180.0 18.0

SN74LVC2G14DCKT SC70 DCK 6 250 202.0 201.0 28.0

SN74LVC2G14DCKT SC70 DCK 6 250 180.0 180.0 18.0

SN74LVC2G14DCKTG4 SC70 DCK 6 250 180.0 180.0 18.0

SN74LVC2G14YZPR DSBGA YZP 6 3000 220.0 220.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2020

Pack Materials-Page 2

MECHANICAL DATA DCK (R-PDSO-GS) PLASTIC SMALL-OUTLINE PACKAGE E 18’) 6 4 7 H Fl H ‘ﬁ «40 1233 \ ’i’ To enugemane Seanng Mane Pm 1/ ' ‘ ' ‘ ‘ maexArea Wm H m} j; / ‘ u / Um "4L 1—]; f Scamg Mane \\ \ / 31 409555574/8 U‘ /200/ , m m hmeters AH \mec' mmens‘mrs Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom ﬂcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m FuHs an JFDFC M07763 vunuhcn AB NO'FS Umm> INSrRUMEm-s www.1i.com

LAND PATTERN DATA 7PJSOiC6> PLASTC SMALL OU’LME NOTES' maop> Exc'm‘e Boc'd Luyum stem Openings Based or a stencﬂ hickncss uf 127mm (005mm) * 1* :E /23\\der Musk Cpen‘wg “ 2m Geometry M \meur dimensmns are m m'ﬂhrvete's Th's drawqu is sweat (a chc'vge mm: 'vuhce Custume's shoud p‘uce a new 01 We cvcmt buurd (abr'cahun c'awmg rm :0 uHer the ce'ﬂe' smder musk deﬁned and, ”Jbﬁcuhon \PC77351 is reco'n'nended (Dr uHernme designs Laser cumrg opc'mvcs mm "apczmda wuHs and mo rouncmq corners wm am bcncr aosxc recuscv mstomcrs show can thew Guard assemwy sue for gene design recommencnmons Exomme sxercu deswgw basec on a 50% vo‘umemc bad My paste M‘cr m M4523 var other new rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com

3: ﬁg,

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PACKAGE OUTLINE

0.22

0.08 TYP

0.25

3.0

2.6

2X 0.95

1.45 MAX

0.15

0.00 TYP

6X 0.50

0.25

0.6

0.3 TYP

0 TYP

1.9

3.05

2.75

1.75

1.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0006A

SMALL OUTLINE TRANSISTOR

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

0.2 C A B

INDEX AREA

PIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

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EXAMPLE BOARD LAYOUT

0.07 MAX

ARROUND 0.07 MIN

ARROUND

6X (1.1)

6X (0.6)

(2.6)

2X (0.95)

(R0.05) TYP

4214840/C 06/2021

SOT-23 - 1.45 mm max heightDBV0006A

SMALL OUTLINE TRANSISTOR

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

PKG

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

EXPOSED METAL

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

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EXAMPLE STENCIL DESIGN

(2.6)

2X(0.95)

6X (1.1)

6X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0006A

SMALL OUTLINE TRANSISTOR

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

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PACKAGE OUTLINE

0.5 MAX

0.19

0.15

TYP

0.5 TYP

6X 0.25

0.21

0.5

TYP

B E A

4219524/A 06/2014

DSBGA - 0.5 mm max heightYZP0006

DIE SIZE BALL GRID ARRAY

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. NanoFreeTM package configuration.

NanoFree Is a trademark of Texas Instruments.

BALL A1

CORNER

SEATING PLANE

BALL TYP 0.05 C

0.015 C A B

SYMM

SCALE 9.000

D: Max =

E: Max =

1.418 mm, Min =

0.918 mm, Min =

1.358 mm

0.858 mm

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EXAMPLE BOARD LAYOUT

6X ( )0.225 (0.5) TYP

(0.5) TYP

()

METAL

0.225 0.05 MAX

SOLDER MASK

OPENING

METAL

UNDER

MASK

()

SOLDER MASK

OPENING

0.225

0.05 MIN

4219524/A 06/2014

DSBGA - 0.5 mm max heightYZP0006

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017).

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

DEFINED

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EXAMPLE STENCIL DESIGN

(0.5)

TYP

(0.5) TYP

6X ( 0.25) (R ) TYP0.05

METAL

TYP

4219524/A 06/2014

DSBGA - 0.5 mm max heightYZP0006

DIE SIZE BALL GRID ARRAY

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:40X

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