Texas Instruments 的 SN74LVC1G97-Q1 规格书

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1
FEATURES
Seemechanicaldrawingsfordimensions.
DBVPACKAGE
(TOP VIEW)
DCKPACKAGE
(TOP VIEW)
2
GND VCC
5
34
In0 Y
6
1
In1 In2
34
In0
2
GND
Y
5
1
In1
VCC
6In2
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G97-Q1
www.ti.com
........................................................................................................................................................ SCES561D – MARCH 2004 – REVISED APRIL 2008
CONFIGURABLE MULTIPLE-FUNCTION GATE
•Qualified for Automotive Applications •Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•Supports 5-V V
CC
Operation
•ESD Protection Exceeds JESD 22•Inputs Accept Voltages to 5.5 V
– 2000-V Human-Body Model (A114-A)•Max t
pd
of 7.3 ns at 3.3 V
– 200-V Machine Model (A115-A)•Low Power Consumption, 10- µA Max I
CC
– 1000-V Charged-Device Model (C101)•± 24-mA Output Drive at 3.3 V
•Choose From Nine Specific Logic Functions•I
off
Supports Partial-Power-Down ModeOperation
This configurable multiple-function gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC1G97 features configurable multiple functions. The output state is determined by eight patterns of3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. Allinputs can be connected to V
CC
or GND.
This device functions as an independent gate but, because of Schmitt action, it may have different inputthreshold levels for positive-going (V
T+
) and negative-going (V
T –
) signals.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(3)
SOT (SOT-23) – DBV Reel of 3000 SN74LVC1G97QDBVRQ1 C97_– 40 °C to 125 °C
SOT (SC-70) – DCK Reel of 3000 SN74LVC1G97QDCKRQ1 CS_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .(3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
{L} TEXAS INSTRUMENTS
3
1
6
In2
In1
In0
4Y
SN74LVC1G97-Q1
SCES561D – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................
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FUNCTION TABLE
INPUTS
OUTPUT
YIn2 In1 In0
L L L L
L L H L
L H L H
L H H H
H L L L
H L H H
H H L L
H H H H
LOGIC DIAGRAM (POSITIVE LOGIC)
FUNCTION TABLE
LOGIC FUNCTION FIGURE NO.
2-to-1 data selector 1
2-input AND gate 2
2-input OR gate with one inverted input 3
2-input NAND gate with one inverted input 3
2-input AND gate with one inverted input 4
2-input NOR gate with one inverted input 4
2-input OR gate 5
Inverter 6
Noninverted buffer 7
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LOGIC CONFIGURATIONS
1
2
3
6
5
4
A
Y
A/B
VCC
Y
B
GND
A
B
A/B
1
2
3
6
5
4
BY
A
VCC
Y
GND
A
B
1
2
3
6
5
4
BY
A
VCC
AY
B
AY
BGND
AY
B
AY
B1
2
3
6
5
4
B
Y
A
VCC
GND
1
2
3
6
5
4
B
Y
A
VCC
AY
B
GND
1
2
3
6
5
4Y
A
VCC
YA
GND
1
2
3
6
5
4Y
VCC
YA
GND
A
SN74LVC1G97-Q1
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........................................................................................................................................................ SCES561D – MARCH 2004 – REVISED APRIL 2008
Figure 1. 2-to-1 Data Selector Figure 2. 2-Input AND Gate
Figure 3. 2-Input OR Gate With One Inverted Input Figure 4. 2-Input AND Gate With One Inverted Input2-Input NAND Gate With One Inverted Input 2-Input NOR Gate With One Inverted Input
Figure 5. 2-Input OR Gate Figure 6. Inverter
Figure 7. Noninverted Buffer
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74LVC1G97-Q1
SCES561D – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................
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over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 6.5 V
V
I
Input voltage range
(2)
– 0.5 6.5 V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
– 0.5 6.5 V
V
O
Voltage range applied to any output in the high or low state
(2) (3)
– 0.5 V
CC
+ 0.5 V
I
IK
Input clamp current V
I
< 0 – 50 mA
I
OK
Output clamp current V
O
< 0 – 50 mA
I
O
Continuous output current ± 50 mA
Continuous current through V
CC
or GND ± 100 mA
DBV package 165θ
JA
Package thermal impedance
(4)
°C/WDCK package 259
T
stg
Storage temperature range – 65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
Operating 1.65 5.5V
CC
Supply voltage VData retention only 1.5
V
I
Input voltage 0 5.5 V
V
O
Output voltage 0 V
CC
V
V
CC
= 1.65 V – 4
V
CC
= 2.3 V – 8
I
OH
High-level output current – 16 mAV
CC
= 3 V
– 24
V
CC
= 4.5 V – 24
V
CC
= 1.65 V 4
V
CC
= 2.3 V 8
I
OL
Low-level output current 16 mAV
CC
= 3 V
24
V
CC
= 4.5 V 24
T
A
Operating free-air temperature – 40 125 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
Switching Characteristics
SN74LVC1G97-Q1
www.ti.com
........................................................................................................................................................ SCES561D – MARCH 2004 – REVISED APRIL 2008
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
1.65 V 0.6 1.4
V
T+
2.3 V 1 1.8Positive-going
3 V 1.3 2.2 Vinput threshold
4.5 V 1.9 3.1voltage
5.5 V 2.2 3.6
1.65 V 0.3 0.7
V
T –
2.3 V 0.5 1Negative-going
3 V 0.7 1.4 Vinput threshold
4.5 V 1 2voltage
5.5 V 1.2 2.3
1.65 V 0.3 0.8
2.3 V 0.4 0.9ΔV
THysteresis 3 V 0.5 1 V(V
T+
– V
T –
)
4.5 V 0.6 1.5
5.5 V 0.7 1.7
I
OH
= – 100 µA 1.65 V to 5.5 V V
CC
– 0.2
I
OH
= – 4 mA 1.65 V 1.2
I
OH
= – 8 mA 2.3 V 1.9V
OH
VI
OH
= – 16 mA 3 V 2.4
3 V 2.3I
OH
= – 24 mA
4.5 V 3.8
I
OL
= 100 µA 1.65 V to 5.5 V 0.1
I
OL
= 4 mA 1.65 V 0.45
I
OL
= 8 mA 2.3 V 0.3V
OL
VI
OL
= 16 mA 3 V 0.45
3 V 0.55I
OL
= 24 mA
4.5 V 0.58
I
I
V
I
= 5.5 V or GND 0 to 5.5 V ± 5 µA
I
off
V
I
or V
O
= 5.5 V 0 ± 10 µA
I
CC
V
I
= 5.5 V or GND, I
O
= 0 1.65 V to 5.5 V 10 µA
ΔI
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 5.5 V 500 µA
C
i
V
I
= V
CC
or GND 3.3 V 3.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
Any In Y 3.2 16.4 2 9.3 1.5 7.3 1.1 6.1 ns
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Operating Characteristics
SN74LVC1G97-Q1
SCES561D – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................
www.ti.com
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP TYP
C
pd
Power dissipation capacitance f = 10 MHz 22 23 23 26 pF
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PARAMETER MEASUREMENT INFORMATION
th
tsu
FromOutput
UnderTest
C
(seeNote A)
L
LOADCIRCUIT
S1
VLOAD
Open
GND
RL
DataInput
TimingInput
0V
0V
0V
tW
Input
0V
Input
Output
Waveform1
S1atV
(seeNoteB)
LOAD
Output
Waveform2
S1atGND
(seeNoteB)
VOL
VOH
0V
»0V
Output
Output
TEST S1
t /t
PLH PHL Open
Output
Control
VM
VMVM
VM
VM
1.8V 0.15V±
2.5V 0.2V±
3.3V 0.3V±
5V 0.5V±
1kW
500 W
500 W
500 W
VCC RL
2× VCC
2× VCC
6V
2× VCC
VLOAD CL
30pF
30pF
50pF
50pF
0.15V
0.15V
0.3V
0.3V
VD
3V
VI
VCC/2
VCC/2
1.5V
VCC/2
VM
£2ns
£2ns
£2.5ns
£2.5ns
INPUTS
RL
t /t
r f
VCC
VCC
VCC
VLOAD
t /t
PLZ PZL
GND
t /t
PHZ PZH
VOLTAGEWAVEFORMS
ENABLE ANDDISABLETIMES
LOW- ANDHIGH-LEVEL ENABLING
VOLTAGEWAVEFORMS
PROPAGATIONDELAY TIMES
INVERTING ANDNONINVERTINGOUTPUTS
NOTES: A. C includesprobeandjigcapacitance.
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislow,exceptwhendisabledbytheoutputcontrol.
Waveform2isforanoutputwithinternalconditionssuchthattheoutputishigh,exceptwhendisabledbytheoutputcontrol.
C. Allinputpulsesaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR 10MHz,Z =50 .
D. Theoutputsaremeasuredoneatatime,withonetransitionpermeasurement.
E. t andt arethesameast .
F. t andt arethesameast .
G. t andt arethesameast .
H. Allparametersandwaveformsarenotapplicabletoalldevices.
L
O
PLZ PHZ dis
PZL PZH en
PLH PHL pd
£ W
VOLTAGEWAVEFORMS
PULSEDURATION
VOLTAGEWAVEFORMS
SETUP ANDHOLDTIMES
VI
VI
VI
VM
VM
V /2
LOAD
tPZL tPLZ
tPHZ
tPZH
V – V
OH D
V +V
OL D
VM
VMVM
VM
VOL
VOH
VI
VI
VOH
VOL
VM
VM
VM
VM
tPLH tPHL
tPLH
tPHL
SN74LVC1G97-Q1
www.ti.com
........................................................................................................................................................ SCES561D – MARCH 2004 – REVISED APRIL 2008
Figure 8. Load Circuit and Voltage Waveforms
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PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1G97QDBVRQ1 SOT-23 DBV 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
SN74LVC1G97QDCKRQ1 SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G97QDBVRQ1 SOT-23 DBV 6 3000 200.0 183.0 25.0
SN74LVC1G97QDCKRQ1 SC70 DCK 6 3000 180.0 180.0 18.0
Pack Materials-Page 2
3: fig,
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.45 MAX
0.15
0.00 TYP
6X 0.50
0.25
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
6
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
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EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
6X (1.1)
6X (0.6)
(2.6)
2X (0.95)
(R0.05) TYP
4214840/C 06/2021
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
6
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
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EXAMPLE STENCIL DESIGN
(2.6)
2X(0.95)
6X (1.1)
6X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0006A
SMALL OUTLINE TRANSISTOR
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
6
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