Texas Instruments 的 SN74LVC1404 规格书

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1404
SCES469F –AUGUST 2003–REVISED MARCH 2020
SN74LVC1404 Oscillator Driver for Crystal Oscillator or Ceramic Resonator
1
1 Features
1• Available in the Texas Instruments
NanoFree™ package
• Supports 5-V VCC operation
• Inputs accept voltages to 5.5 V
• One buffered inverter with Schmitt-trigger input
and two unbuffered inverters
• Integrated solution for oscillator applications
• Suitable for commonly used clock frequencies:
– 15 kHz, 3.58 MHz, 4.43 MHz, 13 MHz,
25 MHz, 26 MHz, 27 MHz, 28 MHz
• Control input to disable the oscillator circuit
• Low power consumption (10-µA Max ICC) in
standby state
• ±24-mA Output Drive at 3.3 V
• Ioff supports live insertion, partial-power-down
mode, and back-drive protection
• Latch-up performance exceeds 100 mA
Per JESD 78, Class II
• ESD protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– 1000-V Charged-device model (C101)
2 Applications
• Servers
• PCs and notebooks
• Network switches
• Wearable health and fitness devices
• Telecom infrastructures
• Electronic points-of-sale
3 Description
The SN74LVC1404 device consists of one inverter
with a Schmitt-trigger input and two unbuffered
inverters. It is designed for 1.65-V to 5.5-V VCC
operation.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1404DCT SM8 (8) 2.95 mm × 2.80 mm
SN74LVC1404DCU VSSOP (8) 2.30 mm × 2.00 mm
SN74LVC1404YZP DSBGA (8) 1.88 mm × 0.88 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics, CL= 15 pF ...................... 7
7.7 Switching Characteristics, CL= 30 pF or 50 pF........ 7
7.8 Operating Characteristics.......................................... 7
7.9 Typical Characteristics.............................................. 7
8 Parameter Measurement Information .................. 8
9 Detailed Description............................................ 10
9.1 Overview ................................................................. 10
9.2 Functional Block Diagram....................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes........................................ 11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 17
12 Layout................................................................... 17
12.1 Layout Guidelines ................................................. 17
12.2 Layout Example .................................................... 17
13 Device and Documentation Support ................. 18
13.1 Trademarks........................................................... 18
13.2 Electrostatic Discharge Caution............................ 18
13.3 Glossary................................................................ 18
14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2014) to Revision F Page
• Formatted pinout figures for search capability ....................................................................................................................... 3
• Corrected pin numbering for the DSBGA package to match the mechanical drawing ......................................................... 3
• Changed ESD Ratings table format to comply with JEDEC standards ................................................................................ 4
• Added YZP TAMIN /MAX specs and package thermal information ...................................................................................... 5
Changes from Revision D (January 2007) to Revision E Page
• Updated document to new TI data sheet format.................................................................................................................... 1
• Removed Ordering Information table. ................................................................................................................................... 1
• Added Applications................................................................................................................................................................. 1
• Added Device Information table. ............................................................................................................................................ 1
• Added Handling Ratings table. .............................................................................................................................................. 4
• Changed MAX ambient temperature to 125°C....................................................................................................................... 5
• Added Thermal Information table. .......................................................................................................................................... 5
• Added Typical Characteristics. .............................................................................................................................................. 7
l TEXAS INSTRUMENTS cmu: 1 a jjvcc CTRLEE ‘ 5 Even XOUTEE 2 7 jjoscom XOUTEE 2 7 33 OSCOUT X‘NEE a 5 13A 4 5 XIN CE 3 6 33A GNDEE 33" GND E: 4 5 33 Y GND xw XOUT CTRL OO 00 OO 00 oscouT Vcc See mechamca‘ drawmgs fior dlmenswons
B
1 2
D
A
C
3
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6 Pin Configuration and Functions
DCT Package
8-Pin SSOP
Top View
DCU Package
8-Pin VSSOP
Top View
YZP Package
8-Ball DSBGA
Bottom View
Drawings not to scale
Pin Functions
PIN NO. I/O DESCRIPTION
DCT/DCU YZP NAME
1 A1 CTRL I OSC Control
2 B1 XOUT O Crystal Connection Out
3 C1 XIN I Crystal Connection In
4 D1 GND — Ground
5 D2 Y O Schmitt Trigger Output
6 C2 A I Schmitt Trigger Input
7 B2 OSCOUT O Oscillator Output
8 A2 VCC — Power Supply
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VIInput voltage range(2) XIN, A, CTRL inputs –0.5 6.5 V
VOVoltage range applied to any output
in the high-impedance or power-off state(2) Y output –0.5 6.5 V
VOVoltage range applied to any output
in the high or low state(2)(3) XOUT, OSCOUT –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage Temperature Range -65 150 °C
TJJunction Temperature 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
MAX UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1) ±2000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2) ±1000
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(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) CTRL = Low, XIN = GND
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
Data retention only 1.5
VIInput voltage (XIN, CTRL, A inputs) 0 5.5 V
VOOutput voltage (XOUT, OSCOUT, Y outputs) 0 VCC V
IOH High-level output current (OSCOUT, XOUT, Y outputs)
VCC = 1.65 V –4
mA
VCC = 2.3 V –8
VCC = 3 V –16
–24
VCC = 4.5 V –32
IOL Low-level output current (OSCOUT, XOUT, Y outputs)
VCC = 1.65 V 4
mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
IOL(2) Low-level output current (XOUT) VCC = 1.65 V 2 mA
Δt/Δv Input transition rise and fall time (CTRL input)
VCC = 1.8 V ± 0.15 V 20
ns/V
VCC = 2.5 V ± 0.2 V 20
VCC = 3.3 V ± 0.3 V 10
VCC = 5 V ± 0.5 V 5
TAOperating free-air temperature DCU, DCT –40 125 °C
YZP –40 85
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.4 Thermal Information
THERMAL METRIC(1) DCT DCU YZP UNIT
8 PINS 8 PINS 8 BALLS
RθJA Junction-to-ambient thermal resistance 184.8 198.4 97.5
°C/W
RθJC(top) Junction-to-case (top) thermal resistance 115.3 73.5 1.1
RθJB Junction-to-board thermal resistance 97.3 77.1 26.3
ψJT Junction-to-top characterization parameter 40.9 6.1 0.5
ψJB Junction-to-board characterization parameter 96.3 76.7 26.2
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(1) All typical values are at VCC = 3.3 V, TA= 25°C.
(2) VIL = 0 V and VIH = VCC for XOUT and OSCOUT; the standard VT+ and VT– levels should be applied for the Y output.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VT+
Positive-
going
threshold
A input
1.65 V 0.79 1.16
V
2.3 V 1.11 1.56
3 V 1.5 1.87
4.5 V 2.16 2.74
5.5 V 2.61 3.33
VT–
Negative-
going
threshold
A input
1.65 V 0.39 0.62
V
2.3 V 0.58 0.87
3 V 0.84 1.14
4.5 V 1.41 1.79
5.5 V 1.87 2.29
ΔVT
hysteresis
(VT+ – VT– )A input
1.65 V 0.37 0.62
V
2.3 V 0.48 0.77
3 V 0.56 0.87
4.5 V 0.71 1.04
5.5 V 0.71 1.11
VOH(2)
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1
V
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
IOH = –16 mA 3 V 2.4
IOH = –24 mA 3 V 2.3
IOH = –32 mA 4.5 V 3.8
VOL(2)
IOL = 100 µA 1.65 V to 5.5 V 0.1
V
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
IOL = 16 mA 3 V 0.4
IOL = 24 mA 3 V 0.55
IOL = 32 mA 4.5 V 0.55
VOL XOUT IOL = 100 µA CTRL = Low, XIN = GND 1.65 V to 5.5 V 0.1 V
IOL = 2 mA 1.65 V 0.65
IIAll inputs VI= 5.5 V or GND 0 to 5.5 V ±5 µA
Ioff Y output VIor VO= 0 to 5.5 V 0 ±10 µA
ICC VI= VCC or GND, IO= 0 1.65 V to 5.5 V 10 µA
ΔICC CTRL and A
inputs One input at VCC – 0.6 V,
Other inputs at VCC or GND 3 V to 5.5 V 500 µA
Ci
CTRL and A
inputs VI= VCC or GND 3.3 V 3.5 pF
XIN 6
l TEXAS INSTRUMENTS
30
Gain − dBV
Frequency − MHz
100
20
10
0
−10
1010.1
VCC = 1.8 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 5 V
7
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7.6 Switching Characteristics, CL= 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tpd
A Y 2.8 15.1 1.6 5.7 1.5 4.6 0.9 4.4
nsXIN XOUT 1.7 9.6 1 3.2 1.1 2.4 0.9 1.8
OSCOUT 2.6 17.2 2 5.6 2 4.1 1.5 3.2
CTRL XOUT 3 28.2 1.8 14.4 1.5 12.2 1.1 10.2
7.7 Switching Characteristics, CL= 30 pF or 50 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
tpd
A Y 3 17.3 1.8 7.4 1.8 6.4 1 5.3
nsXIN XOUT 1.2 15.8 0.8 5.8 1 5.4 0.6 4.6
OSCOUT 3.5 25.7 2.6 7.1 2.8 7.8 2 6.7
CTRL XOUT 3.3 24.5 2.1 12 1.9 12.7 1.1 11.2
7.8 Operating Characteristics
TA= 25°C
PARAMETER TEST
CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V UNIT
TYP TYP TYP TYP
Cpd Power dissipation
capacitance f = 10 MHz 25 26 29 39 pF
7.9 Typical Characteristics
Figure 1 shows the open-loop-gain characteristics of the unbuffered inverter of the LVC1404 (that is, between XIN and
XOUT). The device provides a high gain over a wide range of frequencies. spacer
Figure 1. Open-Loop-Gain Characteristics
l TEXAS INSTRUMENTS From Outpul Under Test CL (see Note A) I OV suo LOAD cmcun v INPUTS 0° v. |,/ 1.3V :onv vcc sen 2.5 v :02 v van :2 n 3.3 v :03 v a v 52.5 5 v :05 v vcc 52.5 K7 4" Oulpul VOLTAGE WAVEFORMS PROPAGAHON DELAV TIMES NOTES. A cL mc‘udes pmbe and Hg capacnan a Wavemrm 1 ‘5 car an output mm mt Wavelorm 2 ‘5 car an output mm mt Imnmuo AH mput pmses are supphed by gen The outputs are measured me at a «M and «n+2 are the same as «ms. thL and 1m are the same as «an «M and «M are the same as ‘m A” parameters and wavelorms are
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH - V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VM
VMVM
VM
VM
VM
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 MΩ
1 MΩ
1 MΩ
1 MΩ
VCC
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS RL
(tPZ)
RL
(Except tPZ)
1 kΩ
1 kΩ
1 kΩ
1 kΩ
0 V
tw
Input
VOLTAGE WAVEFORMS
PULSE DURATION
VMVM
VI
8
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8 Parameter Measurement Information
Figure 2. Load Circuit and Voltage Waveforms
l TEXAS INSTRUMENTS 0 V s: O From Outpul i Under Test CL ,7 (see Mme A) ‘ LOAD CIRCUIT V IN on VI 1.3 v :an v V0‘: 2.5 v :02 v V0‘: 3.3 V :03 V 3 V 5 v :05 v v0C H7 «w 4H \ \ \ \ ‘ VOLTAGE WAVEFORMS PULSE DURATION ‘ \ \ ‘PLH H p—Dfi l \ Oulpul VOLTAGE WAVEFORMS PROPAGATION DELAV TIMES NOTES. A cL mc‘udes pmbe and Hg capacnan a Wavemrm 1 ‘s car an output mm m Wavelorm 2 ‘s car an oulpm mm m Imnmun AH mpm pmses are supphed by gen The oqums are measured me at a «M and IFHZ are me same as «ms. thL and 1m are me same as «an «M and «M are me same as (m A” parameters and wavelorms are
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
VLOAD
Open
GND
RL
RL
Data Input
Timing Input
VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH - V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
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Parameter Measurement Information (continued)
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LVC1404 device consists of one inverter with a Schmitt-trigger input and two unbuffered inverters. It is
designed for 1.65-V to 5.5-V VCC operation.
XIN and XOUT pins can be connected to a crystal or resonator in oscillator applications. The SN74LVC1404
device provides an additional unbuffered inverter (OSCOUT) and a Schmitt-trigger input inverter for signal
conditioning (see the Functional Block Diagram). The control (CTRL) input disables the oscillator circuit to reduce
power consumption. The oscillator circuit is disabled and the XOUT output is set to low level when CTRL is low.
To ensure the oscillator circuit remains disabled during power up or power down, CTRL should be connected to
GND through a pulldown resistor. The minimum value of the resistor is determined by the current-sourcing
capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
9.2 Functional Block Diagram
9.3 Feature Description
• Wide operating voltage range
– Operates from 1.65 V to 5.5 V
• Has buffered output and un-buffered output from oscillator
• Schmitt-trigger buffer
– Allows for extra buffering of the oscillator output
• Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
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9.4 Device Functional Modes
Table 1. Function Table
INPUTS OUTPUTS
CTRL XIN XOUT OSCOUT
H L H L
H H L H
L X L H
Table 2. Function Table
INPUT
AOUTPUT
Y
L H
H L
llllllllllllllll ||||||||||||||||
CTRL(1)
Rs≅1 kΩ
CL≅16 pF
C2≅32 pF
XOUT
XIN
OSCOUT
Y
A
Optional Signal-Conditioning Stage
CLOAD RLOAD
CLOAD
RF≅2.2 MΩ
C1≅32 pF
GND
1
2
3
45
6
7
8VCC
RLOAD
1 2
L
1 2
C C
C
C C
=
+
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10 Application and Implementation
10.1 Application Information
Figure 4 shows a typical application of the SN74LVC1404 device in a Pierce oscillator circuit. The output voltage
can be conditioned further by connecting OSCOUT to the Schmitt-trigger input inverter. The Schmitt-trigger input
inverter produces a rail-to-rail voltage waveform. The recommended load for the crystal, shown in this example,
is 16 pF. The value of the recommended load (CL) can be found in the crystal manufacturer's data sheet. Values
of C1and C2are chosen so that and C1≉C2. Rsis the current-limiting resistor, and the value
depends on the maximum power dissipation of the crystal. Generally, the recommended value of Rsis specified
in the crystal manufacturer's data sheet and, usually, this value is approximately equal to the reactance of C2at
resonance frequency, that is, RS= XC2. RFis the feedback resistor that is used to bias the inverter in the linear
region of operation. Usually, the value is chosen to be within 1 MΩto 10 MΩ.
10.2 Typical Application
Figure 4. Typical Application Diagram
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Typical Application (continued)
10.2.1 Design Requirements
• The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This decreases
the closed-loop gain of the oscillator circuit. The value of Rscan be decreased to increase the closed-loop
gain, while maintaining the power dissipation of the crystal within the maximum limit.
• Rsand C2form a low-pass filter and reduce spurious oscillations. Component values can be adjusted, based
on the desired cutoff frequency.
• C2can be increased over C1to increase the phase shift and help in start-up of the oscillator. Increasing C2
may affect the duty cycle of the output voltage.
• At high frequency, phase shift due to Rsbecomes significant. In this case, Rscan be replaced by a capacitor
to reduce the phase shift.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
10.2.2.1 Testing
After the selection of proper component values, the oscillator circuit should be tested, using these components,
to ensure that the oscillator circuit shows required performance over the recommended operating conditions.
• Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its
equivalent parallel-resonant resistance.
• When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the
circuit oscillates at the appropriate frequency at the lowest VCC and highest VCC.
• Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements.
l TEXAS INSTRUMENTS Time — ns
Time − ns
RS = 240 W
3.5
Output Voltage − V
0
3
2.5
2
1.5
1
0.5
0
−0.5
20 40 60 80
RS = 10 kW
RS = 2 kW
RS = 0
14
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Typical Application (continued)
10.2.3 Application Curves
10.2.3.1 LVC1404 in 25-MHz Crystal-Oscillator Circuit
C1≈C2= 30 pF (1)
XC2 = 200 Ω(capacitive reactance at resonance frequency, that is, 25 MHz) (2)
VCC = 3.3 V (3)
Figure 5. Effect of RSon Oscillator Waveform (Frequency = 25 MHz)
Table 3. Effect of RSon Duty Cycle and ICC
(Frequency = 25 MHz)
RS
(Ω)ICC
(mA) Positive Duty Cycle
(%)
0 22.2 43
240 11.1 45.9
2 k 7.3 47.3
10 k 8.6 46.7
l TEXAS INSTRUMENTS Time — ns Time » n5
RS = 10 kW
3.5
Output Voltage − V
0
3
2.5
2
1.5
1
0.5
0
200 400 600 800
RS = 2 kW
RS = 240 W
Time − ns
Time − ns
RS = 10 kW
3.5
Output Voltage − V
0
3
2.5
2
1.5
1
0.5
0
50 100 150 200
RS = 3 kW
RS = 450 W
15
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10.2.3.2 LVC1404 in 10-MHz Crystal-Oscillator Circuit
C1≈C2= 30 pF (4)
XC2 = 480 Ω(capacitive reactance at resonance frequency, that is, 10 MHz) (5)
VCC = 3.3 V (6)
Figure 6. Effect of RSon Oscillator Waveform (Frequency = 10 MHz)
Table 4. Effect of RSon Duty Cycle and ICC
(Frequency = 10 MHz)
RS
(Ω)ICC
(mA) Positive Duty Cycle
(%)
450 6.9 40
3 k 8.4 47.6
10 k 15.1 43.9
10.2.3.3 LVC1404 in 2-MHz Crystal-Oscillator Circuit
C1≈C2= 30 pF (7)
XC2 = 2.4 kΩ(capacitive reactance at resonance frequency, that is, 2 MHz) (8)
VCC = 3.3 V (9)
Figure 7. Effect of RSon Oscillator Waveform (Frequency = 2 MHz)
Table 5. Effect of RSon Duty Cycle and ICC
(Frequency = 2 MHz)
RS
(Ω)ICC
(mA) Positive Duty Cycle
(%)
240 11.1 45.9
2 k 7.3 47.3
10 k 8.6 46.7
l TEXAS INSTRUMENTS
RS = 220 kW
0
3
2.5
2
1.5
1
0.5
0
5 10 15 20
RS = 100 kW
RS = 50 kW
Output Voltage − V
Time − ms
3.5
16
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10.2.3.4 LVC1404 in 100-kHz Crystal-Oscillator Circuit
C1≈C2= 30 pF (10)
XC2 = 48 kΩ(capacitive reactance at resonance frequency, that is, 100 kHz) (11)
VCC = 3.3 V (12)
Figure 8. Effect of RSon Oscillator Waveform (Frequency = 100 kHz)
Table 6. Effect of RSon Duty Cycle and ICC
(Frequency = 100 kHz)
RS
(Ω)ICC
(mA) Positive Duty Cycle
(%)
50 k 9 46.4
100 k 9.5 46.1
220 k 13.7 44.3
l TEXAS INSTRUMENTS
Vcc
Unused Input
Input
Output
Input
Unused Input Output
17
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11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 9 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Figure 9. Layout Diagram
l TEXAS INSTRUMENTS
18
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13 Device and Documentation Support
13.1 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1404DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CA4
(R, Z)
SN74LVC1404DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CA4J, CA4R)
SN74LVC1404YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 44N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 29-Jan-2021
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pitch between SucCeSSWe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1404DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
SN74LVC1404DCTR SM8 DCT 8 3000 177.8 12.4 3.45 4.4 1.45 4.0 12.0 Q3
SN74LVC1404DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC1404DCUR VSSOP DCU 8 3000 178.0 9.0 2.25 3.35 1.05 4.0 8.0 Q3
SN74LVC1404YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2021
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1404DCTR SM8 DCT 8 3000 182.0 182.0 20.0
SN74LVC1404DCTR SM8 DCT 8 3000 183.0 183.0 20.0
SN74LVC1404DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74LVC1404DCUR VSSOP DCU 8 3000 180.0 180.0 18.0
SN74LVC1404YZPR DSBGA YZP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-May-2021
Pack Materials-Page 2
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
LAND PATTERN DATA DCU (S—PDSO—G8) PLASTIC SMALL OUTLINE PACKAGE (DH-Z DOWN) Example Board Layout (Nate 0,5) l ihi' 6x 0,5 I 3,1 ( 8% ‘\ / + 0,3 Exampie /Soider Mask Opening \ Pad Geometry Exampie Stencii Design (Nate D) 8x 0,25 —‘ |——‘ Er Eflfii- Bx 0,75 7 ‘|———'- 6x 0,5 HHH%- meow/c 04/12 NOTES: Au Pom .m Ali iinear dimensions are in miiiimeters‘ This drawing is subject to change without notice. Publication iPC—735I is recommended for aiternate designs. Laser cutting aperture5 with trupezoidai wails and also rounding corners wiil ciier better paste reiease. Customers should Contact their haard assembly site for stencii design recommendations. Refer to iFC—7525 for other slencii recommendations. Custamers shauid Contact their board fabrication site for saider mask toierances between and around signai pads. {I} Tums INSTRUMENTS www.li.com
www.ti.com
PACKAGE OUTLINE
C
4.25
3.75 TYP
1.3
1.0
6X 0.65
8X 0.30
0.15
2X
1.95
(0.15) TYP
0 - 8 0.1
0.0
0.25
GAGE PLANE
0.6
0.2
A
3.15
2.75
NOTE 3
B2.9
2.7
NOTE 4
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
18
0.13 C A B
5
4
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 3.500
J
www.ti.com
EXAMPLE BOARD LAYOUT
(3.8)
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
8X (1.1)
8X (0.4)
6X (0.65)
(R0.05)
TYP
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
1
45
8
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(3.8)
6X (0.65)
8X (0.4)
8X (1.1)
4220784/C 06/2021
SSOP - 1.3 mm max heightDCT0008A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
WT
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PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1.5
TYP
0.5 TYP
8X 0.25
0.21
0.5
TYP
B E A
D
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
D
SCALE 8.000
D: Max =
E: Max =
1.919 mm, Min =
0.918 mm, Min =
1.858 mm
0.857 mm
www.ti.com
EXAMPLE BOARD LAYOUT
8X ( 0.23) (0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
D
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
8X ( 0.25) (R0.05) TYP
METAL
TYP
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
D
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