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Texas Instruments 的 SN54LV161A, SN74LV161A 规格书
Support Mixed-Mode Voltage Operation on
All Ports
Internal Look-Ahead ior Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
SN54LV161A . . . FK P
lo" Supports Partial-Power—Down Mode (Top View)
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
o ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114—A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
i—u—u—u—u—u—u—u—i
|_l|_l|_l|_l|_il_l|_l|_l
i—ii—ii—ii—ii—i
descrip "on/ordering iniormation
The ’LV161A devices are 47bit synchronous
blnary counters deslgned for 27V to 5.5V V00
operation. NC , No internal eonne
ORDERING INFORMATION
u P223333; m:
Tube oi 40 SN74LV16|AD
sovc ' D Reel oi 25m SN74LV16|ADR we”
sop , NS Reel oi 2mm SN74LV161ANSR 74LVieiA
a o SSOP , DB Reel oi 2mm SN74LV161ADBR LVIElA
'40 C m 85 0 Tube oi 90 SN74LV161APW
TSSOF , PW Reel oi 2mm SN74LV161APWR LV161A
Reel oi 250 SN74LV161APWT
TVSOF , DGV Reel oi 2mm SN74LV161ADGVR LVIElA
cow , J Tube oi 25 SNJSALVlGlAJ SNJSALVI
75500 io 125QC CFP , w Tube oi isu SNJSALVlGlAW SNJSALVI
LCCC , FK Tube oi 55 SNJSALVl ei AFK SNJSALVI
T Package drawings standard packing quantities, thermal daia symbolization, and PCB design gul
are available at www ti.com/sc/package,
Please be aware ihai an important notice concerning avallablllty, standard warranty, and use
Texas lnsiruments semiconductor producLs and disclaimers thereto appears at me end oi this data sh
Copyright c 2005,
mln| cunlnmx Pianucllmi
uiiizss miiuwis: uarEn .m.
M" “f""m" 5:215? El $15123." 1:333:31 5”"?11‘“ I
emu ”3am"! in. mn ”some, mm. min! .4 in TEXAS
Wm. I
NSTRUMENTS
POST omcz aox 555303 - DALLAS rExAs 752s5
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 5.5-V VCC Operation
DMax tpd of 9.5 ns at 5 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DSupport Mixed-Mode Voltage Operation on
All Ports
DInternal Look-Ahead for Fast Counting
DCarry Output for n-Bit Cascading
DSynchronous Counting
DSynchronously Programmable
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’LV161A devices are 4-bit synchronous
binary counters designed for 2-V to 5.5-V VCC
operation.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
SOIC − D
Tube of 40 SN74LV161AD
LV161A
SOIC − D Reel of 2500 SN74LV161ADR LV161A
SOP − NS Reel of 2000 SN74LV161ANSR 74LV161A
−40°C to 85°C
SSOP − DB Reel of 2000 SN74LV161ADBR LV161A
−40°C to 85°CTube of 90 SN74LV161APW
TSSOP − PW Reel of 2000 SN74LV161APWR LV161A
TSSOP − PW
Reel of 250 SN74LV161APWT
LV161A
TVSOP − DGV Reel of 2000 SN74LV161ADGVR LV161A
CDIP − J Tube of 25 SNJ54LV161AJ SNJ54LV161AJ
−55°C to 125°CCFP − W Tube of 150 SNJ54LV161AW SNJ54LV161AW
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54LV161AFK SNJ54LV161AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV161A ...J OR W PACKAGE
SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV161A . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
QA
QB
NC
QC
QD
A
B
NC
C
D
CLK
CLR
NC
LOAD
ENT RCO
ENP
GND
NC VCC
‘4‘ TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the
outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and
internal gating. This mode of operation eliminates the output counting spikes that normally are associated with
synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising
(positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four
of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS OUTPUTS
FUNCTION
CLR LOAD ENP ENT CLK QA QB QC QD FUNCTION
L X X X X L L L L Reset to “0”
HLXX↑AB C D Preset Data
HHXL↑No Change No Count
HHLX↑No Change No Count
HHHH↑Count up Count
H X X X ↑No Change No Count
LOAD
ENT
ENP
64
3D
4R
M1
(:2
1, 27/1123
(:4
an
AR
M1
(:2
T, 2mm
(:4
an
AR
M1
(:2
1, 27/1123
(:4
an
AR
[>09
T Fars1mphc1ty,mutmg cm complementary s1gna\s E and H15 m1 Shawn on m were“ huge d1agram, The uses 01 these Signals are shown
on the huge d1agram a1 me D/T mumps.
Pm numbers Shawn are W the D DB, Dev, J NS PW1and w packages.
‘4‘ TEXAS
INSTRUMENTS
9051 omca aox 555303 - DALLAS IEXAS 752s5
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
†For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
M1
G2
G4
3D
4R
1, 2T/1C3
4
13
B
QB
M1
G2
G4
3D
4R
1, 2T/1C3
5
12
C
QC
M1
G2
G4
3D
4R
1, 2T/1C3
6
11
D
QD
M1
G2
G4
3D
4R
1, 2T/1C3
2
LD†
CK†
CK
R
LD
LD (Load) 7 M1
TE (Toggle Enable)
CK (Clock) 4:
‘9 TEXAS
INSTRUMENTS
4 p057 OFFICE aox $553133 - DALLAS IE
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1LD (Load)
Q (Output)
G2TE (Toggle Enable)
CK (Clock)
G4
3D
4R
1, 2T/1C3
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD†
LD†
D
R
CK†
CK†
CK†
CK†
Q
†The origins of LD and CK are shown in the overall logic diagram of the device.
|_________________________
|_________________________
l—————————————————————————
'_________________________
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SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
A
Data
Inputs
Data
Outputs
CLR
LOAD
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear Preset
Count Inhibit
12 13 14 15 0 1 2
‘9 TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in high or low state, VO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . .
Voltage range applied to any output in the power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
mpm transmon nse or can ra‘e
‘4‘ TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.7 VCC ×0.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V VCC ×0.7 VCC ×0.7 V
VCC = 4.5 V to 5.5 V VCC ×0.7 VCC ×0.7
VCC = 2 V 0.5 0.5
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.3 VCC ×0.3
V
VIL Low-level input voltage VCC = 3 V to 3.6 V VCC ×0.3 VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3 VCC ×0.3
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 µA
IOH
High-level output current
VCC = 2.3 V to 2.7 V −2 −2
IOH High-level output current VCC = 3 V to 3.6 V −6 −6 mA
VCC = 4.5 V to 5.5 V −12 −12
mA
VCC = 2 V 50 50 µA
IOL
Low-level output current
VCC = 2.3 V to 2.7 V 2 2
IOL Low-level output current VCC = 3 V to 3.6 V 6 6 mA
VCC = 4.5 V to 5.5 V 12 12
mA
VCC = 2.3 V to 2.7 V 0 200 0 200
∆t/∆vInput transition rise or fall rate VCC = 3 V to 3.6 V 0 100 0 100 ns/V
∆t/∆v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 0 20 0 20
ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV161A SN74LV161A
UNIT
PARAMETER
TEST CONDITIONS
VCC MIN TYP MAX MIN TYP MAX
UNIT
IOH = −50 µA2 V to 5.5 V VCC−0.1 VCC−0.1
VOH
IOH = −2 mA 2.3 V 2 2
V
VOH IOH = −6 mA 3 V 2.48 2.48 V
IOH = −12 mA 4.5 V 3.8 3.8
IOL = 50 µA2 V to 5.5 V 0.1 0.1
VOL
IOL = 2 mA 2.3 V 0.4 0.4
V
VOL IOL = 6 mA 3 V 0.44 0.44 V
IOL = 12 mA 4.5 V 0.55 0.55
IIVI = 5.5 V or GND 0 to 5.5 V ±1±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 20 µA
Ioff VI or VO = 0 to 5.5 V 0 5 5 µA
CiVI = VCC or GND 3.3 V 1.8 1.8 pF
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‘4‘ TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ±0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
tw
Pulse duration
CLK high or low 7 7 7
ns
twPulse duration CLR low 7 7 7 ns
CLR 4.5 4.5 4.5
tsu
Setup time before CLK↑
Data (A, B, C, and D) 7.5 8.5 8.5
ns
tsu Setup time before CLK↑ENP, ENT 9.5 11 11 ns
LOAD low 10 11.5 11.5
thHold time, all synchronous inputs after CLK↑1.5 1.5 1.5 ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
tw
Pulse duration
CLK high or low 5 5 5
ns
twPulse duration CLR low 5 5 5 ns
CLR 2.5 2.5 2.5
tsu
Setup time before CLK↑
Data (A, B, C, and D) 5.5 6.5 6.5
ns
tsu Setup time before CLK↑ENP, ENT 7.5 9 9 ns
LOAD low 8 9.5 9.5
thHold time, all synchronous inputs after CLK↑1 1 1 ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV161A SN74LV161A
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
tw
Pulse duration
CLK high or low 5 5 5
ns
twPulse duration CLR low 5 5 5 ns
CLR 1.5 1.5 1.5
tsu
Setup time before CLK↑
Data (A, B, C, and D) 4.5 4.5 4.5
ns
tsu Setup time before CLK↑ENP, ENT 5 6 6 ns
LOAD low 5 6 6
thHold time, all synchronous inputs after CLK↑1 1 1 ns
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‘4‘ TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54LV161A SN74LV161A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF 50* 125* 40* 40
MHz
fmax CL = 50 pF 30 95 25 25 MHz
Q7.9* 16.2* 1* 19.5* 1 19.5
tpd
CLK RCO
(count mode) 8.9* 17* 1* 20.5* 1 20.5
tpd
CLK
RCO
(preset mode) CL = 15 pF 11.9* 20.6* 1* 24.5* 1 24.5 ns
ENT RCO
L
8.3* 15.7* 1* 19* 1 19
tPHL
CLR
Q8.8* 17* 1* 20.5* 1 20.5
tPHL CLR RCO 9.8* 16.6* 1* 20* 1 20
Q10.5 19.2 1 22.5 1 22.5
tpd
CLK RCO
(count mode) 11.7 20 1 23.5 1 23.5
tpd
CLK
RCO
(preset mode) CL = 50 pF 14.5 23.6 1 27.5 1 27.5 ns
ENT RCO
L
11 18.7 1 22 1 22
tPHL
CLR
Q11.4 20 1 23.5 1 23.5
t
PHL
CLR
RCO 12.6 19.6 1 23 1 23
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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‘4‘ TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54LV161A SN74LV161A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF* 80* 165* 70* 70
MHz
fmax CL = 50 pF 55 125 50 50 MHz
Q6 12.8 1* 15* 1 15
tpd*
CLK RCO
(count mode) 6.7 13.6 1* 16* 1 16
tpd*
CLK
RCO
(preset mode) CL = 15 pF 8.6 17.2 1* 20* 1 20 ns
ENT RCO
L
6.2 12.3 1* 14.5* 1 14.5
tPHL*
CLR
Q6.5 13.6 1* 16* 1 16
tPHL*CLR RCO 7.2 13.2 1* 15.5* 1 15.5
Q7.8 16.3 1 18.5 1 18.5
tpd
CLK RCO
(count mode) 8.7 17.1 1 19.5 1 19.5
tpd
CLK
RCO
(preset mode) CL = 50 pF 10.6 20.7 1 23.5 1 23.5 ns
ENT RCO
L
8.3 15.8 1 18 1 18
tPHL
CLR
Q8.4 17.1 1 19.5 1 19.5
t
PHL
CLR
RCO 9.2 16.7 1 19 1 19
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
Owe! ompm, maxxmum dynamwc VOL
Owe! ompm, mmmum dynamic VOL
Owe! ompm, mmmum dynamic VQH
Vcc
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‘4‘ TEXAS
INSTRUMENTS
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C SN54LV161A SN74LV161A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
CL = 15 pF 135* 220 115* 115
MHz
fmax CL = 50 pF 95 165 85 85 MHz
Q4.5* 8.1* 1* 9.5* 1 9.5
tpd
CLK RCO
(count mode) 5.1* 8.1* 1* 9.5* 1 9.5
tpd
CLK
RCO
(preset mode) CL = 15 pF 6.3* 10.3* 1* 12* 1 12 ns
ENT RCO
L
4.8* 8.1* 1* 9.5* 1 9.5
tPHL
CLR
Q4.9* 9* 1* 10.5* 1 10.5
tPHL CLR RCO 5.5* 8.6* 1* 10* 1 10
Q5.9 10.1 1 11.5 1 11.5
tpd
CLK RCO
(count mode) 6.6 10.1 1 11.5 1 11.5
tpd
CLK
RCO
(preset mode) CL = 50 pF 7.8 12.3 1 14 1 14 ns
ENT RCO
L
6.1 10.1 1 11.5 1 11.5
tPHL
CLR
Q6.3 11 1 12.5 1 12.5
t
PHL
CLR
RCO 6.9 10.6 1 12 1 12
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER
SN74LV161A
UNIT
PARAMETER
MIN TYP MAX
UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V
VOL(V) Quiet output, minimum dynamic VOL −0.2 −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
3.3 V 23.6
pF
C
pd
Power dissipation capacitance
C
L
= 50 pF,
f = 10 MHz
5 V 25.8
pF
& & $'("%$ $#($ )(! $ # '("%1# (
#0$ )%# ' #1#+)"#$, %(%#( %% %$ #(
)#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(1# # (0
%$0# ( $$!# ## )(! .! $#,
From Output
T Under Test
CL 7 cL
(see Note A) A (see Note A) I
0
Open Drain vcc
SI 0
IPLZIIPZL VGc
IPHZIIPZH GND
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
H7 lw 4H
I I
I I VCC
Input 50% Vcc
0 v
VOLTAGE WAVEFORMS
PULSE DURATION
fl: vac
Input
‘ a v
I
lpLH H H—Pk IPHL
I t 7 T T VOH
In-Phase I 50% V06 50% Van
Output I V
‘ I OL
IPHL H H—Dti IPLH
I
VOH
Out-oI-Phase a I 5
Output SIvan/ever; {so/svcvc
T T T 0L
VOLTAGE WAVEFORMS
PROPAGATION nELAv TIMES
INVEHTING AND NONINVERTING OUTPUTS
NOTES. A. CLIncIudeSpmbe and no capacIlance.
, 7 7 , Vcc
Timing Input
I a v
tsu 44—» I
I 777777 Vcc
Data Input
0 v
VOLTAGE WAVEFOHMS
SETUP AND HOLD TIMES
I I
IPZL»I f +I ‘WIPLZ
Output :Vcc
Waveform 1 I
Slathc I 7777 0L
(see Note B) I
IPZHM ‘W +I ‘rlPHz
Output 7 7 7 7
Wavetorm 2 50% V V0"
S1 at GND CC :0 V
(see Note B)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
a. Wavelorm t is tor an output wIIh IrIIernaI conditIDns suoh that the output is Iow‘ except when dIsabIed by the output ccntroI.
WaveIOrm 2 is tor an output wth Internal condItIOnS such that the output is hIgh, excepI when dISabIed by the output controt.
tpLz ano tpHZ are the same as Idis.
IPZL ano tPZH are the same as Ian
tpHL and lpLH are the same as Ipd
IQFWPO
AII input puIses are supplIed by generators having the IctIlctwing characteristics. PRR 9 MHz, 20 e 50 n t, g 3 ns t. g 3 ns,
The outputs are measured one at a time, with one Input transition per measurement
AII parameters ano wavetorms are not apphcapIe tc aII oevices.
‘9 TEXAS
INSTRUMENTS
12 POST OFFICE on $55303 U DALLAS. IEXAS 75285
SCLS404F − APRIL 1998 − REVISED DECEMBER 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
I TEXAS
INSTRUMENTS
Samples
Samples
Samples
Samples
Samples
Sample:
Sample:
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LV161AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161ADBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161ADGVR ACTIVE TVSOP DGV 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161ANSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 74LV161A
SN74LV161APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161APWRE4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
SN74LV161APWT ACTIVE TSSOP PW 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV161A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
I TEXAS
INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS
INSTRUMENTS
REEL DIMENSIONS TAPE DIMENSIONS
7 “K0 '«Pt»
Reel
Dlameter
AD Dimension designed to accommodate the component Width
ED Dimension designed to accommodate the component iengtn
K0 Dimension designed to accommodate the component Ihlckness
7 W OveraH wtdlh loe Gamer tape
i P1 Pitch between successive cavtty centers
f
T Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
O O O D O O D D SprocketHotes
,,,,,,,,,,, ‘
User Direcllon 0' Feed
Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV161ADBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LV161ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LV161ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LV161ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LV161APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LV161APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jul-2021
Pack Materials-Page 1
l TEXAS
INSTRUMENTS
TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV161ADBR SSOP DB 16 2000 853.0 449.0 35.0
SN74LV161ADGVR TVSOP DGV 16 2000 853.0 449.0 35.0
SN74LV161ADR SOIC D 16 2500 340.5 336.1 32.0
SN74LV161ANSR SO NS 16 2000 853.0 449.0 35.0
SN74LV161APWR TSSOP PW 16 2000 853.0 449.0 35.0
SN74LV161APWT TSSOP PW 16 250 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Jul-2021
Pack Materials-Page 2
MECHANICAL DATA
D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥
4040047 S/M 06/1‘
NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5>
B Th5 drawer ‘5 subje», ,0 change mm: Home,
A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘
nm exceed 3005 (015) eam swce
@ Body mm does 101 meme 11mm fish.
E Rdererce JEDEC MS 012 mam Ac,
nter‘ec: flash sfu‘ not exceed 0017 (043) each swde
{if TEXAS
INSTRUMENTS
www.1i.com
LAND PATTERN DATA
D (RiPDSOiGiB) PLASTiC SMALL OUTLINE
stencil Openings
Example
Pod Geometry
(See Note c)
Non Soidermosk Detirled Pad
alir 4x1, 27 i 16X0'55ai ‘+l4xi 27
mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T
@E-HnH-a-a— {downgrade
r,
Example
Snider Mask 0 erlin
l /l/ i a
i 0 07 It (See Note E)
All Around ,'
421i233e4/E oa/iz
AH linear dimensions are in millimeters
This drawing is subject ta anange without notice.
Publication che7351 is recommended tar alternate designs.
Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release
contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations
Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods
NOTES:
Customers should
POE”?
r"
{I} Tums
INSTRUMENTS
www.li.com
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500
v¢\‘\‘\‘\+““‘
gimm—LE—urmm M i
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
YL““‘+““‘
fimmamfl
J
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
MECHANICAL DATA
NS (R-PDSO-G") PLASTIC SMALL—OUTLINE PACKAGE
14-PINS SHOWN
HHFHHFH
j j t t H H j,
A
jfi/—\ %
lgLLLLLiLLL/fiif
A MAX 1060 1060 1290 1530
A MW 990 9,90 1230 14‘70
4040062/0 03/03
VOTES: A. AH Hneur dimenswons are m mHHmetevs
a, Tm: druwmg 5 subject to change wmom name.
0 Body dwmenswons do not mamas mom flash 0v pmtmswom not to exceed 0,15
INSTRUMEN'IS
www.li.m
0.16 NOM
17
i Gage Plane
0,15
7|,20MAX 0,?
PINS N 14 1s 20 24 as 43 56
DIM
AMAX 3‘70 3.70 5‘10 5.10 700 9,00 11,40
AMIN 350 3,50 400 4,90 7‘70 9,50 11,20
407325| /E 03/00
*5 TEXAS
INSTRUMENTS
p057 omca aox $55303 - DALLAS IEXAS 752s5
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
oo
A‘ioyi
55
fiHHHHHHHHHHHHfi
{'3 TEXAS
INSTRUMENTS
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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