Texas Instruments 的 UCC28061 规格书

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UCC28060
1
NATURAL INTERLEAVING FEATURES SYSTEM FEATURES
APPLICATIONS
+–
COMP
VREF
PGND
AGND
VCC ZCDA
ZCDB
GDA
CS
GDB
VINAC
VSENSE
PWMCNTL
UCC28061
TSET
PHB
HVSEN
EMI
Filter
400VDC
PowerGoodto
downstreamconverter
85-265VAC
InputVoltage(V)
5
4
3
2
1
70 120 170 220 270
CapacitorRippleCurrent(A)
P =600W
V =400V
OUT
OUT
1-PhaseTM
2-PhaseTMInterleave
1-PhaseCCM
UCC28061
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Natural Interleaving™ Transition-Mode PFC Controller With Improved Audible NoiseImmunity
•Improved Audible Noise Performance23
•Phase Management Capability
•Soft Start on Overvoltage•FailSafe OVP with Dual Paths Prevents Output
•Integrated BrownoutOver-Voltage Conditions Caused byVoltage-Sensing Failures
•Improved Efficiency and Design Flexibilityover Traditional, Single-Phase Continuous•Sensorless Current Shaping Simplifies Board
Conduction Mode (CCM)Layout and Improves Efficiency
•Input Filter and Output Capacitor Current•Inrush Safe Current Limiting:
Cancellation:– Prevents MOSFET conduction during
– Reduced current ripple for higher systeminrush
reliability and smaller bulk capacitor– Eliminates reverse recovery events in
– Reduced EMI filter sizeoutput rectifiers
•Enables Use of Low-Cost Diodes withoutExtensive Snubber Circuitry•Improved Light-Load Efficiency•Improved Transient Response•Complete System-Level Protection•1-A Source/1.8-A Sink Gate Drivers
•100-W to 800-W Power Supplies•Gaming
•D to A Set Top Boxes•Adapters
•LCD, Plasma and DLP™ TVs•Home Audio Systems
Typical Application Circuit
Ripple Current Reduction
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DLP is a trademark of Texas Instruments.
3Natural Interleaving is a trademark of Texas Instuments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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CONTENTS
DESCRIPTION
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
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•Ordering Information 2•Electrical Characteristics 4•Device Information 7•Functional Block Diagram 9•Typical Characteristics 10•Application Information 16•Design Example 22•Additional References 29
Optimized for consumer applications concerned with audible noise elimination, this solution extends theadvantages of transition mode — high efficiency with low-cost components — to higher power ratings thanpreviously possible. By utilizing a Natural Interleaving technique, both channels operate as masters (that is, thereis no slave channel) synchronized to the same frequency. This approach delivers inherently strong matching,faster responses, and ensures that each channel operates in transition mode.
Complete system-level protections feature input brownout, output over-voltage, open-loop, overload, soft-start,phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection (OVP) featureprotects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic device failure.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PART NUMBER PACKAGE
(2)
OPERATING TEMPERATURE RANGE, T
A
UCC28061D SOIC 16-Pin (D) – 40 ° C to +125 ° C
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) SOIC (D) package is available taped and reeled by adding Rto the above part number. Reeled quantities for UCC28061DR are 2500devices per reel.
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ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
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All voltages are with respect to GND, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
UCC28061 UNIT
VCC
(2)
– 0.5 to +21
PWMCNTL – 0.5 to +20Input voltage range VCOMP
(3)
, CS, PHB, HVSEN
(4)
, VINAC
(4)
, VSENSE
(4)
– 0.5 to +7
ZCDA, ZCDB – 0.5 to +4
Continuous input current VCC 20
Input current PWMCNTL 10
Input current range ZCDA, ZCDB, VSENSE – 5 to +5 mA
Output current VREF – 10
Continuous gate current GDA, GDB
(5)
± 25
Operating – 40 to +125Junction temperature, T
J
Storage – 65 to +150 ° C
Lead temperature, T
SOL
Soldering, 10s +260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other condition beyond those included under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.(2) Voltage on VCC is internally clamped. VCC may exceed the absolute maximum input voltage if the source is current limited below theabsolute maximum continuous VCC input current level.(3) In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.(4) In normal use, VINAC, VSENSE, and HVSEN are connected to resistors and are internally limited in voltage swing. Although notrecommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as ± 10 mA from high voltagesources.
(5) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required todamp ringing due to stray inductance. See Figure 12 and Figure 13 for details.
THERMAL IMPEDANCEPACKAGE JUNCTION-TO-AMBIENT T
A
= +25 ° C POWER RATING T
A
= +85 ° C POWER RATING
SOIC 16-Pin (D) 140 ° C/W
(1)
890 mW
(1)
460 mW
(1)
(1) Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermalresistance. This number is only a general guide; see TI document SPRA953 device Thermal Metrics.
All voltages are with respect to GND, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
MIN MAX UNIT
VCC input voltage from a low-impedance source 14 21 V
VCC input current from a high-impedance source 8 18
mAVREF load current 0 – 2
VINAC Input voltage 0 6 V
ZCDA, ZCDB series resistor 20 80
kΩTSET resistor to program PWM on-time 66.5 400
HVSEN input voltage 0.8 4.5 V
PWMCNTL pull-up resistor to VREF 1 10 k Ω
RATING UNIT
Human body model (HBM) 2000 V
Charged device model (CDM) 500 V
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ELECTRICAL CHARACTERISTICS
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At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out ofthe specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC BIAS SUPPLY
VCC
(shunt)
VCC shunt voltage
(1)
I
VCC
= 10 mA 22 24 26 V
I
VCC(stby)
VCC current, disabled VSENSE = 0 V 100 200 µA
I
VCC(on)
VCC current, enabled VSENSE = 6 V 5 8 mA
UNDERVOLTAGE LOCKOUT (UVLO)
VCC
(on)
VCC turn-on threshold 11.5 12.6 13.5
VCC
(off)
VCC turn-off threshold 9.5 10.35 11.5 V
UVLO Hysteresis 1.85 2.25 2.65
REFERENCE
V
REF
VREF output voltage, no load I
VREF
= 0 mA 5.82 6.00 6.18 V
VREF change with load 0 mA ≤I
VREF
≤– 2 mA 1 6
mVVREF change with VCC 12 V ≤VCC ≤20 V 1 10
ERROR AMPLIFIER
VSENSE input regulation voltage T
A
= +25 ° C 5.85 6.00 6.15
VVSENSE input regulation voltage 5.82 6.00 6.18
VSENSE input bias current In regulation 125 300 800 nA
COMP high voltage, clamped VSENSE = 5.8 V 4.70 4.95 5.10
VCOMP low voltage, saturated VSENSE = 6.2 V 0.03 0.125
COMP = 3 V,g
m
VSENSE to COMP transconductance 75 96 110 µS5.94 V < VSENSE < 6.06 V
COMP source current, overdriven VSENSE = 5 V, COMP = 3 V – 120 – 160 – 190
µACOMP sink current VSENSE = 6.2 V, COMP = 3 V 7 20 32
VSENSE threshold for COMP offset enable, down
Voltage below V
REF
135 185 235 mVfrom V
REF
V
OVP
VSENSE over-voltage threshold, rising 6.25 6.45 6.7
VSENSE over-voltage hysteresis 0.1 0.2 0.4
VVSENSE enable threshold, rising 1.15 1.25 1.35
VSENSE enable hysteresis 0.02 0.05 0.2
OUTPUT MONITORING
V
PWMCNTL
HVSEN threshold to PWMCNTL HVSEN rising 2.35 2.50 2.65 V
HVSEN input bias current, high HVSEN = 3 V – 0.5 0.5
µAHVSEN input bias current, low HVSEN = 2 V 28 36 41
HVSEN rising threshold to over-voltage fault 4.64 4.87 5.1
VHVSEN falling threshold to over-voltage fault 4.45 4.67 4.80
PHB = 5 V,Phase Fail filter time to PWMCNTL high 8 12 20 msZCDA switching, ZCDB = 0.5 V
PWMCNTL leakage current high HVSEN = 2 V, PWMCNTL = 15 V – 1 1 µA
PWMCNTL output voltage low HVSENS = 3 V, IPWMCNTL = 5 mA 0.2 0.5 V
(1) Excessive VCC input voltage and current will damage the device. This clamp does not protect the device from an unregulated supply. Ifan unregulated supply is used, a Fixed Positive Voltage Regulator such as the UA78L15A is recommended. See the Absolute MaximumRatings table for the limits on VCC voltage and current.
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ELECTRICAL CHARACTERISTICS (continued)At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out ofthe specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GATE DRIVE
(2)
GDA, GDB output voltage high I
GDA
, I
GDB
= – 100 mA 11.5 13 15
GDA, GDB output voltage high, clamped VCC = 20 V, I
GDA
, I
GDB
= – 5 mA 12 13.5 15 V
GDA, GDB output voltage high, low VCC VCC = 12 V, I
GDA
, I
GDB
= – 5 mA 10 10.5 11.5
GDA, GDB on-resistance high I
GDA
, I
GDB
= – 100 mA 8 14 Ω
GDA, GDB output voltage low I
GDA
, I
GDB
= 100 mA 0.15 0.3 V
GDA, GDB on-resistance low I
GDA
, I
GDB
= 100 mA 2 3 Ω
Rise time 1 V to 9 V, C
LOAD
= 1 nF 18 30
nsFall time 9 V to 1 V, C
LOAD
= 1 nF 12 25
GDA, GDB output voltage UV I
GDA
, I
GDB
= 2.5 mA 1.6 2 V
ZERO CURRENT DETECTOR
ZCDA, ZCDB voltage threshold, falling 0.8 1.0 1.2
ZCDA, ZCDB voltage threshold, rising 1.5 1.68 1.88 V
ZCDA, ZCDB clamp, high I
ZCDA
= +2 mA, I
ZCDB
= +2 mA 2.6 3.0 3.4
ZCDA, ZCDB input bias current ZCDA = 1.4 V, ZCDB = 1.4 V – 0.5 0.5 µA
ZCDA, ZCDB clamp, low I
ZCDA
= – 2 mA, I
ZCDB
= – 2 mA – 0.4 – 0.2 0 V
Respective gate drive output rising 10%ZCDA, ZCDB delay to GDA, GDB outputs
(2)
45 100 nsfrom zero crossing input falling to 1 V
CURRENT SENSE
CS input bias current At rising threshold – 150 – 250 µA
CS current limit rising threshold – 0.18 – 0.20 – 0.22
VCS current limit falling threshold – 0.005 – 0.015 – 0.029
From CS exceeding threshold – 0.05 V toCS current limit response time
(2)
60 100 nsGDx dropping 10%
MAINS INPUT
VINAC input bias current VINAC = 2 V – 0.5 0.5 µA
BROWNOUT
VINAC brownout threshold VINAC falling 1.34 1.39 1.44 V
VINAC brownout current VINAC = 1 V 5 7 9 µA
VINAC fails to exceed the brownoutVINAC brownout filter time 340 440 540 msthreshold for the brownout filter time
(2) Refer to Figure 12 ,Figure 13 ,Figure 14 , and Figure 15 in the Typical Characteristics for typical gate drive waveforms.
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ELECTRICAL CHARACTERISTICS (continued)At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, – 40 ° C < T
J
= T
A
< +125 ° C, and currents are positive into and negative out ofthe specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PULSE-WIDTH MODULATOR
K
TL
On-time factor, phases A and B VINAC = 3.2 V, VSENSE = 5.8 V
(3)
3.6 4.0 4.4
µs/VVINAC = 3.2 V, VSENSE = 5.8 V,K
TLS
On-time factor, single-phase, A 7.2 8 8.9PHB = 0 V
(3)
Phase B to phase A on-time matching VSENSE = 5.8 V, VINAC = 3.2 V – 6% 6%
COMP = 0.25 V, VINAC = 1 V 1.2 2 2.7Zero-crossing distortion correction additional on
µstime
COMP = 0.25 V, VINAC = 0.1 V 12.6 20 29
PHB threshold falling, to single-phase operation To GDB output shutdown VINAC = 1.5 V 0.7 0.8 0.9
VPHB threshold rising, to two-phase operation To GDB output running VINAC = 1.5 V 0.9 1.0 1.1
T
(min)
Minimum switching period R
TSET
= 133 k Ω
(3)
1.7 2.2 2.5
µsPWM restart time ZCDA = ZCDB = 2 V
(4)
165 200 265
THERMAL SHUTDOWN
Thermal shutdown temperature T
J
, temperature rising
(5)
+160
° CThermal restart temperature T
J
, temperature falling
(5)
+140
(3) Gate drive on-time is proportional to V
COMP
– 125 mV. The on-time proportionality factor, K
T
, is different in two-phase and single-phasemodes. The on-time factor, K
T
, scales linearly with the value of R
TSET
. The minimum switching period is proportional to R
TSET
.(4) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restarttime. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.(5) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operatingtemperature is not specified or assured.
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DEVICE INFORMATION
ZCDA
VREF
GDA
PGND
VCC
GDB
CS
PWMCNTL
ZCDB
VSENSE
TSET
PHB
COMP
AGND
VINAC
HVSEN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
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UCC28061D
SOIC 16-Pin (D)Top View
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTIONNAME NO. I/O
Analog ground: Connect analog signal bypass capacitors, compensation components, and analogAGND 6 — signal returns to this pin. Connect the analog and power grounds at a single point to isolate high-currentnoise signals of the power components from interference with the low-current analog circuits.
Error amplifier output: The error amplifier is a transconductance amplifier, so this output is ahigh-impedance current source. Connect voltage regulation loop compensation components from thispin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minusan offset of approximately 125 mV. During soft-start events (undervoltage, brownout, disable or outputCOMP 5 O
over voltage), COMP is pulled low. Normal operation only resumes after the soft-start event clears andCOMP has been discharged below 0.5 V, making sure that the circuit restarts with a low COMP voltageand a short on-time. Do not connect COMP to a low-impedance source that would interfere with COMPfalling below 0.5 V.
Current sense input: Connect the current sense resistor and the negative terminal of the diode bridgeto this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. Asinput current increases, the voltage on CS goes more negative. This cycle-by-cycle over-currentprotection limits input current by turning off both gate driver (GDx) outputs when CS is more negativethan the CS rising threshold (approximately – 200 mV). The GD outputs remain low until CS falls to theCS 10 I CS falling threshold (approximately – 15 mV). Current sense is blanked for approximately 100 nsfollowing the falling edge of either GD output. This blanking filters noise that occurs when currentswitches from a power FET to a boost diode. In most cases, no additional current sense filtering isrequired. If filtering is required, the filter series resistance must be under 100 Ωto maintain accuracy. Toprevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensingresistor to the CS pin through a low value external resistor.
GDA 14 O Channel A and channel B gate drive output: Connect these pins to the gate of the power FET foreach phase through the shortest connection practical. If it is necessary to use a trace longer than 0.5inch (12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringingGDB 11 O
can be reduced by adding a 5- Ωto 10- Ωresistor in series with GDA and GDB.
High voltage output sense: The UCC28061 incorporates FailSafe OVP so that any single failure doesnot allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE andHVSEN and shuts down the PWM if either pin exceeds the appropriate over-voltage threshold. Usingtwo pins to monitor for over-voltage provides redundant protection and fault tolerance. HVSEN can alsobe used to enable a downstream power converter when the voltage on HVSEN is within the operatingHVSEN 8 I
region. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Selectthe HVSEN divider impedance for the desired power-good hysteresis. During operation, HVSEN mustnever fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28061 into a special test mode, usedonly for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise andprevent false over-voltage shutdown.
Power ground for the integrated circuit: Connect this pin to AGND through a separate short trace toPGND 13 —
isolate gate driver noise from analog signals.
Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time forchannel A is immediately doubled when channel B is disabled, which helps to keep COMP voltagePHB 4 I constant during the phase management transient. The PHB pin allows the user to add external phasemanagement circuitry if they desire. To disable phase management, connect the PHB pin to the VREFpin.
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TERMINAL FUNCTIONS (continued)
TERMINAL
DESCRIPTIONNAME NO. I/O
PWM enable logic output: This open-drain output goes low when HVSEN is within the HVSEN goodPWMCNTL 9 O region and the ZCDA and ZCDB inputs are switching correctly if operating in two-phase mode (see PHBPin). Otherwise, PWMCNTL is high impedance.
Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set theTSET 3 I
on-time versus COMP voltage and the minimum period at the gate drive outputs.
Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connecta 0.1- µF ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. ThisVCC 12 —
supply powers all circuits in the device and must be capable of delivering 6 mA dc plus the transientpower MOSFET gate charging current.
Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectifiedinput power mains. When the voltage on VINAC remains below the brownout threshold for more thanVINAC 7 I the brownout filter time, the device enters a brownout mode and both output drives are disabled. Selectthe input voltage divider ratio for the desired brownout threshold. Select the divider impedance for thedesired brownout hysteresis.
Voltage reference output: Connect a 0.1- µF ceramic bypass capacitor from this pin to AGND. VREFVREF 15 O turns off during VCC undervoltage and VSENSE disable to save supply current and increase efficiency.This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
Output dc voltage sense: Connect this pin to a voltage divider across the output of the powerconverter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for thedesired output voltage. Connect the ground side of this divider to ground through a separate short traceVSENSE 2 I for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drainlogic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduceVCC current. If VSENSE is disconnected, open-loop protection provides an internal current source topull VSENSE low, turning off the gate drivers.
Zero current detection inputs: These inputs expect to see a negative edge when the inductor currentin the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupledZCDA 16 I
through a series resistor that limits the clamping current to less than ± 3 mA. Connect these pins througha current limiting resistor to the zero crossing detection windings of the appropriate boost
inductor. The inductor winding must be connected so that this voltage drops when inductor currentdecays to zero. When the inductor current drops to zero, the ZCD input must drop below the fallingZCDB 1 I threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off,the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for anotherfalling ZCD edge.
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7VINAC
+
1.4V Brownout
440ms Delay
7mA
Crossover
Notch
Reduction
Phase A
On Time Control
3
1.68V/1V
ZCDA
+
1.68V/1V
ZCDB
+
16
1
Phase B
On Time Control
2VSENSE
+
VREF
gm
6V
15
EN
+
6.45V
OV
+
4.95V
300nA
TSET
STOPA
STOPB
5
COMP
222mV
Brownout
EN
UV
+
12 VCC
GDA
13 PGND
UV
12.6V
10.35V
24V
11 GDB
14
+
13.5V
PGND
Interleave
Control
4.87V
9
PWMCNTL
36mA
8 HVSEN
Phase
OK
2.5V
+
+
HVSEN OV
10
CS
Overcurrent
+
OV
OC
TSD
STOPA
HVSENOV
Burst Operation
STOPB
SinglePhase
-0.2V/-0.015V
OC
+
0.8V Single
Phase
4
PHB
6
AGND
Thermal
ShutDown
+
160C
TJTSD
ZCA
ZCB
Phase Fail
Detector
1.25V
13.5V
OV
EN
UV
96ms
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BLOCK DIAGRAM
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TYPICAL CHARACTERISTICS
V BiasSupplyVoltage V
VCC - -
5.5
5.0
4.5
4.0
3.5
3.0
0
0 2 4 6 8 10 12 14 16 18 20
I BiasSupplyCurrent mA-
VCC-
VCCTurn-Off VCCTurn-On
2.5
2.0
1.5
1.0
0.5
T Temperature C°
J- -
6.0
5.8
5.6
5.4
5.2
4.0
-40 -20 0 20 40 60 80 100 120
I BiasSupplyCurrent mA-
VCC -
5.0
4.8
4.6
4.4
4.2
Operating
T Temperature C°
J- -
140
120
100
80
60
0
-40 -20 0 20 40 60 80 100 120
I BiasSupplyCurrent A- m
VCC -
40
20
Disabled
V InputVoltage V
VSENSE - -
40
20
0
-20
-40
-60
-180
5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5
I OutputCurrent A
- m
COMP -
-80
-100
-120
-140
-160
Transconductance96 SmSinkCurrent
25 Am
InputRegulationVoltage
0 Aat6.0Vm
COMPOffsetEnable
165mVDownfrom
RegulationVoltage
SourceCurrentOverdriven-160 Am
UCC28061
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At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
BIAS SUPPLY CURRENT BIAS SUPPLY CURRENTvs vsBIAS SUPPLY VOLTAGE TEMPERATURE
Figure 1. Figure 2.
BIAS SUPPLY CURRENT
vsTEMPERATURE ERROR AMPLIFIER TRANSFER FUNCTION
Figure 3. Figure 4.
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l TEXAS INSTRUMENTS
T Temperature C°
J- -
110
105
100
95
90
80
-40 -20 0 20 40 60 80 100 120
g Transconductance s
- m
m-
85
5.94V<V <6.06V
SENSE
T Temperature C°
J- -
150
145
140
135
130
125
-40 -20 0 20 40 60 80 100 120
I CurrentSenseInputBiasCurrent A- m
CS -
V InputVoltage V
VSENSE - -
440
400
360
320
280
240
0
0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
I InputBiasCurrent nA
-
VSENSE -
200
160
120
80
40
UCC28061
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.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
ERROR AMPLIFIER TRANSCONDUCTANCE ERROR AMPLIFIER OUTPUT CURRENTvs vsTEMPERATURE OUTPUT VOLTAGE
Figure 5. Figure 6.
ERROR AMPLIFIER INPUT BIAS CURRENT CURRENT SENSE INPUT BIAS CURRENTvs vsINPUT VOLTAGE TEMPERATURE
Figure 7. Figure 8.
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‘9 TEXAS INSTRUMENTS < ‘="" :5th="" 359m="" m="">_‘_n_ Emu z
V InputVoltage V
ZCD - -
5
4
3
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
I ClampCurrent mA-
ZCD -
2
1
V InputVoltage V
ZCD - -
0
-0.5
-1.0
-3.5
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
I ClampCurrent mA-
ZCD -
-1.5
-2.0
-2.5
-3.0
Time ns-
14
12
10
-2
0 50 100 150 200 250 300 350
GateDriveOutput V-
8
6
4
2
0
V =20Vand12V
C =4.7nF
CC
LOAD
GDSourceCurrent:
V =20V
V =12V
CC
CC
GDVoltage:
V =20V
V =12V
CC
CC
3.0
2.5
2.0
-1.0
GateDriveSourceCurrent A
-
1.5
1.0
0.5
0
-0.5
T Temperature C°
J- -
500
490
480
470
460
350
-40 -20 0 20 40 60 80 100 120
BrownoutFilterDelayTime ms-
450
440
430
360
370
380
390
400
410
420
UCC28061
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
ZERO CURRENT DETECT CLAMP CURRENT ZERO CURRENT DETECT CLAMP CURRENTvs vsHIGH INPUT VOLTAGE LOW INPUT VOLTAGE
Figure 9. Figure 10.
BROWNOUT FILTER DELAY TIME GATE DRIVE RISINGvs vsTEMPERATURE TIME
Figure 11. Figure 12.
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/ /‘ / // \‘t "\\\
Time ns-
14
12
10
-2
0 20 40 60 80 100 120 140
GateDriveOutput V-
8
6
4
2
0
V =20Vand12V
C =4.7nF
CC
LOAD
GDSinkCurrent:
V =20V
V =12V
CC
CC
GDVoltage:
V =20V
V =12V
CC
CC
3.0
2.5
2.0
-1.0
GateDriveSourceCurrent A
-
1.5
1.0
0.5
0
-0.5
Time ns-
7
6
5
-1
-25 50 100 150 200 250 300
ZCDInput V-
4
3
2
1
0
0
14
12
10
-2
GateDriveOutput V-
8
6
4
2
0
C =4.7nF
LOAD
ZCDInputVoltage
GDOutput:
T = 40 C
T =+25 C
T =+125 C
J- °
J
J
°
°
Time ns-
500
400
300
-300
-25 50 100 150 200 250 300
CurrentSenseInput mV
-
200
100
0
-100
-200
0
14
12
10
-2
GateDriveOutput V-
8
6
4
2
0
C =4.7nF
LOAD
CSInput
Voltage GDOutput:
T = 40 C
T =+25 C
T =+125 C
J- °
J
J
°
°
V BiasSupplyVoltage V
VCC - -
15
14
13
12
11
10
8
10 11 12 13 14 15 16 17 18 19 20
GateDriveVoltage V-
9
R =2.7kW
LOAD
T = 40 C- °
J
T =+25 C
J°
T =+125 C
J°
UCC28061
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.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
GATE DRIVE FALLING GATE DRIVE RISINGvs vsTIME TIME AND DELAY FROM ZCD INPUT
Figure 13. Figure 14.
GATE DRIVE FALLING GATE DRIVE OUTPUT HIGHvs vsTIME AND DELAY FROM CS INPUT VCC
Figure 15. Figure 16.
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l TEXAS INSTRUMENTS \ \\ \ \\
GateDriveSinkCurrent mA-
2.5
2.0
1.5
1.0
0
0 1 2 3 4 5 6 7 8 9 10
GateDriveVoltage V-
0.5
T = 40 C- °
J
T =+25 C
J°
T =+125 C
J°
T Temperature C°
J- -
15
14
13
5
-40 -20 0 20 40 60 100 120
GateDriveVoltage V-
12
11
10
9
8
7
6
ClampedVCC 15V³
UnclampedVCC=12V
R =2kW
LOAD
60
R TimeSettingResistor kW
TSET - -
10
9
8
7
6
0
60 80 100 180 200 220 240 260 280
K On-TimeFactor s/V
- m
T-
5
4
3
2
1
120 140 160
KTL
T Temperature C°
J- -
9
8
7
0
-40 -20 0 20 40 60 80 100 120
K On-TimeFactor s/V-m
TL -
6
5
4
3
2
1
R =266kW
TSET
R =133kW
TSET
R =66kW
TSET
UCC28061
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TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
GATE DRIVE OUTPUT IN UVLO GATE DRIVE HIGH VOLTAGEvs vsSINK CURRENT TEMPERATURE
Figure 17. Figure 18.
ON-TIME FACTOR ON-TIME FACTOR PHASE A AND Bvs vsTIME SETTING RESISTOR TEMPERATURE
Figure 19. Figure 20.
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l TEXAS INSTRUMENTS s PWM Restart Time
PhaseShiftofGDARelativetoGDB -Degrees
110
108
106
90
150 160 170 180 190 200 210
K/K %
-
TT0
104
102
100
98
96
94
92
R =266kW
TSET
R =133kW
TSET
R =66kW
TSET
K =
T0
2(K K )´
TA TB
K +K
TA TB
GDA GDB
V InputACVoltageSense V
VINAC - -
100
0.1
0 0.5 1.0 1.5 2.0 2.5 3.0
AdditionalOn-Time s- m
10
1
R =266k
TSET W
R =133k
TSET W
R =66kW
TSET
UCC28061
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.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
TYPICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R
TSET
= 133 k Ω; all voltagesare with respect to GND, all outputs unloaded, T
J
= T
A
= +25 ° C, and currents are positive into and negative out of thespecified terminal, unless otherwise noted.
ON-TIME FACTOR PWM RESTART TIMEvs vsPHASE SHIFT TEMPERATURE
Figure 21. Figure 22.
ADDITIONAL ON-TIME
vsVINAC ZERO-CROSSING DISTORTION CORRECTION
Figure 23.
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l TEXAS INSTRUMENTS 2xL TON KT COMP )
APPLICATION INFORMATION
Theory of Operation
I (t)=
PEAK
VINAC(t) T´ON
L
(1)
I (t)=
AVG
VINAC(t) T´ON
2 L´
(2)
On-Time Control, Maximum Frequency Limiting, and Restart Timer
T =K (V 125mV)-
ON T COMP
(3)
T =K 4.825V´
ON(max) T
(4)
UCC28061
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The UCC28061 contains the control circuits for two boost pulse-width modulation (PWM) power converters. Theboost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage onthe error amplifier output. Each power converter then turns off the power MOSFET until current in the boostinductor decays to 0, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductorcurrent decays to 0, the power converter starts another cycle. This on/off cycling produces a triangle wave ofcurrent, with peak current set by the on-time and power mains input voltage, as shown in Equation 1 .
The average line current is exactly equal to half of the peak line current, as shown in Equation 2 .
With T
ON
and L being essentially constant during an ac line period, the resulting triangular current waveformduring each switching cycle has an average value proportional to the instantaneous value of the rectified ac linevoltage. This architecture results in a resistive input impedance characteristic at the line frequency and anear-unity power factor.
The outputs of the two PWMs operate 180 ° out-of-phase so that power-line ripple current for the two PWMs isgreatly reduced from the ripple current of each individual PWM. This design reduces ripple current at the inputand output, allowing the reduction in size and cost of input and output filters.
Optimal phase balance occurs if the individual power stages and the on-times are well-matched. Mismatches ininductor values do not affect the phase relationship.
Gate drive on-time varies with the error amplifier output voltage by a factor called K
T
, as shown in Equation 3 .
Where:
V
COMP
is the output of the error amplifier, and 125 mV is a modulator offset.
To provide smooth transition between two-phase and single-phase operation, K
T
increases by a factor of two insingle-phase mode:•K
TLS
= 2 × K
TL
; active in single-phase operation
The clamped maximum output of the error amplifier is limited to 4.95 V. This value, less the 125 mV modulatoroffset, limits on-time to Equation 4 .
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage level.
The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before theminimum period timer elapses, turn-on is delayed, resulting in discontinuous phase current.
The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD inputhas not transitioned high-to-low for approximately 200 µs. To prevent the circuit from operating in continuousconduction mode (CCM), the restart time does not trigger turn-on until both phase currents return to 0.
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l TEXAS INSTRUMENTS 133 kg 133 ks:
K =
TL
RTSET
133kW´4.0 ms
V
(5)
T =
MIN
RTSET
133kW´2.2ms;MinimumSwitchingPeriod
(6)
Natural Interleaving
Phase Management
UCC28061
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.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
The on-time factors (K
TH
, K
THS
, K
TL
, K
TLS
) and the minimum switching period T
MIN
are proportional to the timesetting resistor R
TSET
, the resistor from the TSET pin to ground, and they can be calculated by Equation 5through Equation 6 :
The proper value of R
TSET
results in the clamped maximum on-time, T
ON(max)
, required by the converter operatingat the minimum input line and maximum load.
Under normal operating conditions, the UCC28061 regulates the relative phasing of the channel A and channel Binductor currents to be very close to 180 ° , minimizing the ripple currents seen at the line source and outputcapacitor. The phase control function differentially modulates the on-times of the A and B channels based on thephase and frequency relationship. This natural interleaving method allows the converter to achieve 180 ° phaseshift and transition mode operation for both phases without the requirements on boost inductor tolerance. As aresult, the current sharing of the A and B channels are proportional to the inductor tolerance. The best currentsharing is achieved when both inductors are exactly the same value.
At light load, it can improve efficiency to shut down one phase. Although conduction losses increase inone-phase operation, switching losses decrease. At certain power levels, the reduction of switching losses isgreater than the increase in conduction losses. Turning off one phase at light load is especially valuable formeeting light-load efficient standards.
To operate in two-phase (normal) mode, pull PHB high or connect PHB to VREF. To operate in one-phasemode, connect PHB to ground.
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l TEXAS INSTRUMENTS
Zero Crossing Detection and Valley Switching
R
C
ZCD
CT
R1
CR2
ZCD
CT
Brownout Protection
Failsafe OVP — Output Over-Voltage Protection
UCC28061
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In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current crosses 0. Because of theresonance between the boost inductor and the parasitic capacitor at the MOSFET drain node, part of the energystored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore, when therectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET junctioncapacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate delay,the MOSFET can be turned on at the valley of its resonating drain voltage (valley switching). In this way, theenergy recovery can be maximized and switching loss is minimized.
The RC time constant is generally derived empirically, but a good starting point is a value equal to 25% of theresonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 24 .Because the ZCD pin is internally clamped, a more accurate delay can also be realized by using Figure 25 .
Figure 24. Simple RC Delay Circuit
Figure 25. More Accurate Time Delay Circuit
As the power line RMS voltage decreases, RMS input current increases to maintain the output voltage constantfor a specific load. Brownout protection prevents the RMS input current from exceeding a safe operating level.Power line RMS voltage is sensed at VINAC. When the voltage applied to VINAC fails to exceed the brownoutthreshold for the brownout filter time, a brownout condition is detected and both gate drive outputs immediatelypull low. During brownout, COMP is actively pulled low. Gate drive outputs remain low until the voltage on VINACrises above the brownout threshold. After a brownout, the power stage soft-starts as COMP rises.
The brownout detection threshold and its hysteresis are set by the voltage divider ratio and resistor values.Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on line peakvoltage. The peak VINAC voltage can be easily translated into RMS value. Suggested resistor values for thevoltage divider are 3 M Ω± 1% from the rectified input voltage to VINAC and 46.4 k Ω± 1% from VINAC to ground.These resistors set the typical thresholds for RMS line voltages, as shown in Table 1 .
Table 1. Brownout Thresholds
THRESHOLD BROWNOUT (RMS)
Falling 65 V
Rising 79.8 V
FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant pathsfor output voltage sensing provide additional protection against output over-voltage. Over-voltage protection isimplemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either inputsenses an over-voltage condition. The output voltage can still maintain a safe level with either loop failure. Thedevice is re-enabled when both sense inputs fall back into the normal range. At that time, the gate drive outputsresume switching under PWM control. Output over-voltage does not cause soft-start and the COMP pin is notdischarged during an output over-voltage event.
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Over-Current Protection
Phase Fail Protection
Distortion Reduction
UCC28061
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.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
Under certain conditions (such as inrush, brownout recovery, and output overload), the PFC power stage seeslarge currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current sensing method uses a shunt resistor in series with the MOSFET source to sense theconverter current, resulting in multiple ground points and high power dissipation. Furthermore, since no currentinformation is available when the MOSFETs are off, the source resistor current sensing method requiresrepeated turn-ons of the MOSFETs during over-current conditions. As a result, the converter may temporarilyoperate in continuous current mode (CCM) and experience failures induced by excessive reverse recoverycurrents in the boost diode.
The UCC28061 uses a single resistor to continuously sense the total inductor (input) current. This way, turn-on ofthe MOSFETs is completely avoided when the inductor currents are excessive. The drive to the MOSFETs isinhibited until total inductor current drops to near zero, precluding reverse recovery induced failures (thesefailures are most likely to occur when the ac line recovers from a brownout condition).
Following an over-current condition, both MOSFETs are turned on in phase when the input current drops to near0. Because two phase currents are temporarily operating in phase, set the over-current protection threshold tomore than twice of each phase maximum current ripple value in order to allow a return to normal operation afteran over-current event.
The UCC28061 detects failure of one phase by monitoring the sequence of ZCD pulses. During normaltwo-phase operation, if one ZCD input remains idle for longer than approximately 14 ms while the other ZCDinput switches normally, PWMCNTL goes high, indicating that the power stage is not operating correctly. Duringnormal single-phase operation, phase failure is not monitored. On the UCC28061, phase failure is not monitoredif COMP is below approximately 222 mV.
Because of the resonance between the capacitance present across the drain-source of the switching MOSFETand the boost inductor, conventional transition mode power factor correction circuits may not be able to absorbpower from the input line when the input voltage is around 0 V. This limitation results in waveform distortion andincreased harmonic distortion. To reduce line current distortion to the lowest possible level, the UCC28061increases switching MOSFET on-time when input voltage is around 0 V to increase the power absorption andcompensate for this effect.
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Improved Error Amplifier
REF
VSENSE
+
-
COMP
4.95V
CZ
RZ
CP
+
+
COMP
VSENSE
Soft Start
6V
5.8V
6.45V
OV
PWM
Shutdown
100mA
gm
+
R Q
QS
+
0.5V
Brownout
EN
UV
OV
UCC28061
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The voltage error amplifier is a transconductance amplifier. Voltage loop compensation is connected from theerror amplifier output, COMP, to analog ground, AGND. The recommended compensation network is shown inFigure 26 .
Figure 26. Typical Error Amplifier Compensation
To improve the transient response, the error amplifier output current is increased by 100 µA when the error ampinput is below 5.8 V, as shown in Figure 27 . This increase allows faster charging of the compensationcomponents following sudden load current increases (also refer to Figure 4 in the Typical Characteristics ).
Figure 27. Error Amplifier Block Diagram Showing Speed-Up and Latched Soft-Start
The UCC28061 asserts soft start when output over-voltage is detected, pulling COMP to ground. This improvesresponse to a change from heavy load to light load.
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l TEXAS INSTRUMENTS
Open-Loop Protection
Soft-Start
Light-Load Operation
Command for the Downstream Converter
VCC Undervoltage Protection
VCC
UCC28061
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.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
If the feedback loop is disconnected from the device, a current source internal to the UCC28061 pulls theVSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device is disabled. When disabled,supply current decreases, and both gate drive outputs and COMP are actively pulled low. The device isre-enabled when VSENSE rises above 1.25 V. At that time, the gate drive outputs begin switching under PWMcontrol.
The device can be externally disabled by grounding the VSENSE pin with an open-drain or open-collector driver.When disabled, device supply current drops and COMP is actively pulled low. When VSENSE is released, thedevice soft-starts. This disable method forces the device into standby mode and minimizes its powerconsumption. This feature is particularly useful when standby power is a key design aspect.
If the feedback loop is disconnected from ground, the VSENSE voltage goes high. When VSENSE rises abovethe over-voltage protection threshold, both gate drive outputs go low, and COMP is actively pulled low. Thedevice is re-enabled when VSENSE falls back into range. At that time, the gate drive outputs begin switchingunder PWM control. The VSENSE pin is internally clamped to protect the device from damage under thiscondition.
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP toAGND charges from a low level to the final value. This process implements a soft-start, with a time constant setby the output current of the error amplifier and the value of the compensation capacitors. In the event of abrownout, logic disable, or VCC undervoltage fault, COMP is actively pulled low so the PWM soft-starts after thisevent is cleared. The UCC28061 also asserts soft start when output over-voltage is detected. Even if a faultevent happens very briefly, soft-start fully discharges the compensation components before resuming operation,ensuring soft-starting. See Figure 27 for details.
As load current decreases, the error amplifier commands less input current by lowering the COMP voltage. IfPHB (normally connected to COMP) falls below 0.8 V at low input line (or 1.1 V at high input line), channel Bstops switching and channel A on-time doubles to compensate. If COMP falls below 150 mV, channel A alsostops switching and the loop enters a hysteretic control mode. The PWM skips cycles to maintain regulation.
Instead of skipping cycles, the UCC28061 allows on-time reduction smoothly to zero as load decreases.However, maximum switching frequency is limited, so at very light load, discountinuous operation is possible.
In the UCC28061, the PWMCNTL pin is used to coordinate the PFC stage with a downstream converter.Through the HVSEN pin, the output voltage is sensed. When the output voltage is within the desired range, thePWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. The enablethreshold and hysteresis can be adjusted independently through the voltage divider ratio and resistor values. TheHVSEN pin is also used for the FailSafe over-voltage protection. When designing the voltage divider, make surethis FailSafe over-voltage protection level is set above normal operating levels.
VCC must rise above the undervoltage threshold for the PWM to begin functioning. If VCC drops below thethreshold during operation, both gate drive outputs and COMP are actively pulled low. VCC must rise above thethreshold for PWM function to restart.
VCC is connected to a bias supply of between 13 V and 21 V. When powered from a poorly-regulated supply, anexternal zener diode is recommended to prevent excessive current into VCC.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): UCC28061
‘5; TEXAS INSTRUMENTS
DESIGN EXAMPLE
+–
COMP
VREF
PGNDAGND
VCC ZCDA
ZCDB
GDA
CS
GDB
VINAC
VSENSE
PWMCNTL
UCC28061
TSET
PHB
HVSEN
R
100 W
CIN
10nF
RZ
CZ
RSCPRT
16V
2.2 mF
Q1
Q2
D1
D2
RZA
RZB
L1
L2
RG1
RG2
COUT
RD
RC
RLOAD
16V
RE
RF
RA
RB
50kW
PWMCNTL 20kW
20kW
5W
5W
CB
CA
F1
D3
2.2 mF
CF3
CF2
RP
Bridge
VOUT
CF4
22pF
CF5
22pF
Design Goals
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
www.ti.com
An example of the UCC28061 PFC controller in a two-phase transition mode interleaved PFC pre-regulator isshown in Figure 28 .
Figure 28. Typical Transition Mode Interleaved PFC Pre-Regulator
The specifications for this design were chosen based on the power requirements of a 300-W LCD TV. Thesespecifications are shown in Table 2 .
Table 2. Design Specifications
PARAMETER MIN TYP MAX UNIT
265V
IN
RMS input voltage 85 (V
IN_MIN
) V
RMS(V
IN_MAX
)
V
OUT
Output voltage 390 V
f
LINE
Line frequency 47 63 Hz
PF Power factor at maximum load 0.90
P
OUT
300 W
ηFull load efficiency 0.92
f
MIN
Minimum switching frequency 45 kHz
22 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28061
{I} TEXAS INSTRUMENTS
Recommended PCB Device Layout
CF4
UCC28061
www.ti.com
.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the inputand output filter capacitors should be located after the two phase currents are combined together. Similar toother power management devices, when laying out the printed circuit board (PCB) it is important to use stargrounding techniques and keep filter capacitors as close to device ground as possible. To minimize theinterference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneathmagnetic elements. Because of the precise timing requirement, the timing setting resistor R
T
should be put asclose as possible to the TSET pin and returned to the analog ground. See Figure 29 for a recommendedcomponent layout and placement.
Figure 29. Recommended PCB Layout
NOTE:
PHB and VREF Pins are connected by a Jumper on the back of the board.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): UCC28061
l TEXAS INSTRUMENTS Vou‘r Pom fMIN ZA RZE kg
Inductor Selection
D =
PEAK_LOW_LINE
V V- Ö
OUT IN_MIN 2
VOUT
»0.69
=
390V 85V- Ö2
390V
(7)
L1=L2=
h ´ V xD
IN_MIN PEAK_LOW_LINE
2
P f
OUT MIN
´» m340 H
=0.92(85V) 0.69
2
300W 45kHz´
(8)
I =
LPEAK
PÖ
OUT 2
V´ h
IN_MIN
=300W Ö2
85V 0.92´»5.4A
(9)
I =
LRMS
ILPEAK
Ö6=5.4A
Ö6»2.2A
(10)
V V- Ö
OUT IN_MAX 2
2V »8
=390V 265V- Ö2
2V
NP
NS
=
(11)
ZCD Resistor Selection (R
ZA
, R
ZB
)
V N
OUT S
N 3mA´
P
» W16.3k
=390V
8 3mA´
R =R ³
ZA ZB
(12)
R =R =2
ZA ZB 0kW
(13)
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
www.ti.com
The boost inductor is selected based on the inductor ripple current requirements at the peak of low line.Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (D
PEAK_LOW_LINE
),as shown in Equation 7 .
The minimum switching frequency of the converter (f
MIN
) under low line conditions occurs at the peak of low lineand is set between 25 kHz and 50 kHz to avoid audible noise. For this design example, f
MIN
was set to 45 kHz:
The inductor for this design would have a peak current (I
LPEAK
) of 5.4 A, as shown in Equation 9 , and an RMScurrent (I
LRMS
) of 2.2 A, as shown in Equation 10 .
This converter uses constant on-time (T
ON
) and zero-current switching (ZCS) to set up the converter timing.Auxiliary windings off of L1 and L2 detect when the inductor currents are 0. Selecting the turns ratio inEquation 11 ensures that there is at least 2 V at the peak of high line to reset the ZCD comparator after everyswitching cycle.
The turns-ratio of each auxiliary winding is:
The minimum value of the ZCD resistors is selected based on the internal zener clamp maximum current ratingof 3 mA, as shown in Equation 12 .
In this design the ZCD resistors were set to 20 k Ω, as shown in Equation 13 .
24 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28061
l TEXAS INSTRUMENTS
HVSENSE
V =V 0.90 351V´ »
OUT_OK OUT
(14)
R =
E
Hysteresis
36 Am=108V
36 Am=3MW
(15)
R =
F=
=31.185kW » W31.6k
2.5V
V 2.5V-
OUT_OK
RE
- m36 A
2.5V
351V 2.5V-
3MW- m36 A
(16)
V =
OUT_MIN =»240V
2.5V(R +R )
E F
RF
2.5V(3M +31.6k )W W
31.6kW
(17)
V =
OV_FAILSAFE =»467V
4.87V(R +R )
E F
RF
4.87V(3M +31.6k )W W
31.6kW
(18)
UCC28061
www.ti.com
.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
The HVSENSE pin programs the PWMCNTL output of the UCC28061. The PWMCNTL open-drain output can beused to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts in highimpedance and pulls to ground when the HVSENSE increases above 2.5 V. Setting the point where PWMCNTLbecomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 14 toEquation 18 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominalvalue.
Resistor R
E
sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal.For this example, R
E
was selected to provide 108 V of hysteresis, as shown in Equation 15 .
Resistor R
F
is used to program the PWMCNTL active threshold, as shown in Equation 16 .
This PWMCNTRL output remains active until a minimum output voltage (V
OUT_MIN
) is reached, as shown inEquation 17 .
According to the resistor value, the FailSafe OVP threshold should be set according to Equation 18 :
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): UCC28061
l TEXAS INSTRUMENTS OUT VOUT
Output Capacitor Selection
C³
OUT =» m147 F
V (V )-
OUT OUT_MIN
2 2
2
POUT
h
1
fLINE
(390V) (240V)-
2 2
2300W
0.92
1
47Hz
(19)
C =200 Fm
OUT
(20)
21 2 300 14
4 0 92 390 4 47 200h p p m
´´
= = »
´ ´ ´ ´ ´ ´ ´
OUT
RIPPLE
OUT LINE OUT
PW
V V
V f C . V Hz F
(21)
I =
COUT_100Hz = =0.591A
POUT
V´ h Ö
OUT ´2
300W
390V 0.92´ ´ Ö2
(22)
I =
COUT_HF -(I )
COUT_100 Hz
2
P 2
OUT Ö2
2´ ´h VIN_MIN
4 VÖIN_MIN
2
9 VpOUT
2
(23)
I =
COUT_HF -(0.591A)2
300W 2´ Ö2
2´ ´0.92 85V
4 85VÖ ´2
9 390Vp ´
2
»0.966A
(24)
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
www.ti.com
The output capacitor (C
OUT
) is selected based on holdup requirements as shown in Equation 19 .
Two 100- µF capacitors were used in parallel for the output capacitor:
For this size capacitor, the output voltage ripple (V
RIPPLE
) is approximately 11 V, as shown in Equation 21 :
In addition to hold-up requirements, a capacitor must be selected so that it can withstand the low-frequency RMScurrent (I
COUT_100 Hz
) and the high-frequency RMS current (I
COUT_HF
); see Equation 22 to Equation 24 .High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current rating on theproduct data sheets.
26 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28061
l TEXAS INSTRUMENTS ‘PEAK 0.015 S2 IDM IPEAK
Selecting an R
S
for Peak Current Limiting
I =
PEAK »13A
2P (1.2)
OUT Ö2
h ´ VIN_MIN
2 300W 1.2´ Ö ´
2
0.92 85V´
=
(25)
R =
S» W15m
200mV
IPEAK
200mV
13A
=
(26)
R =
S´ »15m 0.22WW
300W
85V 0.92´
2
P =
RS
POUT
V´ h
IN_MIN
2
(27)
´5s= 833A s
2
2.5W
0.015 W
I t=
2
(28)
Power Semiconductor Selection (Q1, Q2, D1, D2):
I I =13A³
DM PEAK
(29)
I =
DS »2.3A
4 VÖIN_MIN
2
9 Vp ´ OUT
IPEAK
2
1
6-=4 85VÖ ´
2
9 390Vp ´
13A
2
1
6-
(30)
I =
D»1.4A
4 VÖIN_MIN
2
9 Vp ´ OUT
IPEAK
2=4 85VÖ ´
2
9 390Vp ´
13A
2
(31)
UCC28061
www.ti.com
.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
The UCC28061 peak limit comparator senses the total input current and is used to protect the MOSFETs duringinrush and over-load conditions. For reliability, the peak current limit (I
PEAK
) threshold in this design is set for120% of the nominal inrush current that is observed during power-up, as shown in Equation 25 .
A standard 15-m Ωmetal-film current-sense resistor is used for current sensing, as shown in Equation 26 . Theestimated power loss of the current sense resistor (P
RS
) is less than 0.25 W during normal operation, as shownin Equation 27 .
The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs towithstand a short-circuit current larger than the current required to open the fuse (F1). I
2
t (ampere squaredseconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I
2
t is equalto RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I
2
t of 14 A
2
s waschosen to protect the design from a short-circuit condition. To ensure the current-sense resistors have a highenough surge protection, a 15-M Ω, 500-mW, metal-strip resistor was chosen for the design. The resistor has a2.5-W surge rating for 5 seconds. This result translates into 833 A
2
s and has a high enough I
2
t rating to survive ashort-circuit before the fuse opens, as described in Equation 28 .
The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application noteSLUU138 ,UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-Regulator, explains how toselect power semiconductor components for transition-mode PFC pre-regulators.
The MOSFET maximum-pulsed drain current (Q1, Q2) is shown in Equation 29 :
The MOSFET RMS current calculation (Q1, Q2) is shown in Equation 30 :
To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.
The boost diode RMS current (D1, D2) is shown in Equation 31 :
To meet the power requirements of the design, MURS306T3 600-V diodes from On Semiconductor were chosenfor the design for D1 and D2.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): UCC28061
l TEXAS INSTRUMENTS VREF $2 Pom MAX M52 OUT VREF) V7 fMW
Brownout Protection
R =
A» W3M
Hysteresis
7 Am=21V
7 Am
(32)
R =
B» W47k
1.4V R´A
V 0.75 1.4V´ Ö -
IN_MIN 2=1.4V ´ W3M
85V 0.75 1.4V´ Ö -2
(33)
Converter Timing
f =
MIN =39.2kHz
P L1
OUT MAX
´=
h(V )´IN_MIN
2VÖ
IN_MIN ´2
VOUT
1-
300W 390 Hm´
0.92 (85V)´285V Ö´ 2
390V
1-
(34)
R =
TSET » W121k
4.85V 4 s fm´ ´ MIN
=
133kWVÖ
IN_MIN ´2
VOUT
1-
4.85V 4 s 39.2kHzm´ ´
133kW85V Ö´ 2
390V
1-
(35)
f =
MAX »550kHz
2 s Rm ´ T
=
133kW
2 s 121km W´
133kW
(36)
Programming V
OUT
R =3MW
C
(37)
V =6V
REF
(38)
R =
D» W47k
(V V )-
OUT REF
=
V R
REF C
´
(390V 6V)-
6V 3M´ W
(39)
V =6.45V
OVP =418V
RD
=6.45V
R +R
C D
47kW
3M +47kW W
(40)
UCC28061
SLUS837A – JUNE 2008 – REVISED JULY 2009 ..............................................................................................................................................................
www.ti.com
Resistor R
A
and R
B
are selected to activate brownout protection at 75% of the specified minimum operated inputvoltage. Resistor R
A
programs the brownout hysteresis comparator, which was selected to provide 21 V ofhysteresis. R
A
and R
B
are shown in Equation 32 and Equation 33 .
In this design example, brownout becomes active when the input drops below 64 V
RMS
and deactivates when theinput reaches 79 V
RMS
.
Select the timing resistor, R
TSET
, for the correct on-time (T
ON
) based on K
TL
, as shown in Equation 34 . To ensureproper operation, the timing must be set based on the highest boost inductance (L1
MAX
). In this design example,the boost inductor could be as high as 390 µH, based on line and load conditions, as shown in Equation 35 .
This result sets the maximum frequency clamp (f
MAX
), as shown in Equation 36 , which improves efficiency at lightload.
Resistor R
C
is selected to minimize error because of VSENSE input bias current and minimize loading on thepower line when the PFC is disabled. Construct resistor R
C
from two or more resistors in series to meethigh-voltage requirements. R
C
was also selected to be of a similar value of R
A
and R
E
to simplify the bill ofmaterials and reduce design costs.
Based on the resistor values shown in Equation 37 to Equation 39 , the primary output over-voltage protectionthreshold should be as shown in Equation 40 :
28 Submit Documentation Feedback Copyright © 2008 – 2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28061
l TEXAS INSTRUMENTS VOUT S2 WPLE m
Loop Compensation
g =96 Sm
m
(41)
H= »0.015=
VREF
VOUT
6V
390V
(42)
R =
Z=6.313k 6.34k» WW=
100mV
V H g
RIPPLE m
´ ´
100mV
11V 0.015 96 Sm´ ´
(43)
C =
Z=2.67 Fm=
1
fLINE
5
2p ´ ´ RZ
1
47Hz
5
2p ´ ´ W6.34k
(44)
C =
P=1.12nF=
1
fMIN
2
2p ´ ´ RZ
1
45kHz
2
2p ´ ´ W6.34k
(45)
C =2.2 Fm
Z
(46)
C =1nF
P
(47)
ADDITIONAL REFERENCES
Related Parts
References
Package Outline and Recommended PCB Footprint
UCC28061
www.ti.com
.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009
Resistor R
Z
is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. Thisvalue ensures good power factor and low input current harmonic distortion.
The transconductance amplifier gain is shown in Equation 41 :
The voltage divider feedback gain is shown in Equation 42 and Equation 43 :
C
Z
is then set to add 45 ° of phase margin at 1/5th of the switching frequency, as shown in Equation 44 :
C
P
is sized to attenuate high-frequency noise, as shown in Equation 45 :
The standard values of Equation 46 and Equation 47 should be chosen for C
Z
and C
P
.
Table 3 lists several TI parts that have characteristics similar to the UCC28061.
Table 3. Related Parts
DEVICE DESCRIPTION
UCC28051 PFC controller for low to medium power applications
UCC28019 8-pin continuous conduction mode (CCM) PFC controller
UCC28060 Natural Interleaving™ Dual-Phase Transition-Mode PFC Controller
These references, design tools, and links to additional references, including design software, may be found atwww.power.ti.com :•Evaluation Module, UCC28060EVM 300W interleaved PFC Pre-regulator,SLUU280 from Texas Instruments•Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator,SLUU138 from Texas Instruments
The mechanical packages at the end of this data sheet outline the mechanical dimensions of the 16-pin D(SOIC) package and provide recommendations for PCB layout.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): UCC28061
TEXAS INSTRUMENTS Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
UCC28061D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28061
UCC28061DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28061
UCC28061DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 UCC28061
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC28061 :
•Automotive : UCC28061-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC28061DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28061DR SOIC D 16 2500 340.5 336.1 32.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UCC28061D D SOIC 16 40 507 8 3940 4.32
UCC28061DG4 D SOIC 16 40 507 8 3940 4.32
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
MECHANICAL DATA D ( *"ifi O G if” )LASHC SMALL 0U ¥N¥ 4040047 S/M 06/1‘ NO'ES, A AH Hnec' dimensmrs c'e m 'mc'ves ['nflhmeter5> B Th5 drawer ‘5 subje», ,0 change mm: Home, A Body \cngth docs rm mac mod Hoar, p'omswons, (xv gmc bms Mom mm warmers, or gm buns sha‘ nm exceed 3005 (015) eam swce @ Body mm does 101 meme 11mm fish. E Rdererce JEDEC MS 012 mam Ac, nter‘ec: flash sfu‘ not exceed 0017 (043) each swde {if TEXAS INSTRUMENTS www.1i.com
LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
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