Texas Instruments 的 SN74AUP1G74 规格书

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SN74AUP1G74
SCES644D –MARCH 2006–REVISED DECEMBER 2015
SN74AUP1G74 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
With Clear and Preset
1 Features 2 Applications
1• Available in the Texas Instruments NanoStar™ • Servers
Package • LED Displays
• Low Static-Power Consumption: • Network Switches
ICC = 0.9 μA Maximum • Telecom Infrastructure
• Low Dynamic-Power Consumption: • Motor Drivers
Cpd = 5.5 pF Typical at 3.3 V • I/O Expanders
• Low Input Capacitance: Ci= 1.5 pF Typical
• Low Noise – Overshoot and Undershoot 3 Description
< 10% of VCC The AUP family is TI's premier solution to the
• Ioff Supports Partial-Power-Down Mode Operation industry's low-power needs in battery-powered
portable applications. This family ensures a very low
• Schmitt-Trigger Action Allows Slow Input static- and dynamic-power consumption across the
Transition and Better Switching Noise Immunity at entire VCC range of 0.8 V to 3.6 V, resulting in
the Input increased battery life. This product also maintains
(Vhys = 250 mV Typical at 3.3 V) excellent signal integrity (see the very low undershoot
• Wide Operating VCC Range of 0.8 V to 3.6 V and overshoot characteristics shown in Figure 6).
• Optimized for 3.3-V Operation Device Information(1)
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal PART NUMBER PACKAGE BODY SIZE (NOM)
Operation SN74AUP1G74YFP DSBGA (8) 1.56 mm × 0.76 mm
• tpd = 5 ns Maximum at 3.3 V SN74AUP1G74YZP DSBGA (8) 1.86 mm × 0.89 mm
• Suitable for Point-to-Point Applications SN74AUP1G74DCU VSSOP (8) 2.30 mm × 2.00 mm
• Latch-Up Performance Exceeds 100 mA Per SN74AUP1G74DQE X2SON (8) 1.40 mm × 1.00 mm
JESD 78, Class II SN74AUP1G74RSE UQFN (8) 1.50 mm × 1.50 mm
• ESD Performance Tested Per JESD 22 (1) For all available packages, see the orderable addendum at
– 2000-V Human-Body Model (A114-B, Class II) the end of the data sheet.
– 1000-V Charged-Device Model (C101)
AUP – The Lowest-Power Family
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.2 Enable and Disable Times...................................... 14
1 Features.................................................................. 18 Detailed Description............................................ 15
2 Applications ........................................................... 18.1 Overview ................................................................. 15
3 Description ............................................................. 18.2 Functional Block Diagram....................................... 15
4 Revision History..................................................... 28.3 Feature Description................................................. 15
5 Pin Configuration and Functions......................... 38.4 Device Functional Modes........................................ 15
6 Specifications......................................................... 49 Application and Implementation ........................ 16
6.1 Absolute Maximum Ratings ..................................... 49.1 Application Information .......................................... 16
6.2 ESD Ratings ............................................................ 49.2 Typical Power Button Circuit .................................. 16
6.3 Recommended Operating Conditions ...................... 410 Power Supply Recommendations ..................... 17
6.4 Thermal Information.................................................. 511 Layout................................................................... 17
6.5 Electrical Characteristics, TA= 25°C ........................ 511.1 Layout Guidelines ................................................. 17
6.6 Electrical Characteristics, TA= –40°C to +85°C ....... 611.2 Layout Example .................................................... 17
6.7 Timing Requirements................................................ 712 Device and Documentation Support ................. 18
6.8 Switching Characteristics, CL= 5 pF ........................ 812.1 Documentation Support ........................................ 18
6.9 Switching Characteristics, CL= 10 pF ...................... 912.2 Community Resources.......................................... 18
6.10 Switching Characteristics, CL= 15 pF .................. 10 12.3 Trademarks........................................................... 18
6.11 Switching Characteristics, CL= 30 pF .................. 11 12.4 Electrostatic Discharge Caution............................ 18
6.12 Operating Characteristics...................................... 12 12.5 Glossary................................................................ 18
6.13 Typical Characteristics.......................................... 12 13 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information ............... 13 Information ........................................................... 18
7.1 Propagation Delays, Setup and Hold Times, and
Pulse Width)............................................................. 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2010) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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C1 C2
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A1 A2
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SN74AUP1G74
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SCES644D –MARCH 2006–REVISED DECEMBER 2015
5 Pin Configuration and Functions
DCU Package DQE Package
8-Pin VSSOP 8-Pin X2SON
Top View Top View
YFP or YZP Package
RSE Package 8-Pin DSBGA
8-Pin UQFN Top View
Top View
Pin Functions(1)
PIN
I/O DESCRIPTION
VSSOP,
NAME UQFN DSBGA
X2SON
CLK 1 7 A1 I Rising edge triggered clock signal input
CLR 6 2 C2 I Clear, Active low
D 2 6 B1 I Data input
GND 4 4 D1 — Ground
PRE 7 1 B2 I Preset, Active low
Q 5 3 D2 O Output
Q 3 5 C1 O Inverted output
VCC 8 8 A2 — Power supply
(1) See Mechanical, Packaging, and Orderable Information for dimensions.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 4.6 V
VIInput voltage(2) –0.5 4.6 V
VOVoltage applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VOOutput voltage in the high or low state(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature 150 °C
Tstg Storage temperature –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Electrostatic
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
MIN MAX UNIT
VCC Supply voltage 0.8 3.6 V
VCC = 0.8 V VCC
VCC = 1.1 V to 1.95 V 0.7 × VCC
VIH High-level input voltage V
VCC = 2.3 V to 2.7 V 1.6
VCC = 3 V to 3.6 V 2
VCC = 0.8 V 0
VCC = 1.1 V to 1.95 V 0.3 × VCC
VIL Low-level input voltage V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.9
VIInput voltage 0 3.6 V
VOOutput voltage 0 VCC V
VCC = 0.8 V –20 μA
VCC = 1.1 V –1.1
VCC = 1.4 V –1.7
IOH High-level output current VCC = 1.65 –1.9 mA
VCC = 2.3 V –3.1
VCC = 3 V –4
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs,SCBA004.
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Recommended Operating Conditions(1) (continued)
MIN MAX UNIT
VCC = 0.8 V 20 μA
VCC = 1.1 V 1.1
VCC = 1.4 V 1.7
IOL Low-level output current VCC = 1.65 V 1.9 mA
VCC = 2.3 V 3.1
VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V
TAOperating free-air temperature –40 85 °C
6.4 Thermal Information
SN74AUP1G74
DCU DQE RSE YFP/YZP
THERMAL METRIC(1) UNIT
(VSSOP) (X2SON) (UQFN) (DSBGA)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 227 261 253 102 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics, TA= 25°C
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IOH = –20 μA 0.8 V to 3.6 V VCC – 0.1
IOH = –1.1 mA 1.1 V 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.11
IOH = –1.9 mA 1.65 V 1.32
VOH V
IOH = –2.3 mA 2.05
2.3 V
IOH = –3.1 mA 1.9
IOH = –2.7 mA 2.72
3 V
IOH = –4 mA 2.6
IOL = 20 μA 0.8 V to 3.6 V 0.1
IOL = 1.1 mA 1.1 V 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.31
IOL = 1.9 mA 1.65 V 0.31
VOL V
IOL = 2.3 mA 0.31
2.3 V
IOL = 3.1 mA 0.44
IOL = 2.7 mA 0.31
3 V
IOL = 4 mA 0.44
IIA or B input VI= GND to 3.6 V 0 V to 3.6 V 0.1 μA
Ioff VIor VO= 0 V to 3.6 V 0 V 0.2 μA
ΔIoff VIor VO= 0 V to 3.6 V 0 V to 0.2 V 0.2 μA
VI= GND or (VCC to 3.6 V),
ICC 0.8 V to 3.6 V 0.5 μA
IO= 0
ΔICC VI= VCC – 0.6 V(1), IO= 0 3.3 V 40 μA
0 V 1.5
CiVI= VCC or GND pF
3.6 V 1.5
CoVO= GND 0 V 3 pF
(1) One input at VCC – 0.6 V, other input at VCC or GND
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6.6 Electrical Characteristics, TA= –40°C to +85°C
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IOH = –20 μA 0.8 V to 3.6 V VCC – 0.1
IOH = –1.1 mA 1.1 V 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.03
IOH = –1.9 mA 1.65 V 1.3
VOH V
IOH = –2.3 mA 1.97
2.3 V
IOH = –3.1 mA 1.85
IOH = –2.7 mA 2.67
3 V
IOH = –4 mA 2.55
IOL = 20 μA 0.8 V to 3.6 V 0.1
IOL = 1.1 mA 1.1 V 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.37
IOL = 1.9 mA 1.65 V 0.35
VOL V
IOL = 2.3 mA 0.33
2.3 V
IOL = 3.1 mA 0.45
IOL = 2.7 mA 0.33
3 V
IOL = 4 mA 0.45
IIA or B input VI= GND to 3.6 V 0 V to 3.6 V 0.5 μA
Ioff VIor VO= 0 V to 3.6 V 0 V 0.6 μA
ΔIoff VIor VO= 0 V to 3.6 V 0 V to 0.2 V 0.6 μA
VI= GND or (VCC to 3.6 V),
ICC 0.8 V to 3.6 V 0.9 μA
IO= 0
ΔICC VI= VCC – 0.6 V(1), IO= 0 3.3 V 50 μA
0 V
CiVI= VCC or GND pF
3.6 V
CoVO= GND 0 V pF
(1) One input at VCC – 0.6 V, other input at VCC or GND
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SCES644D –MARCH 2006–REVISED DECEMBER 2015
6.7 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC MIN(1) TYP(2) MAX(1) UNIT
0.8 V 21
1.2 V ± 0.1 V 40
1.5 V ± 0.1 V 50
fclock Clock frequency MHz
1.8 V ± 0.15 V 60
2.5 V ± 0.2 V 90
3.3 V ± 0.3 V 90
0.8 V 3.5
1.2 V ± 0.1 V 2
1.5 V ± 0.1 V 2
CLK high or low 1.8 V ± 0.15 V 2
2.5 V ± 0.2 V 2
3.3 V ± 0.3 V 2
twPulse duration ns
0.8 V 4.5
1.2 V ± 0.1 V 2
1.5 V ± 0.1 V 2
PRE or CLR low 1.8 V ± 0.15 V 2
2.5 V ± 0.2 V 2
3.3 V ± 0.3 V 2
0.8 V 3
1.2 V ± 0.1 V 1.3
1.5 V ± 0.1 V 1
Data high 1.8 V ± 0.15 V 1
2.5 V ± 0.2 V 0.5
3.3 V ± 0.3 V 0.5
0.8 V 1
1.2 V ± 0.1 V 1.2
1.5 V ± 0.1 V 1
tsu Setup time before CLK↑Data low ns
1.8 V ± 0.15 V 1
2.5 V ± 0.2 V 1
3.3 V ± 0.3 V 1
0.8 V 1
1.2 V ± 0.1 V 0.5
1.5 V ± 0.1 V 0.5
PRE or CLR inactive 1.8 V ± 0.15 V 0.5
2.5 V ± 0.2 V 0.5
3.3 V ± 0.3 V 0.5
0.8 V 0
1.2 V ± 0.1 V 0
1.5 V ± 0.1 V 0
thHold time, data after CLK↑ns
1.8 V ± 0.15 V 0
2.5 V ± 0.2 V 0
3.3 V ± 0.3 V 0
(1) Minimum and maximum values are for TA= –40°C to +85°C
(2) Typicals are for TA= 25°C
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6.8 Switching Characteristics, CL= 5 pF
over recommended operating free-air temperature range, CL= 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
FROM TO
PARAMETER VCC TAMIN TYP MAX UNIT
(INPUT) (OUTPUT)
0.8 V TA= 25°C 60
TA= 25°C 80
1.2 V ± 0.1 V TA= –40°C to 85°C 60
TA= 25°C 125
1.5 V ± 0.1 V TA= –40°C to 85°C 90
fmax TA= 25°C 150 MHz
1.8 V ± 0.15 V TA= –40°C to 85°C 120
TA= 25°C 180
2.5 V ± 0.2 V TA= –40°C to 85°C 160
TA= 25°C 190
3.3 V ± 0.3 V TA= –40°C to 85°C 180
0.8 V TA= 25°C 31
TA= 25°C 2 10 20
1.2 V ± 0.1 V TA= –40°C to 85°C 2.7 20.4
TA= 25°C 2 6 12
1.5 V ± 0.1 V TA= –40°C to 85°C 1.9 12.4
Q TA= 25°C 2 5 9
1.8 V ± 0.15 V TA= –40°C to 85°C 1.4 9.5
TA= 25°C 2 3 6
2.5 V ± 0.2 V TA= –40°C to 85°C 1.1 6.2
TA= 25°C 2 3 4
3.3 V ± 0.3 V TA= –40°C to 85°C 1 4.7
CLK 0.8 V TA= 25°C 28
TA= 25°C 2 9 19
1.2 V ± 0.1 V TA= –40°C to 85°C 2.4 19
TA= 25°C 2 6 11
1.5 V ± 0.1 V TA= –40°C to 85°C 1.6 11.8
tpd Q TA= 25°C 2 5 9 ns
1.8 V ± 0.15 V TA= –40°C to 85°C 1.3 9
TA= 25°C 2 3 6
2.5 V ± 0.2 V TA= –40°C to 85°C 1.1 6
TA= 25°C 2 3 4
3.3 V ± 0.3 V TA= –40°C to 85°C 1 4.6
0.8 V TA= 25°C 26
TA= 25°C 2 9 20
1.2 V ± 0.1 V TA= –40°C to 85°C 2 20
TA= 25°C 2 6 12
1.5 V ± 0.1 V TA= –40°C to 85°C 1.5 13
PRE or CLR Q or Q TA= 25°C 2 5 9
1.8 V ± 0.15 V TA= –40°C to 85°C 1.3 10
TA= 25°C 2 3 6
2.5 V ± 0.2 V TA= –40°C to 85°C 1 7
TA= 25°C 2 3 5
3.3 V ± 0.3 V TA= –40°C to 85°C 1 5
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6.9 Switching Characteristics, CL= 10 pF
over recommended operating free-air temperature range, CL= 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
FROM TO
PARAMETER VCC TAMIN TYP MAX UNIT
(INPUT) (OUTPUT)
0.8 V TA= 25°C 46
TA= 25°C 65
1.2 V ± 0.1 V TA= –40°C to 85°C 50
TA= 25°C 95
1.5 V ± 0.1 V TA= –40°C to 85°C 55
fmax TA= 25°C 110 MHz
1.8 V ± 0.15 V TA= –40°C to 85°C 60
TA= 25°C 170
2.5 V ± 0.2 V TA= –40°C to 85°C 130
TA= 25°C 180
3.3 V ± 0.3 V TA= –40°C to 85°C 160
0.8 V TA= 25°C 33
TA= 25°C 2 10 22
1.2 V ± 0.1 V TA= –40°C to 85°C 3.4 21.8
TA= 25°C 2 7 13
1.5 V ± 0.1 V TA= –40°C to 85°C 2.4 13.5
Q TA= 25°C 2 6 10
1.8 V ± 0.15 V TA= –40°C to 85°C 1.9 10.4
TA= 25°C 2 4 6
2.5 V ± 0.2 V TA= –40°C to 85°C 1.5 7
TA= 25°C 2 3 5
3.3 V ± 0.3 V TA= –40°C to 85°C 1.2 5.3
CLK 0.8 V TA= 25°C 30
TA= 25°C 2 10 20
1.2 V ± 0.1 V TA= –40°C to 85°C 3 20.3
TA= 25°C 2 7 12
1.5 V ± 0.1 V TA= –40°C to 85°C 2.2 12.8
tpd Q TA= 25°C 2 5 9 ns
1.8 V ± 0.15 V TA= –40°C to 85°C 1.8 9.9
TA= 25°C 2 4 6
2.5 V ± 0.2 V TA= –40°C to 85°C 1.3 6.7
TA= 25°C 2 3 5
3.3 V ± 0.3 V TA= –40°C to 85°C 1.1 5.2
0.8 V TA= 25°C 29
TA= 25°C 2 10 21
1.2 V ± 0.1 V TA= –40°C to 85°C 2 21.4
TA= 25°C 2 7 13
1.5 V ± 0.1 V TA= –40°C to 85°C 2 13.8
PRE or CLR Q or Q TA= 25°C 2 5 10
1.8 V ± 0.15 V TA= –40°C to 85°C 2 10.8
TA= 25°C 2 4 7
2.5 V ± 0.2 V TA= –40°C to 85°C 1.5 7.4
TA= 25°C 2 3 5
3.3 V ± 0.3 V TA= –40°C to 85°C 1.5 5.8
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6.10 Switching Characteristics, CL= 15 pF
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
FROM TO
PARAMETER VCC TAMIN TYP MAX UNIT
(INPUT) (OUTPUT)
0.8 V TA= 25°C 41
TA= 25°C 75
1.2 V ± 0.1 V TA= –40°C to 85°C 50
TA= 25°C 95
1.5 V ± 0.1 V TA= –40°C to 85°C 55
fmax TA= 25°C 100 MHz
1.8 V ± 0.15 V TA= –40°C to 85°C 60
TA= 25°C 150
2.5 V ± 0.2 V TA= –40°C to 85°C 130
TA= 25°C 200
3.3 V ± 0.3 V TA= –40°C to 85°C 160
0.8 V TA= 25°C 35
TA= 25°C 2 12 23.1
1.2 V ± 0.1 V TA= –40°C to 85°C 4.1 23.2
TA= 25°C 2 8 14.1
1.5 V ± 0.1 V TA= –40°C to 85°C 2.9 14.6
Q TA= 25°C 2 6 10.7
1.8 V ± 0.15 V TA= –40°C to 85°C 2.4 11.3
TA= 25°C 2 4 7
2.5 V ± 0.2 V TA= –40°C to 85°C 1.9 7.6
TA= 25°C 2 4 5.4
3.3 V ± 0.3 V TA= –40°C to 85°C 1.6 5.9
CLK 0.8 V TA= 25°C 32
TA= 25°C 2 11 21.8
1.2 V ± 0.1 V TA= –40°C to 85°C 3.7 21.8
TA= 25°C 2 7 13.5
1.5 V ± 0.1 V TA= –40°C to 85°C 2.6 14
tpd Q TA= 25°C 2 6 10.4 ns
1.8 V ± 0.15 V TA= –40°C to 85°C 2.2 10.9
TA= 25°C 2 4 7.1
2.5 V ± 0.2 V TA= –40°C to 85°C 1.7 7.5
TA= 25°C 2 3 5.4
3.3 V ± 0.3 V TA= –40°C to 85°C 1.4 5.8
0.8 V TA= 25°C 31
TA= 25°C 2 11 23
1.2 V ± 0.1 V TA= –40°C to 85°C 2 22.9
TA= 25°C 2 7 14
1.5 V ± 0.1 V TA= –40°C to 85°C 2 14.9
PRE or CLR Q or Q TA= 25°C 2 6 11
1.8 V ± 0.15 V TA= –40°C to 85°C 2 11.7
TA= 25°C 2 4 7
2.5 V ± 0.2 V TA= –40°C to 85°C 2 8.1
TA= 25°C 2 4 6
3.3 V ± 0.3 V TA= –40°C to 85°C 1.5 6.4
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6.11 Switching Characteristics, CL= 30 pF
over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
FROM TO
PARAMETER VCC TAMIN TYP MAX UNIT
(INPUT) (OUTPUT)
0.8 V TA= 25°C 21
TA= 25°C 50
1.2 V ± 0.1 V TA= –40°C to 85°C 40
TA= 25°C 60
1.5 V ± 0.1 V TA= –40°C to 85°C 50
fmax TA= 25°C 75 MHz
1.8 V ± 0.15 V TA= –40°C to 85°C 70
TA= 25°C 100
2.5 V ± 0.2 V TA= –40°C to 85°C 90
TA= 25°C 100
3.3 V ± 0.3 V TA= –40°C to 85°C 90
0.8 V TA= 25°C 32
TA= 25°C 3 14 27
1.2 V ± 0.1 V TA= –40°C to 85°C 5.9 27
TA= 25°C 3 10 17
1.5 V ± 0.1 V TA= –40°C to 85°C 4.4 17.2
Q TA= 25°C 3 8 13
1.8 V ± 0.15 V TA= –40°C to 85°C 3.6 13.4
TA= 25°C 3 6 9
2.5 V ± 0.2 V TA= –40°C to 85°C 3 9.2
TA= 25°C 3 5 7
3.3 V ± 0.3 V TA= –40°C to 85°C 2.6 7.2
CLK 0.8 V TA= 25°C 40
TA= 25°C 3 13 26
1.2 V ± 0.1 V TA= –40°C to 85°C 5.5 25.9
TA= 25°C 3 9 16
1.5 V ± 0.1 V TA= –40°C to 85°C 4.1 16.8
tpd Q TA= 25°C 3 7 13 ns
1.8 V ± 0.15 V TA= –40°C to 85°C 3.5 13.2
TA= 25°C 3 5 9
2.5 V ± 0.2 V TA= –40°C to 85°C 2.7 9.2
TA= 25°C 3 5 7
3.3 V ± 0.3 V TA= –40°C to 85°C 2.4 7.2
0.8 V TA= 25°C 38
TA= 25°C 3 13 26
1.2 V ± 0.1 V TA= –40°C to 85°C 3 27
TA= 25°C 3 9 17
1.5 V ± 0.1 V TA= –40°C to 85°C 3 17.4
PRE or CLR Q or Q TA= 25°C 3 8 13
1.8 V ± 0.15 V TA= –40°C to 85°C 3 14
TA= 25°C 3 6 9
2.5 V ± 0.2 V TA= –40°C to 85°C 3 10
TA= 25°C 3 5 7
3.3 V ± 0.3 V TA= –40°C to 85°C 2.5 8
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: SN74AUP1G74
l TEXAS INSTRUMENTS C 100% Normahzed Power Consumpho AUF Devme Devlce
LVC
AUP
LVC
3.3-V
Logic(1)
0%
20%
40%
60%
80%
100%
Device
Normalized Power Consumption
AUP
AUP
3.3-V
Logic(1)
0%
20%
40%
60%
80%
100%
Device
Normalized Power Consumption
SN74AUP1G74
SCES644D –MARCH 2006–REVISED DECEMBER 2015
www.ti.com
6.12 Operating Characteristics
TA= 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
0.8 V 5.5
1.2 V ± 0.1 V 5.5
1.5 V ± 0.1 V 5.5
Cpd Power dissipation capacitance f = 10 MHz pF
1.8 V ± 0.15 V 5.5
2.5 V ± 0.2 V 5.5
3.3 V ± 0.3 V 5.5
6.13 Typical Characteristics
(1) Single, dual and triple gates (1) Single, dual and triple gates
Figure 1. Static Power Consumption Figure 2. Dynamic Power Consumption
for AUP Devices (µA) for AUP Devices (pF)
12 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G74
l TEXAS INSTRUMENTS From Oulput Under Tesl CL (see Nola A) I LOAD CIRC
VM
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
1 MΩ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Output
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. All parameters and waveforms are not applicable to all devices.
VMVM
VMVM
VM
5, 10, 15, 30 pF
VCC/2
VCC
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
CL
VM
VI
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
th
tsu
Data Input
Timing Input
VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2 VCC/2
VCC/2
VCC/2
VCC
VCC/2
SN74AUP1G74
www.ti.com
SCES644D –MARCH 2006–REVISED DECEMBER 2015
7 Parameter Measurement Information
7.1 Propagation Delays, Setup and Hold Times, and Pulse Width)
Figure 3. Load Circuit and Voltage Waveforms
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: SN74AUP1G74
l TEXAS INSTRUMENTS 51 From Output Under Test (see CL Note A) I LOAD CIRCUIT Vcc:l.2V v v = 0.3 v CC :0.1 v cL 5,10,15,31on 5,10,15,30 pF 5, vM vcdz vwz VI Vcc Vcc vA 0.1 v 0.1 v NOTES. A pnmuo Output Control Output Wavelorm 1 51 at 2 chc (see Note 5) Output Wavetprm 2 51 at GND (see Note B) ENA LOW- A c:L metuees prppe and pp capacttance. Wavetorm 1 ts tpran output wtth mternat candtt Wavelurm 2 ts tpran output wtth mternat ccmdtt AH mput putses are supplted py peneratprs hav The outputs are measured me at a ttme wtth a tea and tpuz are the same as “,5. thL and tpzH are the same as [2,, AH parameters and wavelorms are npt apphcab
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V∆
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V∆
VOH − V∆
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control VCC/2 VCC/2
VCC/2
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
TEST S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 kΩ
5 kΩ
2 × VCC
SN74AUP1G74
SCES644D –MARCH 2006–REVISED DECEMBER 2015
www.ti.com
7.2 Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
14 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G74
l TEXAS INSTRUMENTS YGD U
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
CLR
CLK
D
PRE
Q
Q
C
6
2
7
3
5
1
SN74AUP1G74
www.ti.com
SCES644D –MARCH 2006–REVISED DECEMBER 2015
8 Detailed Description
8.1 Overview
This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. When both the CLR and PRE
inputs are set low, the CLR input will override the PRE input.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
Pin numbers shown are for the DCU and DQE packages
8.3 Feature Description
This device is available in the Texas Instrument's NanoStar package. It has low static-power consumption of
0.9 uA maximum. It has low noise with overshoot and undershoot at less than ten percent of VCC. It supports
partial-power-down mode operation, which is specified by Ioff. The Schmitt-trigger inputs allow for slow or noisy
input signals. The device has a wide operating voltage range of 0.8 V to 3.6 V, and is optimized for 3.3 V. It has
low propagation delay of 5 ns maximum at 3.3 V.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1G74.
Table 1. Function Table
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
X L X X L H
H H ↑H H L
H H ↑L L H
H H L X Q0Q0
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: SN74AUP1G74
‘5‘ TEXAS INSTRUMENTS
SN74AUP1G17
VCC
1 F
10 k
VCC
A Y CLK
D
Q
GND
VCC
PRE
CLR
Q
SN74AUP1G74
VCC
0.1 F
MCU
SN74AUP1G74
SCES644D –MARCH 2006–REVISED DECEMBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AUP1G74 can be used to control a power button input. Tying Q to D will switch the output between
high and low each time that a high signal is sent to CLK from the push button.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin must be connected
directly to VCC to be inactive.
9.2 Typical Power Button Circuit
Figure 5. Device Power Button Circuit
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the
high drive will also create faster edges into light loads so routing and load conditions must be considered to
prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions.
– For specified high and low levels, see (VIH and VIL)inRecommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 4.6 V at any valid VCC.
2. Recommend Output Conditions:
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
16 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G74
l TEXAS INSTRUMENTS Vollige —v "Mai ns
VCC
Unused Input
Input
Output Output
Input
Unused Input
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45
Time − ns
Voltage − V
OutputInput
SN74AUP1G74
www.ti.com
SCES644D –MARCH 2006–REVISED DECEMBER 2015
Typical Power Button Circuit (continued)
9.2.3 Application Curve
AUP1G08 data at CL= 15 pF
Figure 6. Switching Characteristics at 25 MHz
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
TI recommends a 0.1-μF capacitor, and if there are multiple VCC pins, then TI recommends a 0.01-μF or
0.022-μF capacitor for each power pin. It is ok to parallel multiple bypass caps to reject different frequencies of
noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor must be installed as
close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on
the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more
convenient.
11.2 Layout Example
Figure 7. Layout Diagram
Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: SN74AUP1G74
l TEXAS INSTRUMENTS
SN74AUP1G74
SCES644D –MARCH 2006–REVISED DECEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs,SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
18 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G74
I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74AUP1G74DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 H74R
SN74AUP1G74DCURG4 ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 H74R
SN74AUP1G74DQER ACTIVE X2SON DQE 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 HS
SN74AUP1G74RSER ACTIVE UQFN RSE 8 5000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 HS
SN74AUP1G74YFPR ACTIVE DSBGA YFP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 HSN
SN74AUP1G74YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 HSN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension destgned to accommodate the component tengtti K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pttch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUP1G74DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
SN74AUP1G74DQER X2SON DQE 8 5000 180.0 8.4 1.2 1.6 0.55 4.0 8.0 Q1
SN74AUP1G74RSER UQFN RSE 8 5000 180.0 8.4 1.7 1.7 0.7 4.0 8.0 Q2
SN74AUP1G74YFPR DSBGA YFP 8 3000 178.0 9.2 0.9 1.75 0.6 4.0 8.0 Q1
SN74AUP1G74YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jan-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP1G74DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
SN74AUP1G74DQER X2SON DQE 8 5000 202.0 201.0 28.0
SN74AUP1G74RSER UQFN RSE 8 5000 202.0 201.0 28.0
SN74AUP1G74YFPR DSBGA YFP 8 3000 220.0 220.0 35.0
SN74AUP1G74YZPR DSBGA YZP 8 3000 220.0 220.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Jan-2020
Pack Materials-Page 2
MECHANICAL DATA DCU (R—PDSO—GB) PLASTIC SMALL—OUTLINE PACKAGE (DIE DOWN) F Wngiw 31117 0,15 \0M 7 7,40 310 2,20 3,00 i Gage Pm J i 3W1 / __'—_“ NDEX AREA 1 99 Do $1212]: : Q% J L W 4200503” z7/05 NOTES, A AH Hnec' dimensmrs in m'hmekers B Tris drawing is sum 0 Change mm: malice, 0 Body dimCHSiOnS do mi inciudc mom flash or oromsm Moid tics» and pvctrusmn srai not cxcccd o it) 30V m D FuHs wiwu JEDEC M0457 vuiiuliovi CA ‘4‘ TEXAS INSTRUMENTS www.(i. com
I-I
www.ti.com
PACKAGE OUTLINE
C
1.05
0.95
1.45
1.35
0.40
0.34
0.05
0.00
2X 1.05
6X 0.35
7X 0.35
0.25
8X 0.20
0.15
0.45
0.35
(0.13) TYP
X2SON - 0.4 mm max heightDQE0008A
PLASTIC SMALL OUTLINE - NO LEAD
4225204/A 08/2019
0.05 C
0.07 C A B
0.05
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package complies to JEDEC MO-287 variation X2EAF.
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
PIN 1 ID
SYMM
SYMM
1
45
8
SCALE 9.000
A
B
www.ti.com
EXAMPLE BOARD LAYOUT
6X (0.35)
(R0.05) TYP
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
7X (0.5)
8X (0.175)
(0.9)
(0.6)
X2SON - 0.4 mm max heightDQE0008A
PLASTIC SMALL OUTLINE - NO LEAD
4225204/A 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
SEE SOLDER MASK
DETAIL
1
45
8
METAL EDGE
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DEFINED
SOLDER MASK DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
7X (0.5)
8X (0.175)
6X (0.35)
(0.9)
(R0.05) TYP
(0.6)
X2SON - 0.4 mm max heightDQE0008A
PLASTIC SMALL OUTLINE - NO LEAD
4225204/A 08/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.075 MM THICK STENCIL
SCALE: 40X
SYMM
SYMM
1
45
8
<3 i-iii="">
www.ti.com
PACKAGE OUTLINE
0.5 MAX
0.19
0.13
1.2
TYP
0.4 TYP
0.4 TYP
8X 0.25
0.21
0.30
0.25
E
D
4225242/A 08/2019
DSBGA - 0.5 mm max heightYFP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
0.05 C
A
12
0.015 C A B
SYMM
SYMM
B
C
D
SCALE 10.000
A
B
C
D: Max =
E: Max =
1.59 mm, Min =
0.79 mm, Min =
1.53 mm
0.73 mm
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EXAMPLE BOARD LAYOUT
0.05 MIN
0.05 MAX
8X ( 0.23) (0.4) TYP
(0.4) TYP
( 0.23)
SOLDER MASK
OPENING
( 0.23)
METAL
4225242/A 08/2019
DSBGA - 0.5 mm max heightYFP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
SOLDER MASK DETAILS
NOT TO SCALE
SYMM
SYMM
C
1 2
A
B
D
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
NON-SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
EXPOSED
METAL
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EXAMPLE STENCIL DESIGN
(0.4) TYP
(0.4) TYP
8X ( 0.25) (R0.05) TYP
4225242/A 08/2019
DSBGA - 0.5 mm max heightYFP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
12
C
A
B
D
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 50X
METAL
TYP
--I DJ]; 5771:7774 F \x““+‘ ‘w w 5®
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PACKAGE OUTLINE
C
0.6
0.5
0.05
0.00
2X
1
4X 0.5
6X 0.4
0.3
4X 0.3
0.2
2X 0.45
0.35
2X 0.25
0.15
2X 0.35
0.25
B1.55
1.45 A
1.55
1.45
(0.12)
TYP
UQFN - 0.6 mm max heightRSE0008A
PLASTIC QUAD FLATPACK - NO LEAD
4220323/B 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.05 C
1
3
4
8
0.1 C A B
0.05 C
5
7
SYMM
SYMM
0.1 C A B
0.05 C
PIN 1 ID
(45 X 0.1)
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
0.1 C A B
0.05 C
SCALE 7.000
www.ti.com
EXAMPLE BOARD LAYOUT
2X (0.6)
2X (0.3)
2X
(0.2)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
6X (0.55)
4X (0.25)
4X (0.5)
(1.35)
(1.3)
(R0.05) TYP
UQFN - 0.6 mm max heightRSE0008A
PLASTIC QUAD FLATPACK - NO LEAD
4220323/B 03/2018
SYMM
1
35
8
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
4
7
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NOT TO SCALE
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
6X (0.55)
4X (0.25)
2X (0.6)
2X
(0.3)
(1.35)
(1.3)
2X (0.2)
4X (0.5)
(R0.05) TYP
UQFN - 0.6 mm max heightRSE0008A
PLASTIC QUAD FLATPACK - NO LEAD
4220323/B 03/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
1
3
4
5
7
8
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICKNESS
SCALE: 30X
WT
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PACKAGE OUTLINE
C
0.5 MAX
0.19
0.15
1.5
TYP
0.5 TYP
8X 0.25
0.21
0.5
TYP
B E A
D
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
BALL A1
CORNER
SEATING PLANE
BALL TYP 0.05 C
B
1 2
0.015 C A B
SYMM
SYMM
C
A
D
SCALE 8.000
D: Max =
E: Max =
1.918 mm, Min =
0.918 mm, Min =
1.858 mm
0.858 mm
www.ti.com
EXAMPLE BOARD LAYOUT
8X ( 0.23) (0.5) TYP
(0.5) TYP
( 0.23)
METAL
0.05 MAX ( 0.23)
SOLDER MASK
OPENING
0.05 MIN
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
12
A
B
C
D
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
www.ti.com
EXAMPLE STENCIL DESIGN
(0.5)
TYP
(0.5) TYP
8X ( 0.25) (R0.05) TYP
METAL
TYP
4223082/A 07/2016
DSBGA - 0.5 mm max heightYZP0008
DIE SIZE BALL GRID ARRAY
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
12
A
B
C
D
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