Texas Instruments 的 SN65LV1023A, 1224B 规格书

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I TEXAS INSTRUMENTS TC LKiR/T: TCLK 25 24 23 DB Package SNESLVID23A 2‘ Serialiler ‘9 H3 ‘7 t6 t5 UU>>U>UU>T UUUUUUUU UUUUUUUU DBDDDDDD

SYNC1

SYNC2

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

TCLK_R/F

TCLK

DVCC

AVCC

AGND

PWRDN

AGND

DO+

DO−

AGND

DEN

AGND

AVCC

DGND

DB Package

SN65LV1023A

Serializer

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

AGND

PWRDN

AGND

DO+

DO−

AGND

DEN

AGND

RHB Package

SN65LV1023A

Serializer

(Top View)

DIN0

SYNC2

SYNC1

DVCC

AVCC

DIN9

TCLK_R/F

TCLK

DGND

AVCC

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

Check for Samples: SN65LV1023A SN65LV1224B

1FEATURES DESCRIPTION

• 100-Mbps to 660-Mbps Serial LVDS Data

Payload Bandwidth at 10-MHz to 66-MHz The SN65LV1023A serializer and SN65LV1224B

System Clock deserializer comprise a 10-bit serdes chipset

designed to transmit and receive serial data over

• Pin-Compatible Superset of LVDS differential backplanes at equivalent parallel

DS92LV1023/DS92LV1224 word rates from 10 MHz to 66 MHz. Including

• Chipset (Serializer/Deserializer) Power overhead, this translates into a serial data rate

Consumption <450 mW (Typ) at 66 MHz between 120-Mbps and 792-Mbps payload encoded

• Synchronization Mode for Faster Lock throughput.

• Lock Indicator Upon power up, the chipset link can be initialized via

a synchronization mode with internally generated

• No External Components Required for PLL SYNC patterns or the deserializer can be allowed to

• 28-Pin SSOP and Space Saving 5 × 5 mm QFN synchronize to random data. By using the

Packages Available synchronization mode, the deserializer establishes

• Industrial Temperature Qualified, lock within specified, shorter time parameters.

TA=−40°C to 85°C The device can be entered into a power-down state

• Programmable Edge Trigger on Clock when no data transfer is required. Alternatively, a

• Flow-Through Pinout for Easy PCB Layout mode is available to place the output pins in the

high-impedance state without losing PLL lock.

APPLICATIONS The SN65LV1023A and SN65LV1224B are

• Wireless Base Station characterized for operation over ambient air

• Backplane Interconnect temperature of –40°C to 85°C.

• DSLAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

‘5‘ TEXAS INSTRUMENTS =25. :23 5%. T x x x x i x x 4,7 TCLKiﬁ/F SVNC1 SVNC2

SYNC1

SYNC2

DEN

A+

A−

PLL

LVDS

Timing /

Control

Input Latch

Parallel-to-Serial

TCLK_R/F

DIN

Y+

Y−

PLL Timing /

Control

Output Latch

Serial-to-Parallel

Clock

Recovery

DOUT

REN

REFCLK

LOCK

RCLK_R/F

RCLK

(10 MHz to

66 MHz)

TCLK

(10 MHz to

66 MHz)

SN65LV1224BSN65LV1023A

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BLOCK DIAGRAMS

Product Folder Link(s): SN65LV1023A SN65LV1224B

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SN65LV1023A

SN65LV1224B

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SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

FUNCTIONAL DESCRIPTION

The SN65LV1023A and SN65LV1224B are a 10-bit serializer/deserializer chipset designed to transmit data over

differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset

has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down

mode, and high-impedance mode. The following sections describe each state of operation.

INITIALIZATION MODE

Initialization of both devices must occur before data transmission can commence. Initialization refers to

synchronization of the serializer and deserializer PLLs to local clocks.

When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state,

while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device

begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an

external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs

remain in the high-impedance state, while the PLL locks to the TCLK.

SYNCHRONIZATION MODE

The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be

accomplished in one of two ways:

•Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six

ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the

deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC

patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid SYNC1 or

SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent.

When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock

information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC

patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes

low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the

deserializer LOCK output directly to SYNC1 or SYNC2.

•Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the

serializer to send special SYNC patterns. This allows the SN65LV1224B to operate in open-loop applications.

Equally important is the deserializer’s ability to support hot insertion into a running backplane. In the

open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because lock

time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary constraint

on the random lock time is the initial phase relation between the incoming data and the REFCLK when the

deserializer powers up.

The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer

could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive

multitransition (RMT); see Figure 1 for RMT examples. This occurs when more than one low-high transition takes

place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data

pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists.

Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern

changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock,

the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle.

The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary (stop/start

bits) at the same position.

The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive

cycles. Then the deserializer goes out of lock and hunts for the new data boundary (stop/start bits). In the event

of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a

high-impedance state. The user’s system should monitor the LOCK pin in order to detect a loss of

synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if

reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as

previously noted.

Product Folder Link(s): SN65LV1023A SN65LV1224B

‘5‘ TEXAS INSTRUMENTS kﬂf\?/I\XXXXXXX>\){\ \XXXX%\ I XXYXXXX/ I\)‘(\ J" XXYXXXXXXXX/

Start

Bit

Stop

Bit

DIN0 Held Low and DIN1 Held High

DIN0 DIN1

Start

Bit

Stop

Bit

Start

Bit

Stop

Bit

DIN4 Held Low and DIN5 Held High

DIN4 DIN5

Start

Bit

Stop

Bit

Start

Bit

Stop

Bit

DIN8 Held Low and DIN9 Held High

DIN8 DIN9

Start

Bit

Stop

Bit

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

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Figure 1. RMT Pattern Examples

DATA TRANSMISSION MODE

After initialization and synchronization, the serializer accepts parallel data from inputs DIN0–DIN9. The serializer

uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to

strobe incoming data. If either of the SYNC inputs is high for six TCLK cycles, the data at DIN0−DIN9 is ignored

regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent.

After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the

embedded clock bits in the serial stream.

The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±) at

12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mbps. Because

only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz,

the useful data rate is 66 × 10 = 660 Mbps. The data source, which provides TCLK, must be in the range of 10

MHz to 66 MHz.

The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes.

The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low.

When DEN is driven low, the serializer output pins enter the high-impedance state.

Product Folder Link(s): SN65LV1023A SN65LV1224B

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SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to

the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise

ROUT0–ROUT9 is invalid. The ROUT0−ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be

used is selected by the RCLK_R/F input. The ROUT0–ROUT9, LOCK and RCLK outputs can drive a maximum of

three CMOS input gates (15-pF load. total for all three) with a 66-MHz clock.

POWER DOWN

When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the

power-down state, a low-power sleep mode, to reduce power consumption. The deserializer enters power down

when you drive PWRDN and REN low. The serializer enters power down when you drive PWRDN low. In power

down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces

supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high.

Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and

resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer

initialize and drives LOCK high until lock to the LVDS clock occurs.

HIGH-IMPEDANCE MODE

The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins

(DO+ and DO−) into a high-impedance state. When you drive DEN high, the serializer returns to the previous

state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin

is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins

(ROUT0–ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting

the state of the PLL.

Table 1. Deserializer Truth Table

INPUTS OUTPUTS

PWRDN REB ROUT(0:9)(1) LOCK (2) RCLK(3) (1)

H H Z H Z

H H Active L Active

L X Z Z Z

H L Z Active Z

(1) ROUT and RCLK are 3-stated when LOCK is asserted high.

(2) LOCK output reflects the state of the deserializer with regard to the selected data stream.

(3) RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by

RCLK_R/F.

FAILSAFE BIASING FOR THE SN65LV1224B

The SN65LV1224B has an input threshold sensitivity of ±50 mV. This allows for greater differential noise margin

in the SN65LV1224B. However, in cases where the receiver input is not being actively driven, the increased

sensitivity of the SN65LV1224B can pickup noise as a signal and cause unintentional locking. This may occur

when the input cable is disconnected. The SN65LV1224B has an on-chip fail-safe circuit that drives the serial

input and LOCK signal high. The response time of the fail-safe circuit depends on interconnect characteristics.

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

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PIN FUNCTIONS

PIN I/O DESCRIPTION

DB PACKAGE RHB PACKAGE

SERIALIZER

18, 20, 23, 25 17, 19, 22, 24 AGND Analog circuit ground (PLL and analog circuits)

17, 26 16, 25 AVCC Analog circuit power supply (PLL and analog circuits)

LVTTL logic input. Low puts the LVDS serial output into the high-impedance state.

19 18 DEN High enables serial data output.

15, 16 12, 13, 14, 15 DGND Digital circuit ground

3−12 32, 1−9 DIN0 −DIN9 Parallel LVTTL data inputs

21 20 DO−Inverting LVDS differential output

22 21 DO+ Noninverting LVDS differential output

27, 28 26, 27, 28, 29 DVCC Digital circuit power supply

LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs

24 23 PWRDN into the high-impedance state, putting the device into a low-power mode.

LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of

the two pins is asserted high for 6 cycles of TCLK, the serializer initiates

SYNC1, transmission of a minimum 1026 SYNC patterns. If after completion of the

1, 2 30, 31 SYNC2 transmission of 1026 patterns SYNC continues to be asserted, then the

transmission continues until SYNC is driven low and if the time SYNC holds > 6

cycles, another 1026 SYNC pattern transmission initiates.

LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a

13 10 TCLK_R/F TCLK rising-edge data strobe.

LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to

14 11 TCLK 66-MHz clock. TCLK strobes parallel data into the input latch and provides a

reference frequency to the PLL.

DESERIALIZER

1, 12, 13 10, 11, 28, 29, 30 AGND Analog circuit ground (PLL and analog circuits)

4, 11 1, 8, 9 AVCC Analog circuit power supply (PLL and analog circuits)

14, 20, 22 12, 13, 19, 21 DGND Digital circuit ground

21, 23 20, 22 DVCC Digital circuit power supply

LVTTL level output. LOCK goes low when the deserializer PLL locks onto the

10 7 LOCK embedded clock edge.

LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a

high-impedance state, putting the device into a low-power mode. To initiate power

7 4 PWRDN down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low,

the device is in the power down state.

LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an

2 31 RCLK_R/F RCLK rising-edge data strobe.

9 6 RCLK LVTTL level output recovered clock. Use RCLK to strobe ROUTx.

LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL

3 32 REFCLK frequency.

LVTTL logic input. Low places ROUT0−ROUT9 and RCLK in the high-impedance

8 5 REN state.

5 2 RI+ Serial data input. Noninverting LVDS differential input

6 3 RI– Serial data input. Inverting LVDS differential input

28−24, 19−15 27−23, 18−14 ROUT0−ROUT9 Parallel LVTTL data outputs

Product Folder Link(s): SN65LV1023A SN65LV1224B

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VID

2.4 *ǒVID

2Ǔ

SN65LV1023A

SN65LV1224B

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SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)(1)

UNIT

VCC to GND −0.3 V to 4 V

LVTTL input voltage −0.3 V to (VCC + 0.3 V)

LVTTL output voltage −0.3 V to (VCC + 0.3 V)

LVDS receiver input voltage −0.3 V to 3.9 V

LVDS driver output voltage −0.3 V to 3.9 V

LVDS output short circuit duration 10 ms

HBM up to 6 kV

Electrostatic discharge: MM up to 200 V

Junction temperature 150°C

Storage temperature −65°C to 150°C

DB package maximum package TA= 25°C 1.27 W

power dissipation

RHB package maximum package TA= 25°C 2.85 W

power dissipation

DB package derating 10.3 mW/°C above 25°C

RHB package derating 23.6 mW/°C above 25°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCC (1) Supply voltage 3 3.3 3.6 V

Receiver input voltage range 0 2.4 V

VCM Receiver input common mode range V

Supply noise voltage 100 mVPP

TAOperating free-air temperature –40 25 °C

(1) By design, DVCC and AVCC are separated internally and does not matter what the difference is for |DVCC−AVCC|, as long as both are

within 3 V to 3.6 V.

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS

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SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

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ELECTRICAL CHARACTERISTICS

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS(1)

VIH High-level input voltage 2 VCC V

VIL Low-level input voltage GND 0.8 V

VCL Input clamp voltage ICL =−18 mA -0.86 –1.5 V

IIN Input current, (2) VIN = 0 V or 3.6 V –200 ±100 200 μA

DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS(3)

VIH High-level input voltage 2 VCC V

VIL Low-level input voltage GND 0.8 V

VCL Input clamp voltage ICL =−18 mA -0.62 –1.5 V

Input current (pull-up and

IIN VIN = 0 V or 3.6 V –200 200 μA

pull-down resistors on inputs)

VOH High-level output voltage IOH =−5 mA 2.2 3 VCC V

VOL Low-level output voltage IOL = 5 mA GND 0.25 0.5 V

IOS Output short-circuit current VOUT = 0 V –15 –47 –85 mA

IOZ High-impedance output current PWRDN or REN = 0.8 V, VOUT = 0 V or VCC –10 ±1 10 μA

SERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins DO+ and DO−)

Output differential voltage

VOD RL= 27 Ω, See Figure 2 350 450 mV

(DO+)–(DO−)

Output differential voltage

ΔVOD 35 mV

unbalance

VOS Offset voltage 1.1 1.2 1.3 V

ΔVOS Offset voltage unbalance 4.8 35 mV

D0 = 0 V, DINx = high,

IOS Output short circuit current -10 -90 mA

PWRDN and DEN = 2.4 V

PWRDN or DEN = 0.8 V,

IOZ High-impedance output current ±1 10 μA

DO = 0 V or VCC –10

IOX Power-off output current VCC = 0 V, DO = 0 V or 3.6 V -20 ±1 25 μA

COOutput single-ended capacitance 1±20% pF

DESERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins RI+ and RI−)

VTH Differential threshold high voltage VCM = 1.1 V 50 mV

VTL Differential threshold low voltage –50 mV

VIN = 2.4 V, VCC = 3.6 V or 0 V –10 ±1 15

IIN Input current μA

VIN = 0 V, VCC = 3.6 V or 0 V –10 ±0.05 10

CIInput single-ended capacitance 0.5±20% pF

SERIALIZER SUPPLY CURRENT (Applies to Pins DVCC and AVCC)

f = 10 MHz 20 25

Serializer supply current worst

ICCD RL= 27 Ω, See Figure 5 mA

case f = 66 MHz 55 70

ICCXD Serializer supply current PWRDN = 0.8 V 200 500 μA

DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC)

f = 10 MHz 15 35

Deserializer supply current, worst

ICCR CL= 15 pF, See Figure 5 mA

case f = 66 MHz 80 95

Deserializer supply current, power

ICCXR PWRDN = 0.8 V, REN = 0.8 V 0.36 1 mA

down

(1) Apply to DIN0−DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, and DEN

(2) High IIN values are due to pullup and pulldown resistors on the inputs.

(3) Apply to pins PWRDN, RCLK_R/F, REN, and REFCLK = inputs; apply to pins ROUTx, RCLK, and LOCK = outputs

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS

100

200

300

400

500

600

700

800

900

1000

0 20 40 60 80 100 120 140

Termination(RL)- W

V IN-mV

VOD

SN65LV1023A

SN65LV1224B

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SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Figure 2. Typical VOD Curve

SERIALIZER TIMING REQUIREMENTS FOR TCLK

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tTCP Transmit clock period 15.15 T 100 ns

tTCIH Transmit clock high time 0.4T 0.5T 0.6T ns

tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns

tt(CLK) TCLK input transition time 3 6 ns

tJIT TCLK input jitter See Figure 19 150 ps (RMS)

Frequency tolerance -100 +100 ppm

Product Folder Link(s): SN65LV1023A SN65LV1224B

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SERIALIZER SWITCHING CHARACTERISTICS

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tTLH(L) LVDS low-to-high transition time RL= 27 Ω, CL= 10 pF to GND, See 0.2 0.4 ns

Figure 6

tLTHL(L) LVDS high-to-low transition time 0.25 0.4 ns

tsu(DI) DIN0−DIN9 setup to TCLK 0.5 ns

See Figure 9

tsu(DI) DIN0−DIN9 hold from TCLK 4 ns

td(HZ) DO± high-to-high impedance state 2.5 5

delay

td(LZ) DO± low-to-high impedance state 2.5 5

delay RL= 27 Ω, CL= 10 pF to GND, See ns

Figure 10

td(ZH) DO± high-to-high impedance 5 10

state-to-high delay

td(ZL) DO± high-to-high impedance 6.5 10

state-to-low delay

tw(SPW) SYNC pulse duration 6×tTCP ns

See Figure 12

t(PLD) Serializer PLL lock time 1026×tTCP ns

td(S) Serializer delay See Figure 13 tTCP+1 tTCP+2 tTCP+3 ns

230

tDJIT Deterministic jitter RL = 27 Ω, CL= 10 pF to GND ps

150

tRJIT Random jitter RL = 27 Ω, CL= 10 pF to GND 10 19 ps (RMS)

DESERIALIZER TIMING REQUIREMENTS FOR REFCLK

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tRFCP REFCLK period 15.15 T 100 ns

tRFDC REFCLK duty cycle 30% 50% 70%

tt(RF) REFCLK transition time 3 6 ns

Frequency tolerance -100 +100 ppm

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SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

DESERIALIZER SWITCHING CHARACTERISTICS

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER TEST PIN/FREQ MIN TYP MAX UNIT

CONDITIONS

t(RCP) = t(TCP), See

t(RCP) Receiver out clock period RCLK 15.15 100 ns

Figure 13

tTLH(C) CMOS/TTL low-to-high ROUT0−ROUT9 1.2 2.5

CL= 15 pF, CL =

transition time LOCK, RCLK

15 pF, See ns

tTHL(C) CMOS/TTL high-to-low Figure 7 1.1 2.5

transition time

1.75×t(RCP) 1.75×t(RCP)

10 MHz ns

+4.2 +12.6

Deserializer delay, See Room temperature,

td(D) Figure 14 3.3 V 1.75×t(RCP) 1.75×t(RCP)

66 MHz ns

+7.4 +9.7

RCLK 10 MHz 0.4×t(RCP) 0.5×t(RCP)

t(ROS) ROUTx data valid before RCLK RCLK 66 MHz 0.4×t(RCP) 0.5×t(RCP)

See Figure 15 ns

10 MHz −0.4×t(RCP) −0.5×t(RCP)

t(ROH) ROUTx data valid after RCLK 66 MHz −0.4×t(RCP) −0.5×t(RCP)

t(RDC) RCLK duty cycle 40% 50% 60% ns

td(HZ) High-to-high impedance state 6.5 8 ns

delay

td(LZ) Low-to-high impedance state 4.7 8 ns

delay See Figure 16 ROUT0−ROUT9

td(HR) High-impedance state to high 5.3 8 ns

delay

td(ZL) High-impedance state to low 4.7 8 ns

delay

10 MHz 850 x tRFCP

Deserializer PLL lock time from

t(DSR1) 66 MHz 850 x tRFCP

PWRDN (with SYNCPAT) μs

See Figure 17,10 MHz 2

Figure 18,

Deserializer PLL lock time from

t(DSR2) 66 MHz 0.303

and (1)

SYNCPAT

High-impedance state to high

td(ZHLK) LOCK 3 ns

delay (power up)

10 MHz 3680

See Figure 19 and

tRNM Deserializer noise margin ps

(2) 66 MHz 540

(1) t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the

powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer

when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify

deserializer PLL performance, tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs.

(2) tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS

TCLK

ODD DIN

EVEN DIN

020 40 60 80

ICC − SupplyCurrent − mA

TCLKFrequency − MHz

SUPPLY CURRENT

TCLKFREQUENCY

ICC

10 MHz,14.732mA

66MHz,48.88mA

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

www.ti.com

TIMING DIAGRAMS AND TEST CIRCUITS

Figure 3. Worst-Case Serializer ICC Test Pattern

Figure 4.

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS 20 % E Vmu = (50+) - (Do i 20 °/. m 0% ov

RCLK

ODD ROUT

EVEN ROUT

80%

20%

80%

20%

tTLH(L)

Vdiff

tTHL(L)

10 pF

DO+

DO−

10 pF

Vdiff = (DO+) − (DO−)

80%

20%

80%

20%

tTLH(C) tTHL(C)

CMOS/TTL Output

15 pF

Deserializer

90%

10%

90%

10%

tt(CLK)

TCLK

tt(CLK)

3 V

0 V

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Figure 5. Worst-Case Deserializer ICC Test Pattern

Figure 6. Serializer LVDS Output Load and Transition Times

Figure 7. Deserializer CMOS/TTL Output Load and Transition Times

Figure 8. Serializer Input Clock Transition Time

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS V 4‘ \ \ W— F ’ 4‘ k w 1 \ u r, I: 2V‘ navﬁ; 1 ‘uam 0' foam # f 1 H7 hm: 4H x ‘ \ \ , , Do: a-sme culput Acli x H

DIN [9:0]

tsu(DI)

TCLK

th(DI)

For TCLK_R/F = Low

Setup Hold 1.5 V1.5 V

tTCP

1.5 V 1.5 V 1.5 V

13.5 Ω

DO+

DO−

Parasitic Package and

Trace Capacitance

DEN

td(ZH)

td(HZ)

1.5 V1.5 V

3 V

0 V

50%50%

1.1 V

VOH

DO±

VOL

1.1 V

td(ZL)

50%

td(LZ)

13.5 Ω

1.1 V

DEN

DO±

TCLK

td(HZ) or td(LZ)

2 V

1026 Cycles

PWRDN 0.8 V

Output Active

tPLD

td(ZH) or td(ZL)

3-State 3-State

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

www.ti.com

Figure 9. Serializer Setup/Hold Times

Figure 10. Serializer High-Impedance State Test Circuit and Timing

Figure 11. Serializer PLL Lock Time and PWRDN High-Impedance State Delays

Product Folder Link(s): SN65LV1023A SN65LV1224B

‘5‘ TEXAS INSTRUMENTS 7‘ XXX: /\/\/\/\/\/ "F—\ :XXXXXX SVNC P aaaaa DATA

tw(SP)

PWRDN

TCLK

REN

SYNC1

SYNC2

DO±

DATA SYNC Pattern

tw(SP) Min. Timing Met

TCLK

SYNC1

SYNC2

DO±

DATASYNC Pattern

Start

Bit D00 − D09 SYMBOL N Stop

Bit

Start

Bit D00 − D09 SYMBOL N−1 Stop

Bit

DIN

td(S)

DIN0 − DIN9 SYMBOL N DIN0 − DIN9 SYMBOL N+1

Timing for TCLK_R/F = High

TCLK

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Figure 12. SYNC Timing Delays

Figure 13. Serializer Delay

Product Folder Link(s): SN65LV1023A SN65LV1224B

‘5‘ TEXAS INSTRUMENTS

Start

Bit D00 − D09 SYMBOL N+2 Stop

Bit 1.2 V

1 V

Start

Bit D00 − D09 SYMBOL N+1 Stop

Bit

Start

Bit D00 − D09 SYMBOL N Stop

Bit

ROUT

tDD

ROUT0 − ROUT9 SYMBOL N−1 ROUT0 − ROUT9 SYMBOL N

Timing for TCLK_R/F = High

RCLK

ROUT0 − ROUT9 SYMBOL N+1

ROUT [9:0]

RCLK

RCLK_R/F = High

tROS

Data Valid

Before RCLK 1.5 V1.5 V

tROH

tLow

tHigh

RCLK

RCLK_R/F = Low

tHigh

tLow

Data Valid

After RCLK

7 V x (LZ/ZL), Open (HZ/ZH) REN

td(ZL)

td(LZ)

1.5 V1.5 V

VOH

VOL

VOL + 0.5 V

VOL

ROUT[9:0]

VOH

td(ZH)

td(HZ)

500 Ω

450 Ω

50 Ω

Scope

VOL + 0.5 V

VOH − 0.5 V VOH − 0.5 V

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

www.ti.com

Figure 14. Deserializer Delay

Figure 15. Deserializer Data Valid Out Times

Figure 16. Deserializer High-Impedance State Test Circuit and Timing

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS 3.5.3.; X X , 3.5.3.9 W ,

ROUT[9:0]

REFCLK

2 V

PWRDN 0.8 V

td(ZHL)

DATA

Not Important

3-State

SYNC Patterns

1.5 V

RI±

LOCK 3-State

3-State3-State

RCLK 3-State3-State

SYNC Symbol or DIN[9:0]

RCLK_R/F = Low

REN

t(DSR1)

td(ZH) or td(ZL) td(HZ) or td(LZ)

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Figure 17. Deserializer PLL Lock Times and PWRDN 3-State Delays

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS Rgm[9:0] a-sméY X X \w \w X X X X m A ‘\

ROUT[9:0]

REFCLK

PWRDN 0.8 V

DATA

Not Important

SYNC Patterns

RI±

LOCK 3-State

3-State3-State

RCLK 3-State3-State

SYNC Symbol or DIN[9:0]

REN

t(DSR2)

VCC

3.6 V

3 V

0 V

1.2 V

1 V

td(ZH) or td(ZL) td(HZ) or td(LZ)

tDJIT

tSW: Setup and Hold Time (Internal Data Sampling Window)

tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK

tRNM: Receiver Noise Margin Time

VTH

RI±VTL

1.2 V

1 V

tDJIT

tRNM tRNM

tSW

Ideal Sampling Position

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

www.ti.com

Figure 18. Deserializer PLL Lock Time From SyncPAT

Figure 19. Receiver LVDS Input Skew Margin

Product Folder Link(s): SN65LV1023A SN65LV1224B

‘5‘ TEXAS INSTRUMENTS

DO+

DO−

DIN Parallel-to-Serial

> TCLK

VOD = (DO+) − (DO−)

Differential Output Signal Is Shown as (DO+) − (DO−)

3.0 V

VDD

PWRDNB

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Figure 20. VOD Diagram

DEVICE STARTUP PROCEDURE

It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a

logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 21.

Figure 21. Device Startup

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS

100 Ω

Serialized Data

Parallel Data In Parallel Data Out

50 Ω

ASICASIC ASIC ASIC

SN65LV1023A

SN65LV1224B

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

www.ti.com

APPLICATION INFORMATION

DIFFERENTIAL TRACES AND TERMINATION

The performance of the SN65LV1023A/SN65LV1224B is affected by the characteristics of the transmission

medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the

media’s characteristics impedance.

Use balanced cables such as twisted pair or differential traces that are ran close together. A balanced cable

picks up noise together and appears to the receiver as common mode. Differential receivers reject

common-mode noise. Keep cables or traces matched in length to help reduce skew.

Running the differential traces close together helps cancel the external magnetic field, as well as maintain a

constant impedance. Avoiding sharp turns and reducing the number of vias also helps.

TOPOLOGIES

There are several topologies that the serializers can operate. Three common examples are shown below.

Figure 22 shows an example of a single-terminated point-to-point connection. Here a single termination resistor

is located at the deserializer end. The resistor value should match that of the characteristic impedance of the

cable or PC board traces. The total load seen by the serializer is 100 Ω. Double termination can be used and

typically reduces reflections compared with single termination. However, it also reduces the differential output

voltage swing.

AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data

stream. Otherwise the ac-capacitors can induce common mode voltage drift due to the dc-unbalanced data

stream.

Figure 22. Single-Terminated Point-to-Point Connection

Figure 23 shows an example of a multidrop configuration. Here there is one transmitter broadcasting data to

multiple receivers. A 50-kΩresistor at the far end terminates the bus.

Figure 23. Multidrop Configuration

Figure 24 shows an example of multiple serializers and deserializers on the same differential bus, such as in a

backplane. This is a multipoint configuration. In this situation, the characteristic impedance of the bus can be

significantly less due to loading. Termination resistors that match the loaded characteristic impedance are

required at each end of the bus. The total load seen by the serializer in this example is 27 Ω.

Product Folder Link(s): SN65LV1023A SN65LV1224B

l TEXAS INSTRUMENTS

54 Ω

ASIC ASIC ASICASIC

54 Ω

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

Figure 24. Multiple Serializers and Deserializers on the Same Differential Bus

SPACER REVISION HISTORY

Changes from Original (September 2004) to Revision A Page

• Changed Figure 17 ............................................................................................................................................................. 17

• Changed Figure 18 ............................................................................................................................................................. 18

Changes from Revision A (January 2005) to Revision B Page

• Added RHB package information ......................................................................................................................................... 1

Changes from Revision B (July 2005) to Revision C Page

• Changed Package description in the Features list. .............................................................................................................. 1

Changes from Revision C (February 2006) to Revision D Page

• Added the Applications List .................................................................................................................................................. 1

• Deleted the DB and RHB packages for Deserializer ............................................................................................................ 1

• Added Figure 2 ..................................................................................................................................................................... 9

• Changed Figure 4 Supply Current vs TCLK Frequency ..................................................................................................... 12

Changes from Revision D (February 2009) to Revision E Page

• Deleted footnote - "The deserializer delay time for all frequencies does not exceed two serial bit times" From td(D) ........ 11

Product Folder Link(s): SN65LV1023A SN65LV1224B

I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN65LV1023ADB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV1023A

SN65LV1023ADBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV1023A

SN65LV1023ARHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SN65LV

1023A

SN65LV1023ARHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SN65LV

1023A

SN65LV1224BDB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV1224B

SN65LV1224BDBG4 ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV1224B

SN65LV1224BDBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV1224B

SN65LV1224BDBRG4 ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LV1224B

SN65LV1224BRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SN65LV

1224B

SN65LV1224BRHBRG4 ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SN65LV

1224B

SN65LV1224BRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 SN65LV

1224B

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65LV1023A, SN65LV1224B :

•Enhanced Product: SN65LV1023A-EP, SN65LV1224B-EP

NOTE: Qualified Version Definitions:

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pi» Reel Diame|er AD Dimension designed to accommodate the componeni width ED Dimension deSigned to eccemmodaie me componeni iengm KO Dlmenslun designed to accommodate the eomponeni thickness 7 w Overeii Widlh loe earner cape i p1 Piich between successive cawiy ceniers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprockeiHules ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN65LV1023ARHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

SN65LV1224BDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1

SN65LV1224BRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN65LV1023ARHBR VQFN RHB 32 3000 350.0 350.0 43.0

SN65LV1224BDBR SSOP DB 28 2000 350.0 350.0 43.0

SN65LV1224BRHBR VQFN RHB 32 3000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

SN65LV1023ADB DB SSOP 28 50 530 10.5 4000 4.1

SN65LV1224BDB DB SSOP 28 50 530 10.5 4000 4.1

SN65LV1224BDBG4 DB SSOP 28 50 530 10.5 4000 4.1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

i , s % E2333: I-III EEEEEEE

www.ti.com

PACKAGE OUTLINE

26X 0.65

8.45

28X 0.38

0.22

8.2

7.4 TYP

SEATING

PLANE

0.05 MIN

0.25

GAGE PLANE

0 -8

2 MAX

B5.6

5.0

NOTE 4

10.5

9.9

NOTE 3

0.95

0.55

(0.15) TYP

SSOP - 2 mm max heightDB0028A

SMALL OUTLINE PACKAGE

4214853/B 03/2018

14 15

0.15 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-150.

A 15

DETAIL A

TYPICAL

SCALE 1.500

gag—Eggi 1?:

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

28X (1.85)

28X (0.45)

26X (0.65)

(7)

(R0.05) TYP

SSOP - 2 mm max heightDB0028A

SMALL OUTLINE PACKAGE

4214853/B 03/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

14 15

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

@5ng wﬁwmﬁﬁmgi Lit

www.ti.com

EXAMPLE STENCIL DESIGN

28X (1.85)

28X (0.45)

26X (0.65)

(7)

(R0.05) TYP

SSOP - 2 mm max heightDB0028A

SMALL OUTLINE PACKAGE

4214853/B 03/2018

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

14 15

www.ti.com

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

VQFN - 1 mm max heightRHB 32

PLASTIC QUAD FLATPACK - NO LEAD

5 x 5, 0.5 mm pitch

4224745/A

uUUUlUUUJU C C C ,,,,,,,,, g C C C ‘C \ Qﬂﬂﬂiﬂﬂﬂﬂ I:

www.ti.com

PACKAGE OUTLINE

32X 0.3

0.2

3.45 0.1

32X 0.5

0.3

1 MAX

(0.2) TYP

0.05

0.00

28X 0.5

3.5

2X 3.5

A5.1

4.9 B

5.1

4.9 (0.1)

VQFN - 1 mm max heightRHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

817

916

32 25

(OPTIONAL)

PIN 1 ID

0.1 C A B

0.05 C

EXPOSED

THERMAL PAD

33 SYMM

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

SEE SIDE WALL

DETAIL

20.000

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS

www.ti.com

EXAMPLE BOARD LAYOUT

(1.475)

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

32X (0.25)

32X (0.6)

( 0.2) TYP

VIA

28X (0.5)

(4.8)

(1.475)

( 3.45)

(R0.05)

TYP

VQFN - 1 mm max heightRHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

SYMM

916

SYMM

LAND PATTERN EXAMPLE

SCALE:18X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

F L_J CD :11 \ i 1 1

www.ti.com

EXAMPLE STENCIL DESIGN

32X (0.6)

32X (0.25)

28X (0.5)

(4.8)

4X ( 1.49)

(0.845)

(R0.05) TYP

VQFN - 1 mm max heightRHB0032E

PLASTIC QUAD FLATPACK - NO LEAD

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

916

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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