Texas Instruments 的 UCC53x0 规格书

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text

VCC2

UVLO,

Level

Shift

and

Ctrl

Logic

VCC2

VOUT

IN±

IN+

CLAMP

VCC1

VEE2

GND1

ISOLATION BARRIER

text

VCC2

UVLO,

Level

Shift

and

Ctrl

Logic

VCC2

IN±

IN+

VCC1

VEE2

GND1

ISOLATION BARRIER

GND2

UVLO2

text

VCC2

UVLO,

Level

Shift

and

Ctrl

Logic

VCC2

VOUTH

IN±

IN+

VOUTL

VCC1

VEE2

GND1

ISOLATION BARRIER

VOUT

UVLO

and

Input

Logic

UVLO

and

Input

Logic

UVLO

and

Input

Logic

S Version E Version M Version

Product

Folder

Order

Now

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC5310

UCC5320

UCC5350

UCC5390

SLLSER8F –JUNE 2017–REVISED JANUARY 2019

UCC53x0 Single-Channel Isolated Gate Drivers

1 Features

1• Feature Options

– Split Outputs (UCC53x0S)

– UVLO Referenced to GND2 (UCC53x0E)

– Miller Clamp Option (UCC53x0M)

• 8-pin D (4-mm Creepage) and

DWV (8.5mm Creepage) Package

• 60-ns (Typical) Propagation Delay

• 100-kV/μs Minimum CMTI

• Isolation Barrier Life > 40 Years

• 3-V to 15-V Input Supply Voltage

• Up to 33-V Driver Supply Voltage

– 8-V and 12-V UVLO Options

• Negative 5-V Handling Capability on Input Pins

• Safety-Related Certifications:

– 7000-VPK Isolation DWV (Planned) and 4242-

VPK Isolation D per DIN V VDE V 0884-

11:2017-01 and DIN EN 61010-1

– 5000-VRMS DWV and 3000-VRMS D

Isolation Rating for 1 minute per UL 1577

– CQC Certification per GB4943.1-2011

D and DWV (Planned)

• CMOS Inputs

• Operating Temperature: –40°C to +125°C

2 Applications

• Motor Drives

• High Voltage DC-to-DC Converters

• UPS and PSU

• HEV and EV Power Modules

• Solar Inverters

3 Description

The UCC53x0 is a family of single-channel, isolated

gate drivers designed to drive MOSFETs, IGBTs, SiC

MOSFETs, and GaN FETs (UCC5350SBD). The

UCC53x0S provides a split output that controls the

rise and fall times individually. The UCC53x0M

connects the gate of the transistor to an internal

clamp to prevent false turnon caused by Miller

current. The UCC53x0E has its UVLO2 referenced to

GND2 to get a true UVLO reading.

The UCC53x0 is available in a 4 mm SOIC-8 (D) or

8.5 mm SOIC-8 (DWV) package and can support

isolation voltage up to 3 kVRMS and 5 kVRMS

respectively. With these various options the UCC53x0

family is a good fit for motor drives and industrial

power supplies.

Compared to an optocoupler, the UCC53x0 family

has lower part-to-part skew, lower propagation delay,

higher operating temperature, and higher CMTI.

Device Information(1)

ORDERABLE

PART

NUMBER

MINIMUM

SOURCE AND

SINK CURRENT DESCRIPTION

UCC5310MC 2.4 A and 1.1 A Miller clamp

UCC5320SC 2.4 A and 2.2 A Split output

UCC5320EC 2.4 A and 2.2 A UVLO with respect to IGBT

emitter

UCC5350MC 5 A and 5 A Miller clamp

UCC5350SB 5 A and 5 A Split Output with 8 V UVLO

UCC5390SC 10 A and 10 A Split output

UCC5390EC 10 A and 10 A UVLO with respect to IGBT

emitter

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) For a detailed comparison of devices, see the

Device Comparison Table

4 Functional Block Diagram (S, E, and M Versions)

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Functional Block Diagram (S, E, and M

Versions)................................................................. 1

5 Revision History..................................................... 3

6 Device Comparison Table..................................... 4

7 Pin Configuration and Function........................... 5

8 Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Power Ratings........................................................... 7

8.6 Insulation Specifications for D Package.................... 8

8.7 Insulation Specifications for DWV Package.............. 9

8.8 Safety-Related Certifications For D Package ......... 10

8.9 Safety-Related Certifications For DWV Package.... 10

8.10 Safety Limiting Values .......................................... 10

8.11 Electrical Characteristics....................................... 11

8.12 Switching Characteristics...................................... 13

8.13 Insulation Characteristics Curves ......................... 14

8.14 Typical Characteristics.......................................... 15

9 Parameter Measurement Information ................ 22

9.1 Propagation Delay, Inverting, and Noninverting

Configuration............................................................ 22

10 Detailed Description ........................................... 25

10.1 Overview ............................................................... 25

10.2 Functional Block Diagram ..................................... 25

10.3 Feature Description............................................... 27

10.4 Device Functional Modes...................................... 31

11 Application and Implementation........................ 33

11.1 Application Information.......................................... 33

11.2 Typical Application ............................................... 33

12 Power Supply Recommendations ..................... 39

13 Layout................................................................... 40

13.1 Layout Guidelines ................................................. 40

13.2 Layout Example .................................................... 41

13.3 PCB Material......................................................... 43

14 Device and Documentation Support ................. 44

14.1 Documentation Support ........................................ 44

14.2 Certifications ......................................................... 44

14.3 Related Links ........................................................ 44

14.4 Receiving Notification of Documentation Updates 44

14.5 Community Resources.......................................... 44

14.6 Trademarks........................................................... 44

14.7 Electrostatic Discharge Caution............................ 44

14.8 Glossary................................................................ 45

15 Mechanical, Packaging, and Orderable

Information ........................................................... 45

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5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (October 2018) to Revision F Page

• Deleted (UCC5390EC) from 2nd bullet. There are now three released wide-body devices.................................................. 1

• Added DIN EN 61010-1 to Safety-Related Certifications....................................................................................................... 1

• Added "(Planned)" throughout Safety-Related Certifications bullets...................................................................................... 1

• Changed "variants for pinout configuration and drive strength" with switch type information in description.......................... 1

• Changed creepage and clearance from 9 mm to 8.5 mm in Insulation Specifications and throughout datasheet................ 9

• Added VDE and CQC certification for D package and UL file number for DWV package .................................................. 10

• Changed test condition for VOH............................................................................................................................................. 11

• Changed a minor detail to the UCC53x0M figures............................................................................................................... 29

• Changed typical application circuit for E Version to include capacitors on negative bias ................................................... 34

Changes from Revision D (May 2018) to Revision E Page

• Changed UCC5310 DWV package from Preview to Final..................................................................................................... 4

• Changed UCC5320 DWV package from Preview to Final..................................................................................................... 4

Changes from Revision C (February 2018) to Revision D Page

• Changed marketing status of the UCC5390EC from Preview to Production. ....................................................................... 1

Changes from Revision B (August 2017) to Revision C Page

• Added UCC5350SBD, UCC5320SCDWV, UCC5310MCDWV, and UCC5390ECDWV devices to the datasheet .............. 1

• Changed Features, Applications, Description, and functional block diagram to include E and M version, and DWV

package information. .............................................................................................................................................................. 1

• Added UCC5350SB to the pin configuration and function .................................................................................................... 5

• Added Minimum Storage Temperature .................................................................................................................................. 6

• Changed from VDE V 0884-10 to VDE V 0884-11 in insulation specification and safety-related certification table ............. 8

• Changed Safety Limiting Values ......................................................................................................................................... 10

• Deleted test conditions for Supply Currents......................................................................................................................... 11

• Added Typical Curves and Test Conditions to include UCC5390 and UCC5350 information............................................. 15

• Deleted Device I/O Figure ................................................................................................................................................... 32

• Changed ESD Figure .......................................................................................................................................................... 32

• Added UL online certification directory to the certification section....................................................................................... 44

Changes from Revision A (June 2017) to Revision B Page

• Changed minimum ambient operating temperature from –55°C to –40°C ........................................................................... 1

Changes from Original (June 2017) to Revision A Page

• Deleted 17 A from title which is available for future 10-A device........................................................................................... 1

l TEXAS INSTRUMENTS

UCC5310

UCC5320

UCC5350

UCC5390

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www.ti.com

Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

(1) The S, E, and M suffixes are part of the orderable part number. See the Mechanical, Packaging, and Orderable Information section for

the full orderable part number.

6 Device Comparison Table

DEVICE

OPTION(1) PACKAGE MINIMUM

SOURCE

CURRENT

MINIMUM

SINK

CURRENT

CONFIGURATION UVLO ISOLATION RATING

UCC5310MC D2.4 A 1.1 A Miller clamp 12 V 3-kVRMS

DWV 5-kVRMS

UCC5320EC D 2.4 A 2.2 A UVLO with reference

to GND2 12 V 3-kVRMS

UCC5320SC D2.4 A 2.2 A Split output 12 V 3-kVRMS

DWV 5-kVRMS

UCC5350MC D 5 A 5 A Miller clamp 12 V 3-kVRMS

UCC5350SB D 5 A 5 A Split Output 8 V 3-kVRMS

UCC5390EC D10 A 10 A UVLO with reference

to GND2 12 V 3-kVRMS

DWV 5-kVRMS

UCC5390SC D 10 A 10 A Split output 12 V 3-kVRMS

*9 TEXAS INSTRUMENTS

1VCC1

8 VEE2

2IN+ 7 GND2

3IN±6 OUT

4GND1 5 VCC2

Not to scale

1VCC1

8 VEE2

2IN+ 7 CLAMP

3IN±6 OUT

4GND1 5 VCC2

Not to scale

1VCC1 8 V EE2

2IN+ 7 OUTL

3IN±6 OUTH

4GND1 5 VCC2

Not to scale

UCC5310

UCC5320

UCC5350

UCC5390

www.ti.com

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7 Pin Configuration and Function

UCC5320S, UCC5350SB, and UCC5390S

8-Pin SOIC

Top View

UCC5310M and UCC5350M

8-Pin SOIC

Top View

UCC5320E and UCC5390E

8-Pin SOIC

Top View

Pin Functions

TYPE DESCRIPTION

NAME NO.

UCC53x0S UCC53x0M UCC53x0E

CLAMP — 7 — I Active Miller-clamp input found on the UCC53x0M used to prevent false

turnon of the power switches.

GND1 4 4 4 G Input ground. All signals on the input side are referenced to this ground.

GND2 — — 7 G Gate-drive common pin. Connect this pin to the IGBT emitter. UVLO

referenced to GND2 in the UCC53x0E.

IN+ 2 2 2 I Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS

input threshold. This pin is pulled low internally if left open. Use Table 4 to

understand the input and output logic of these devices.

IN– 3 3 3 I Inverting gate-drive voltage control input. The IN– pin has a CMOS input

threshold. This pin is pulled high internally if left open. Use Table 4 to

understand the input and output logic of these devices.

OUT — 6 6 O Gate-drive output for UCC53x0E and UCC53x0M versions.

OUTH 6 — — O Gate-drive pullup output found on the UCC53x0S.

OUTL 7 — — O Gate-drive pulldown output found on the UCC53x0S.

VCC1 1 1 1 P Input supply voltage. Connect a locally decoupled capacitor to GND. Use a

low-ESR or ESL capacitor located as close to the device as possible.

VCC2 5 5 5 P Positive output supply rail. Connect a locally decoupled capacitor to VEE2.

Use a low-ESR or ESL capacitor located as close to the device as possible.

VEE2 8 8 8 P Negative output supply rail for E version, and GND for S and M versions.

Connect a locally decoupled capacitor to GND2 for E version. Use a low-

ESR or ESL capacitor located as close to the device as possible.

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UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) To maintain the recommended operating conditions for TJ, see the Thermal Information.

8 Specifications

8.1 Absolute Maximum Ratings

Over operating free air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Input bias pin supply voltage VCC1 – GND1 GND1 – 0.3 18 V

Driver bias supply VCC2 – VEE2 –0.3 35 V

VEE2 bipolar supply voltage for

E version VEE2 – GND2 –17.5 0.3 V

Output signal voltage VOUTH – VEE2, VOUTL – VEE2, VOUT – VEE2, VCLAMP – VEE2 VEE2 – 0.3 VCC2 + 0.3 V

Input signal voltage VIN+ – GND1, VIN– – GND1 GND1 – 5 VCC1 + 0.3 V

Junction temperature, TJ(2) –40 150 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic

discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS–001(1) ±4000

Charged device model (CDM), per JEDEC specification JESD22-

C101(2) ±1500

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCC1 Supply voltage, input side 3 15 V

VCC2 Positive supply voltage output side (VCC2 – VEE2), UCC53x0 13.2 33 V

VCC2 Positive supply voltage output side (VCC2 – VEE2), UCC5350SBD 9.5 33 V

VEE2 Bipolar supply voltage for E version (VEE2 – GND2), UCC53x0 –16 0 V

VSUP2 Total supply voltage output side (VCC2 – VEE2), UCC53x0 13.2 33 V

TAAmbient temperature –40 125 °C

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.4 Thermal Information

THERMAL METRIC(1)

UCC53x0

UNITD (SOIC) DWV (SOIC)

8 PINS 8 PINS

RθJA Junction–to-ambient thermal resistance 109.5 119.8 °C/W

RθJC(top) Junction–to-case (top) thermal resistance 43.1 64.1 °C/W

RθJB Junction–to-board thermal resistance 51.2 65.4 °C/W

ΨJT Junction–to-top characterization parameter 18.3 37.6 °C/W

ΨJB Junction–to-board characterization parameter 50.7 63.7 °C/W

8.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

D Package

PDMaximum power dissipation on input and

output VCC1 = 15 V, VCC2 = 15 V, f = 2.1-MHz,

50% duty cycle, square wave, 2.2-nF

load

1.14 W

PD1 Maximum input power dissipation 0.05 W

PD2 Maximum output power dissipation 1.09 W

DWV Package

PDMaximum power dissipation on input and

output VCC1 = 15 V, VCC2 = 15 V, f = 1.9-MHz,

50% duty cycle, square wave, 2.2-nF

load

1.04 W

PD1 Maximum input power dissipation 0.05 W

PD2 Maximum output power dissipation 0.99 W

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SLLSER8F –JUNE 2017–REVISED JANUARY 2019

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall

be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

8.6 Insulation Specifications for D Package

PARAMETER TEST CONDITIONS VALUE UNIT

CLR External Clearance(1) Shortest pin–to-pin distance through air ≥4 mm

CPG External Creepage(1) Shortest pin–to-pin distance across the package

surface ≥4 mm

DTI Distance through the insulation Minimum internal gap (internal clearance) > 21 µm

CTI Comparative tracking index DIN EN 60112 (VDE 0303–11); IEC 60112 > 600 V

Material Group According to IEC 60664–1 I

Overvoltage category per IEC 60664-1 Rated mains voltage ≤150 VRMS I-IV

Rated mains voltage ≤300 VRMS I-III

DIN V VDE 0884–11: 2017–01(2)

VIORM Maximum repetitive peak

isolation voltage AC voltage (bipolar) 990 VPK

VIOWM Maximum isolation working

voltage AC voltage (sine wave); time dependent dielectric

breakdown (TDDB) test; 700 VRMS

VIOTM Maximum transient isolation

voltage VTEST = VIOTM, t = 60 s (qualification) ;

VTEST = 1.2 × VIOTM, t = 1 s (100% production) 4242 VPK

VIOSM Maximum surge isolation

voltage(3) Test method per IEC 62368-1, 1.2/50-µs waveform,

VTEST = 1.3 × VIOSM (qualification) 4242 VPK

qpd Apparent charge(4)

Method a: After I/O safety test subgroup 2/3,

Vini = VIOTM, tini = 60 s

Vpd(m) = 1.2 × VIORM, tm= 10 s

≤5

Method a: After environmental tests subgroup 1,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.2 × VIORM, tm= 10 s

≤5

Method b1: At routine test (100% production) and

preconditioning (type test),

Vini = 1.2 x VIOTM, tini = 1 s;

Vpd(m) = 1.5 × VIORM, tm= 1 s

≤5

CIO Barrier capacitance, input to

output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 1.2 pF

RIO Isolation resistance, input to

output(5)

VIO = 500 V, TA= 25°C > 1012

ΩVIO = 500 V, 100°C ≤TA≤125°C > 1011

VIO = 500 V at TS= 150°C > 109

Pollution degree 2

Climatic category 40/125/21

UL 1577

VISO Withstand isolation voltage VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 ×

VISO, t = 1 s (100% production) 3000 VRMS

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(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

8.7 Insulation Specifications for DWV Package

PARAMETER TEST CONDITIONS VALUE UNIT

DWV

CLR External Clearance(1) Shortest pin–to-pin distance through air ≥8.5 mm

CPG External Creepage(1) Shortest pin–to-pin distance across the package

surface ≥8.5 mm

DTI Distance through the insulation Minimum internal gap (internal clearance) > 21 µm

CTI Comparative tracking index DIN EN 60112 (VDE 0303–11); IEC 60112 > 600 V

Material Group According to IEC 60664–1 I

Overvoltage category per IEC 60664-1 Rated mains voltage ≤600 VRMS I-III

Rated mains voltage ≤1000 VRMS I-II

DIN V VDE 0884–11: 2017–01(2)

VIORM Maximum repetitive peak

isolation voltage AC voltage (bipolar) 2121 VPK

VIOWM Maximum isolation working

voltage

AC voltage (sine wave); time dependent dielectric

breakdown (TDDB) test 1500 VRMS

DC Voltage 2121 VDC

VIOTM Maximum transient isolation

voltage VTEST = VIOTM, t = 60 s (qualification) ;

VTEST = 1.2 × VIOTM, t = 1 s (100% production) 7000 VPK

VIOSM Maximum surge isolation

voltage(3) Test method per IEC 62368-1, 1.2/50-µs waveform,

VTEST = 1.6 × VIOSM (qualification) 8000 VPK

qpd Apparent charge (4)

Method a: After I/O safety test subgroup 2/3,

Vini = VIOTM, tini = 60 s

Vpd(m) = 1.2 × VIORM, tm= 10 s

≤5

Method a: After environmental tests subgroup 1,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.6 × VIORM, tm= 10 s

≤5

Method b1: At routine test (100% production) and

preconditioning (type test),

Vini = 1.2 x VIOTM, tini = 1 s;

Vpd(m) = 1.875 × VIORM, tm= 1 s

≤5

CIO Barrier capacitance, input to

output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 1.2 pF

RIO Isolation resistance, input to

output(5)

VIO = 500 V, TA= 25°C > 1012

ΩVIO = 500 V, 100°C ≤TA≤125°C > 1011

VIO = 500 V at TS= 150°C > 109

Pollution degree 2

Climatic category 40/125/21

UL 1577

VISO Withstand isolation voltage VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 ×

VISO, t = 1 s (100% production) 5000 VRMS

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

8.8 Safety-Related Certifications For D Package

VDE UL CQC

Certified according to DIN V VDE V 0884–11:2017–01

and DIN EN 61010-1 (VDE 0411-1):2011-07 Recognized under UL 1577

Component Recognition Program Certified according to GB 4943.1–2011

Basic Insulation

Maximum Transient Isolation Overvoltage, 4242 VPK;

Maximum Repetitive Peak Voltage, 990 VPK;

Maximum Surge Isolation Voltage, 4242 VPK

Single protection, 3000 VRMS

Basic Insulation,

Altitude ≤5000m,

Tropical Climate,

700 VRMS Maximum Working Voltage

Certificate Number: 40047657 File Number: E181974 Certification number: CQC18001199354

8.9 Safety-Related Certifications For DWV Package

VDE UL CQC

Plan to certify according to DIN V VDE V

0884–11:2017–01 and DIN EN 61010-1 Recognized under UL 1577

Component Recognition Program Plan to certify according to GB

4943.1–2011

Reinforced Insulation

Maximum Transient isolation Overvoltage, 7000 VPK;

Maximum Repetitive Peak Isolation Voltage, 2121 VPK;

Maximum Surge Isolation Voltage, 8000 VPK

Single protection, 5000 VRMS

Reinforced Insulation,

Altitude ≤5000 m,

Tropical Climate

Certification planned File Number: E181974 Certification planned

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS

and PSparameters represent the safety current and safety power respectively. The maximum limits of ISand PSshould not be

exceeded. These limits vary with the ambient temperature, TA.

The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

TJ= TA+ RθJA × P, where P is the power dissipated in the device.

TJ(max) = TS= TA+ RθJA × PS, where TJ(max) is the maximum allowed junction temperature.

PS= IS× VI, where VIis the maximum input voltage.

8.10 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

D PACKAGE

ISSafety output supply

current

RθJA = 109.5°C/W, VCC2 = 15 V, TJ= 150°C, TA= 25°C,

see Figure 1 Output side 73

RθJA = 109.5°C/W, VCC2 = 30 V, TJ= 150°C, TA= 25°C,

see Figure 1 Output side 36

PSSafety output supply

power RθJA = 109.5°C/W, TJ= 150°C, TA= 25°C, see Figure 3

Input side 0.05

WOutput side 1.09

Total 1.14

TSMaximum safety

temperature(1) 150 °C

DWV PACKAGE

ISSafety input, output,

or supply current

RθJA = 119.8°C/W, VI= 15 V, TJ= 150°C, TA= 25°C, see

Figure 2 Output side 66

RθJA = 119.8°C/W, VI= 30 V, TJ= 150°C, TA= 25°C, see

Figure 2 Output side 33

PSSafety input, output,

or total power RθJA = 119.8°C/W, TJ= 150°C, TA= 25°C, see Figure 4

Input side 0.05

WOutput side 0.99

Total 1.04

TSMaximum safety

temperature(1) 150 °C

l TEXAS INSTRUMENTS

UCC5310

UCC5320

UCC5350

UCC5390

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SLLSER8F –JUNE 2017–REVISED JANUARY 2019

Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

8.11 Electrical Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL= 100-pF, TA=

–40°C to +125°C, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENTS

IVCC1 Input supply quiescent current 1.67 2.4 mA

IVCC2 Output supply quiescent

current 1.1 1.8 mA

SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS

VIT+(UVLO1) VCC1 Positive-going UVLO

threshold voltage 2.6 2.8 V

VIT– (UVLO1) VCC1 Negative-going UVLO

threshold voltage 2.4 2.5 V

Vhys(UVLO1) VCC1 UVLO threshold

hysteresis 0.1 V

UCC5310MC, UCC5320SC,UCC5320EC,UCC5390SC,UCC5390EC, and UCC5350MC UVLO THRESHOLDS (12-V UVLO Version)

VIT+(UVLO2) VCC2 Positive-going UVLO

threshold voltage 12 13 V

VIT–(UVLO2) VCC2 Negative-going UVLO

threshold voltage 10.3 11 V

Vhys(UVLO2) VCC2 UVLO threshold voltage

hysteresis 1 V

UCC5350SB UVLO THRESHOLD (8-V UVLO Version)

VIT+(UVLO2) VCC2 Positive-going UVLO

threshold voltage 8.7 9.4 V

VIT–(UVLO2) VCC2 Negative-going UVLO

threshold voltage 7.3 8.0 V

Vhys(UVLO2) VCC2 UVLO threshold voltage

hysteresis 0.7 V

LOGIC I/O

VIT+(IN) Positive-going input threshold

voltage (IN+, IN–) 0.55 × VCC1 0.7 × VCC1 V

VIT–(IN) Negative-going input threshold

voltage (IN+, IN–) 0.3 × VCC1 0.45 × VCC1 V

Vhys(IN) Input hysteresis voltage (IN+,

IN–) 0.1 × VCC1 V

IIH High-level input leakage at IN+ IN+ = VCC1 40 240 µA

IIL Low-level input leakage at IN– IN– = GND1 –240 –40 µA

IN– = GND1 – 5 V –310 –80

GATE DRIVER STAGE

VOH

High-level output voltage

(VCC2 - OUT) and

(VCC2 - OUTH) IOUT = –20 mA 100 240 mV

VOL Low level output voltage (OUT

and OUTL)

UCC5320SC and UCC5320EC,

IN+ = low, IN– = high; IO= 20 mA 9.4 13

UCC5310MC,

IN+ = low, IN– = high; IO= 20 mA 17 26

UCC5390SC and UCC5390EC,

IN+ = low, IN– = high; IO= 20 mA 2 3

UCC5350MC and UCC5350SB,

IN+ = low, IN– = high; IO= 20 mA 5 7

l TEXAS INSTRUMENTS

UCC5310

UCC5320

UCC5350

UCC5390

SLLSER8F –JUNE 2017–REVISED JANUARY 2019

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Electrical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL= 100-pF, TA=

–40°C to +125°C, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOH Peak source current

UCC5320SC and UCC5320EC,

IN+ = high, IN– = low 2.4 4.3

UCC5310MC, IN+ = high, IN– = low 2.4 4.3

UCC5390SC and UCC5390EC,

IN+ = high, IN– = low 10 17

UCC5350MC,

IN+ = high, IN– = low 5 10

UCC5350SB

IN+ = high, IN– = low 5 8.5

IOL Peak sink current

UCC5320SC and UCC5320EC,

IN+ = low, IN– = high 2.2 4.4

UCC5310MC, IN+ = low, IN– = high 1.1 2.2

UCC5390SC and UCC5390EC,

IN+ = low, IN– = high 10 17

UCC5350MC,

IN+ = low, IN– = high 5 10

UCC5350SB

IN+ = low, IN– = high 5 10

ACTIVE MILLER CLAMP (UCC53xxM only)

VCLAMP Low-level clamp voltage UCC5310MC, ICLAMP = 20 mA 26 50 mV

UCC5350MC, ICLAMP = 20 mA 7 10

ICLAMP Clamp low-level current UCC5310MC, VCLAMP = VEE2 + 15 V 1.1 2.2 A

UCC5350MC, VCLAMP = VEE2 + 15 V 5 10

ICLAMP(L) Clamp low-level current for

low output voltage

UCC5310MC, VCLAMP = VEE2 + 2 V 0.7 1.5 A

UCC5350MC, VCLAMP = VEE2 + 2 V 5 10

VCLAMP-TH Clamp threshold voltage UCC5310MC and UCC5350MC 2.1 2.3 V

SHORT CIRCUIT CLAMPING

VCLP-OUT Clamping voltage

(VOUTH – VCC2 or VOUT –VCC2)IN+ = high, IN– = low, tCLAMP = 10 µs,

IOUTH or IOUT= 500 mA 1 1.3 V

VCLP-OUT

Clamping voltage

(VEE2 – VOUTL or VEE2 –

VCLAMP or VEE2 – VOUT)

IN+ = low, IN– = high, tCLAMP = 10 µs,

ICLAMP or IOUTL = –500 mA 1.5

IN+ = low, IN– = high,

ICLAMP or IOUTL = –20 mA 0.9 1

ACTIVE PULLDOWN

VOUTSD Active pulldown voltage on

OUTL, CLAMP, OUT IOUTL or IOUT = 0.1 × IOUTL(typ), VCC2 =

open 1.8 2.5 V

l TEXAS INSTRUMENTS

UCC5310

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UCC5350

UCC5390

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(1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.

8.12 Switching Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TA= –40°C to

+125°C, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

trOutput-signal rise time

UCC5320SC, UCC5320EC, and UCC5310MC,

CLOAD = 1 nF 12 28 ns

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, CLOAD = 1 nF 10 26 ns

tfOutput-signal fall time

UCC5320SC and UCC5320EC, CLOAD = 1 nF 10 25 ns

UCC5310MC, CLOAD = 1 nF 10 26 ns

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, CLOAD = 1 nF 10 22 ns

tPLH Propagation delay

(default versions), high

UCC5320SC and UCC5320EC, CLOAD = 100

pF 60 72 ns

UCC5310MC, CLOAD = 100 pF 60 75 ns

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, CLOAD = 100 pF 65 100 ns

tPHL Propagation delay

(default versions), low

UCC5320CS and UCC5320EC, CLOAD = 100

pF 60 75 ns

UCC5310MC, CLOAD = 100 pF 60 75 ns

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, CLOAD = 100 pF 65 100 ns

tUVLO1_rec UVLO recovery delay of VCC1 See Figure 55 30 µs

tUVLO2_rec UVLO recovery delay of VCC2 See Figure 55 50 µs

tPWD Pulse width distortion

|tPHL – tPLH|

UCC5320SC and UCC5320EC, CLOAD = 100

pF 1 20 ns

UCC5310MC, CLOAD = 100 pF 1 20 ns

UCC5390SC, UCC5350SB, and UCC5390EC,

CLOAD = 100 pF 1 20 ns

UCC5350MC, CLOAD = 100 pF 1 20 ns

tsk(pp) Part-to-part skew(1)

UCC5320SC and UCC5320EC, CLOAD = 100

pF 1 25 ns

UCC5310MC, CLOAD = 100 pF 1 25 ns

UCC5390SC, UCC5350SB, and UCC5390EC,

CLOAD = 100 pF 1 25 ns

UCC5350MC, CLOAD = 100 pF 1 25 ns

CMTI Common-mode transient

immunity PWM is tied to GND or VCC1, VCM = 1200 V 100 120 kV/µs

l TEXAS INSTRUMENTS an an 1 500 ‘ 500

Ambient Temperature (qC)

Safety Limiting Power (mW)

0 50 100 150 200

300

600

900

1200

1500

D001TherTherTherTher

Ambient Temperature (qC)

Safety Limiting Power (mW)

0 50 100 150 200

300

600

900

1200

1500

D001Ther

Ambient Temperature (qC)

Safety Limiting Current (mA)

0 50 100 150 200

D001Ther

VCC2=15V

VCC2=30V

Ambient Temperature (qC)

Safety Limiting Current (mA)

0 50 100 150 200

D001Ther

VCC2=15V

VCC2=30V

UCC5310

UCC5320

UCC5350

UCC5390

SLLSER8F –JUNE 2017–REVISED JANUARY 2019

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

8.13 Insulation Characteristics Curves

Figure 1. Thermal Derating Curve for Limiting Current per

VDE for D Package Figure 2. Thermal Derating Curve for Limiting Current per

VDE for DWV Package

Figure 3. Thermal Derating Curve for Limiting Power per

VDE for D Package Figure 4. Thermal Derating Curve for Limiting Power per

VDE for DWV Package

l TEXAS INSTRUMENTS ‘24

VCC2 (V)

Peak Output Current Low IOL (A)

14 16 18 20 22 24 26 28 30 32 34

D020

UCC5390SC

UCC5350MC

UCC5390EC

Temperature (qC)

ICC1 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

1.08

1.1

1.12

1.14

1.16

1.18

1.2

1.22

1.24

D004

UCC5320SC

UCC5320EC

UCC5310MC

VCC2 (V)

Peak Output Current (A)

10 12 14 16 18 20 22 24 26 28 30

D010

IOH

IOL

VCC2 (V)

Peak Output Current Low IOL (A)

14 16 18 20 22 24 26 28 30 32 34

3.5

4.5

5.5

6.5

7.5

8.5

D011

UCC5320SC

UCC5310MC

UCC5320EC

VCC2 (V)

Peak Output Current High IOH (A)

14 16 18 20 22 24 26 28 30 32 34

4.4

4.8

5.2

5.6

6.4

6.8

7.2

7.6

D010

UCC5320SC

UCC5310MC

UCC5320EC

VCC2 (V)

Peak Output Current High IOH (A)

14 16 18 20 22 24 26 28 30 32 34

D019

UCC5390SC

UCC5350MC

UCC5390EC

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

8.14 Typical Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

CLOAD = 150 nF

Figure 5. Output-High Drive Current vs Output Voltage

CLOAD = 150 nF

Figure 6. Output-High Drive Current vs Output Voltage

CLOAD = 150 nF

Figure 7. UCC5350SBD Output-High Drive Current vs Output

Voltage

CLOAD = 150 nF

Figure 8. Output-Low Drive Current vs Output Voltage

CLOAD = 150 nF

Figure 9. Output-Low Drive Current vs Output Voltage

IN+ = L IN– = H

Figure 10. ICC1 Supply Current vs Temperature

l TEXAS INSTRUMENTS ‘25 2 34 1 685 u 168 125

Frequency (MHz)

ICC1 Supply Current (mA)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

1.61

1.615

1.62

1.625

1.63

1.635

1.64

1.645

1.65

1.655

1.66

1.665

1.67

1.675

1.68

D048

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

Temperature (qC)

ICC2 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

0.85

0.9

0.95

1.05

1.1

1.15

1.2

1.25

D007

UCC5320SC

UCC5320EC

UCC5310MC

D006_Icc1_vs_frequency_SLLSER8.grf

Frequency (MHz)

ICC1 Supply Current (mA)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

1.63

1.635

1.64

1.645

1.65

1.655

1.66

1.665

1.67

1.675

1.68

1.685

D006

UCC5320SC

UCC5320EC

UCC5310MC

Temperature (qC)

ICC1 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

1.98

2.01

2.04

2.07

2.1

2.13

2.16

2.19

2.22

2.25

2.28

2.31

2.34

D047

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

D005_Icc1_vs_temperature_SLLSER8.grf

Temperature (qC)

ICC1 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

2.05

2.075

2.1

2.125

2.15

2.175

2.2

2.225

2.25

2.275

2.3

D005

UCC5320SC

UCC5320EC

UCC5310MC

Temperature (qC)

ICC1 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

1.06

1.08

1.1

1.12

1.14

1.16

1.18

1.2

1.22

1.24

1.26

D046

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

UCC5310

UCC5320

UCC5350

UCC5390

SLLSER8F –JUNE 2017–REVISED JANUARY 2019

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Typical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

IN+ = L IN– = H

Figure 11. ICC1 Supply Current vs Temperature IN+ = H IN– = L

Figure 12. ICC1 Supply Current vs Temperature

IN+ = H IN– = L

Figure 13. ICC1 Supply Current vs Temperature Duty Cycle = 50% T = 25°C

Figure 14. ICC1 Supply Current vs Input Frequency

Duty Cycle = 50% T = 25°C

Figure 15. ICC1 Supply Current vs Input Frequency

IN+ = L IN– = H

Figure 16. ICC2 Supply Current vs Temperature

l TEXAS INSTRUMENTS m: was 13/:

Frequncy (MHz)

ICC2 Supply Current (mA)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

1.61

1.615

1.62

1.625

1.63

1.635

1.64

1.645

1.65

1.655

1.66

1.665

1.67

1.675

1.68

D051

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

LOAD (nF)

Output Supply Current ICC2 (mA)

0 1 2 3 4 5 6 7 8 9 10

1.075

1.1

1.125

1.15

1.175

1.2

1.225

1.25

1.275

1.3

1.325

1.35

1.375

D014

UCC5320SC

UCC5310MC

UCC5320EC

Temperature (qC)

ICC2 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

1.45

1.5

1.55

1.6

1.65

1.7

D050

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

Frequency (MHz)

ICC2 Supply Current (mA)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

1.04

1.06

1.08

1.1

1.12

1.14

D009

UCC5320SC

UCC5320EC

UCC5310MC

Temperature (qC)

ICC2 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

0.9

0.95

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

D049

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

Temperature (qC)

ICC2 Supply Current (mA)

-60 -40 -20 0 20 40 60 80 100 120 140

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

1.45

D008

UCC5320SC

UCC5320EC

UCC5310MC

UCC5310

UCC5320

UCC5350

UCC5390

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Typical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

IN+ = L IN– = H

Figure 17. ICC2 Supply Current vs Temperature

IN+ = H IN– = L

Figure 18. ICC2 Supply Current vs Temperature

IN+ = H IN– = L

Figure 19. ICC2 Supply Current vs Temperature

Duty Cycle = 50% T = 25°C

Figure 20. ICC2 Supply Current vs Input Frequency

Duty Cycle = 50% T = 25°C

Figure 21. ICC2 Supply Current vs Input Frequency

fSW = 1 kHz

Figure 22. ICC2 Supply Current vs Load Capacitance

l TEXAS INSTRUMENTS 1 42:

Temperature (qC)

Rise Time tr (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

7.25

7.5

7.75

8.25

8.5

8.75

9.25

9.5

9.75

D027

UCC5310MC

UCC5320EC

UCC5320SC

Temperature (qC)

Rise Time tr (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

6.5

7.5

8.5

9.5

10.5

D028

UCC5350MC

UCC5390EC

UCC5390SC

Temperature (qC)

VCLAMP (mV)

-75 -45 -15 15 45 75 105 135 165

-10

-7.5

-5

-2.5

2.5

7.5

12.5

17.5

22.5

D022

0mA

5mA

10mA

15mA

20mA

Temperature (qC)

VCLAMP-TH (V)

-60 -40 -20 0 20 40 60 80 100 120 140

0.5

1.5

2.5

3.5

4.5

D040

UCC5350MC

UCC5310MC

LOAD (nF)

Output-side Supply Current (mA)

0 1 2 3 4 5 6 7 8 9 10

1.15

1.175

1.2

1.225

1.25

1.275

1.3

1.325

1.35

1.375

1.4

1.425

D045

UCC5390SC

UCC5390EC

UCC5350MC

Temperature (qC)

VCLAMP (mV)

-60 -30 0 30 60 90 120 150 180

-10

-5

D025

0mA

5mA

10mA

15mA

20mA

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Typical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

fSW = 1 kHz

Figure 23. ICC2 Supply Current vs Load Capacitance

IClamp = 0mA~20mA

Figure 24. UCC5310M VClamp vs Temperature

IClamp = 0mA~20mA

Figure 25. UCC5350M VClamp vs Temperature Figure 26. VClamp-TH vs Temperature

Figure 27. Rise Time vs Temperature Figure 28. Rise Time vs Temperature

l TEXAS INSTRUMENTS m f} \\ 53 2: :3:

Temperature (qC)

Propagation Delay (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

D016

TPLH INP

TPHL INP

TPLH INN

TPHL INN

Temperature (qC)

Propagation Delay tPHL (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

49.5

50.5

51.5

52.5

53.5

D033

UCC5310MC

UCC5320EC

UCC5320SC

Temperature (qC)

Propagation Delay tPLH (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

48.5

49.5

50.5

51.5

52.5

53.5

D031

UCC5310MC

UCC5320EC

UCC5320SC

Temperature (qC)

Propagation Delay tPLH (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

50.5

50.75

51.25

51.5

51.75

52.25

52.5

52.75

53.25

D032

UCC5350MC

UCC5390EC

UCC5390SC

Temperature (qC)

Fall Time tf (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

7.5

8.5

9.5

10.5

11.5

D029

UCC5310MC

UCC5320EC

UCC5320SC

Temperature (qC)

Fall Time tf (ns)

-60 -30 0 30 60 90 120 150

7.5

8.5

9.5

D030

UCC5350MC

UCC5390EC

UCC5390SC

UCC5310

UCC5320

UCC5350

UCC5390

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Typical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

Figure 29. Fall Time Vs Temperature Figure 30. Fall Time vs Temperature

Figure 31. Propagation Delay tPLH vs Temperature Figure 32. Propagation Delay tPLH vs Temperature

Figure 33. UCC5350SBD Propagation Delay vs Temperature Figure 34. Propagation Delay tPHL vs Temperature

l TEXAS INSTRUMENTS

LOAD (nF)

Fall Time tf (ns)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

D013

UCC5320SC

UCC5310MC

UCC5320EC

Load Capacitance (nF)

Fall Time tf (ns)

0 1 2 3 4 5 6 7 8 9 10

D038

UCC5390SC

UCC5390EC

UCC5350MC

Load Capacitance (nF)

Rise Time tr (ns)

0 1 2 3 4 5 6 7 8 9 10

D039

UCC5390SC

UCC5390EC

UCC5350MC

VCC2 (V)

Rise Time (ns)

10 12 14 16 18 20 22 24 26 28 30

D011

1-nF

2.2-nF

5.6-nF

10-nF

Temperature (qC)

Propagation Delay tPHL (ns)

-60 -40 -20 0 20 40 60 80 100 120 140

51.5

52.5

53.5

54.5

55.5

56.5

D034

UCC5350MC

UCC5390EC

UCC5390SC

LOAD (nF)

Rise time tr (ns)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

D012

UCC5320SC

UCC5310MC

UCC5320EC

UCC5310

UCC5320

UCC5350

UCC5390

SLLSER8F –JUNE 2017–REVISED JANUARY 2019

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Typical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

Figure 35. Propagation Delay tPHL vs Temperature

fSW = 1 kHz RGH = 0 ΩRGL = 0 Ω

Figure 36. Rise Time vs Load Capacitance

fSW = 1 kHz RGH = 0 ΩRGL = 0 Ω

Figure 37. Rise Time vs Load Capacitance Figure 38. UCC5350SBD Rise Time vs CLand VCC2

fSW = 1 kHz RGH = 0 ΩRGL = 0 Ω

Figure 39. Fall Time vs Load Capacitance

fSW = 1 kHz RGH = 0 ΩRGL = 0 Ω

Figure 40. Fall Time vs Load Capacitance

l TEXAS INSTRUMENTS

VCC2 (V)

Fall Time (ns)

10 12 14 16 18 20 22 24 26 28 30

D013

1-nF

2.2-nF

5.6-nF

10-nF

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Typical Characteristics (continued)

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TA=

–40°C to +125°C, (unless otherwise noted)

Figure 41. UCC5350SBD Fall Time vs CLand VCC2

‘5‘ TEXAS INSTRUMENTS

tPLH tPHL

trtf

50%

10%

90%

50%

OUTH

OUTL

IN+

IN±

VCC2

tPLH tPHL

50%

10%

90%

50%

OUTH

OUTL

IN+

IN± 0 V

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

9 Parameter Measurement Information

9.1 Propagation Delay, Inverting, and Noninverting Configuration

Figure 42 shows the propagation delay OUTH and OUTL for noninverting configurations. Figure 43 shows the

propagation delay with the inverting configuration. These figures also demonstrate the method used to measure

the rise (tr) and fall (tf) times.

Figure 42. OUTH and OUTL Propagation Delay, Noninverting Configuration

Figure 43. OUTH and OUTL Propagation Delay, Inverting Configuration

{L} TEXAS INSTRUMENTS (9 :::::::::::::::::::::

VCC1

IN+

IN±

GND1

VEE2

OUT

VCC2

C3 C4

15 V

PWM

VCM

± +

CLAMP

5 V

ISOLATION BARRIER

VCC1

IN+

IN±

GND1

VEE2

OUTH

VCC2

C3 C4

15 V

PWM

VCM

± +

OUTL

ISOLATION BARRIER

5 V

UCC5310

UCC5320

UCC5350

UCC5390

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Propagation Delay, Inverting, and Noninverting Configuration (continued)

9.1.1 CMTI Testing

Figure 44,Figure 45, and Figure 46 are simplified diagrams of the CMTI testing configuration used for each

device type.

Figure 44. CMTI Test Circuit for Split Output (UCC53x0S)

Figure 45. CMTI Test Circuit for Miller Clamp (UCC53x0M)

‘5‘ TEXAS INSTRUMENTS /77

VCC1

IN+

IN±

GND1

VEE2

OUT

VCC2

C3 C4

15 V

PWM

VCM

± +

GND2

ISOLATION BARRIER

5 V

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Propagation Delay, Inverting, and Noninverting Configuration (continued)

Figure 46. CMTI Test Circuit for UVLO2 with Respect to GND2 (UCC53x0E)

‘5‘ TEXAS INSTRUMENTS

TX IN

RX OUT

Carrier signal through

isolation barrier

TX IN

Oscillator

OOK

Modulation

Transmitter

Emissions

Reduction

Techniques

TX Signal

Conditioning Envelope

Detection

RX Signal

Conditioning

Receiver

RX OUT

SiO2 based

Capacitive

Isolation

Barrier

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

10 Detailed Description

10.1 Overview

The UCC53x0 family of isolated gate drivers has three variations: split output, Miller clamp, and UVLO2

referenced to GND2 (see Device Comparison Table). The isolation inside the UCC53x0 family of devices is

implemented with high-voltage SiO2-based capacitors. The signal across the isolation has an on-off keying

(OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier (see

Figure 48). The transmitter sends a high-frequency carrier across the barrier to represent one digital state and

sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal

conditioning and produces the output through a buffer stage. The UCC53x0 devices also incorporate advanced

circuit techniques to maximize the CMTI performance and minimize the radiated emissions from the high

frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 47,

shows a functional block diagram of a typical channel. Figure 48 shows a conceptual detail of how the OOK

scheme works.

Figure 47 shows how the input signal passes through the capacitive isolation barrier through modulation (OOK)

and signal conditioning.

10.2 Functional Block Diagram

Figure 47. Conceptual Block Diagram of a Capacitive Data Channel

Figure 48. On-Off Keying (OOK) Based Modulation Scheme

VEE2

VCC2

Level

Shifting

and

Control

Logic

UVLO2

UVLO1

GND1

VCC1

IN±

IN+

OUT

CLAMP

2 V

ISOLATION BARRIER

VCC2

VEE2

VCC2

Level

Shifting

and

Control

Logic

UVLO2

UVLO1

GND1

VCC1

IN±

IN+

VCC2

OUTH

ISOLATION BARRIER

OUTL

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Functional Block Diagram (continued)

Figure 49. Functional Block Diagram — Split Output (UCC53x0S)

Figure 50. Functional Block Diagram — Miller Clamp (UCC53x0M)

VEE2

VCC2

Level

Shifting

and

Control

Logic

UVLO2

UVLO1

GND1

VCC1

IN±

IN+

VCC2

OUT

GND2

ISOLATION BARRIER

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Functional Block Diagram (continued)

Figure 51. Functional Block Diagram — UVLO With Respect to GND2 (UCC53x0E)

10.3 Feature Description

10.3.1 Power Supply

The VCC1 input power supply supports a wide voltage range from 3 V to 15 V and the VCC2 output supply

supports a voltage range from 9.5 V to 33 V. For operation with bipolar supplies, the power device is turned off

with a negative voltage on the gate with respect to the emitter or source. This configuration prevents the power

device from unintentionally turning on because of current induced from the Miller effect. The typical values of the

VCC2 and VEE2 output supplies for bipolar operation are 15 V and –8 V with respect to GND2 for IGBTs and 20 V

and –5 V for SiC MOSFETs.

For operation with unipolar supply, the VCC2 supply is connected to 15 V with respect to VEE2 for IGBTs, and 20

V for SiC MOSFETs. The VEE2 supply is connected to 0 V. In this use case, the UCC53x0 device with Miller

clamping function (UCC53x0M) can be used. The Miller clamping function is implemented by adding a low

impedance path between the gate of the power device and the VEE2 supply. Miller current sinks through the

clamp pin, which clamps the gate voltage to be lower than the turnon threshold value for the gate.

10.3.2 Input Stage

The input pins (IN+ and IN–) of the UCC53x0 family are based on CMOS-compatible input-threshold logic that is

completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals

(such as those from 3.3-V microcontrollers), because the UCC53x0 family has a typical high threshold (VIT+(IN)) of

0.55 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good

noise immunity and stable operation. If any of the inputs are left open, 128 kΩof internal pulldown resistance

forces the IN+ pin low and 128 kΩof internal resistance pulls IN– high. However, TI still recommends grounding

an input or tying to VCC1 if it is not being used for improved noise immunity.

Because the input side of the UCC53x0 family is isolated from the output driver, the input signal amplitude can

be larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows

greater flexibility when integrating the gate-driver with control signal sources and allows the user to choose the

most efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a

voltage higher than VCC1.

l TEXAS INSTRUMENTS

Level

Shifting

and

Control

Logic

ROL

ROH

RNMOS

UVLO2 VCC2

OUTH

VEE2

OUTL

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Feature Description (continued)

10.3.3 Output Stage

The output stages of the UCC53x0 family feature a pullup structure that delivers the highest peak-source current

when it is most needed which is during the Miller plateau region of the power-switch turnon transition (when the

power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a P-

channel MOSFET and an additional pullup N-channel MOSFET in parallel. The function of the N-channel

MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is

accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing

states from low to high. Table 1 lists the typical internal resistance values of the pullup and pulldown structure.

Table 1. UCC53x0 On-Resistance

DEVICE OPTION RNMOS ROH ROL RCLAMP UNIT

UCC5320SC and UCC5320EC 4.5 12 0.65 Not applicable Ω

UCC5310MC 4.5 12 1.3 1.3 Ω

UCC5390SC and UCC5390EC 0.76 12 0.13 Not applicable Ω

UCC5350MC 1.54 12 0.26 0.26 Ω

UCC5350SB 1.54 12 0.26 Not applicable Ω

The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device

only. This parameter is only for the P-channel device, because the pullup N-channel device is held in the OFF

state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.

Therefore, the effective resistance of the UCC53x0 pullup stage during this brief turnon phase is much lower than

what is represented by the ROH parameter, which yields a faster turnon. The turnon-phase output resistance is

the parallel combination ROH || RNMOS.

The pulldown structure in the UCC53x0 S and E versions is simply composed of an N-channel MOSFET. For the

M version, an additional FET is connected in parallel with the pulldown structure when the CLAMP and OUT pins

are connected to the gate of the IGBT or MOSFET. The output voltage swing between VCC2 and VEE2 provides

rail-to-rail operation.

Figure 52. Output Stage—S Version

l TEXAS INSTRUMENTS

Level

Shifting

and

Control

Logic ROL

ROH

RNMOS

UVLO2 VCC2

CLAMP

OUT

VEE2

2 V

Level

Shifting

and

Control

Logic

ROL

ROH

RNMOS

UVLO2 VCC2

GND2

OUT

VEE2

UCC5310

UCC5320

UCC5350

UCC5390

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Figure 53. Output Stage—E Version

Figure 54. Output Stage—M Version

10.3.4 Protection Features

10.3.4.1 Undervoltage Lockout (UVLO)

UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2

and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO)

at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected

output low, regardless of the input pins (IN+ and IN–) as shown in Table 4. The VCC UVLO protection has a

hysteresis feature (Vhys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise;

this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and

operating current consumption increases suddenly. Figure 55 shows the UVLO functions.

Table 2. UCC53x0 VCC1 UVLO Logic

CONDITION INPUTS OUTPUTS

IN+ IN– OUTH OUT, OUTL

VCC1 – GND1 < VIT+(UVLO1) during device start-up

H L Hi-Z L

L H Hi-Z L

H H Hi-Z L

L L Hi-Z L

‘5‘ TEXAS INSTRUMENTS

IN+

VCC1

VCC2

VOUT

VIT+ (UVLO2)

VIT± (UVLO2)

IN+

VCC1

VCC2

VOUT

VIT+ (UVLO1)

VIT±(UVLO1)

tUVLO1_rec

tUVLO2_rec

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Table 2. UCC53x0 VCC1 UVLO Logic (continued)

CONDITION INPUTS OUTPUTS

IN+ IN– OUTH OUT, OUTL

VCC1 – GND1 < VIT–(UVLO1) after device start-up

H L Hi-Z L

L H Hi-Z L

H H Hi-Z L

L L Hi-Z L

Table 3. UCC53x0 VCC2 UVLO Logic

CONDITION INPUTS OUTPUTS

IN+ IN– OUTH OUT, OUTL

VCC2 – VEE2 < VIT+(UVLO2) during device start-up

H L Hi-Z L

L H Hi-Z L

H H Hi-Z L

L L Hi-Z L

VCC2 – VEE2 < VIT–(UVLO2) after device start-up

H L Hi-Z L

L H Hi-Z L

H H Hi-Z L

L L Hi-Z L

When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the

output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. Figure 55 shows this delay.

Figure 55. UVLO Functions

10.3.4.2 Active Pulldown

The active pulldown function is used to pull the IGBT or MOSFET gate to the low state when no power is

connected to the VCC2 supply. This feature prevents false IGBT and MOSFET turnon on the OUT, OUTL, and

CLAMP pins by clamping the output to approximately 2 V.

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an

active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper PMOS is

resistively held off by a pullup resistor while the lower NMOS gate is tied to the driver output through a 500-kΩ

resistor. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS

device, which is approximately 1.5 V when no bias power is available.

l TEXAS INSTRUMENTS

UCC5310

UCC5320

UCC5350

UCC5390

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10.3.4.3 Short-Circuit Clamping

The short-circuit clamping function is used to clamp voltages at the driver output and pull the active Miller clamp

pins slightly higher than the VCC2 voltage during short-circuit conditions. The short-circuit clamping function helps

protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping

function is implemented by adding a diode connection between the dedicated pins and the VCC2 pin inside the

driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of

20 mA. Use external Schottky diodes to improve current conduction capability as needed.

10.3.4.4 Active Miller Clamp (UCC53x0M)

The active Miller-clamp function is used to prevent false turn-on of the power switches caused by Miller current in

applications where a unipolar power supply is used. The active Miller-clamp function is implemented by adding a

low impedance path between the power-switch gate terminal and ground (VEE2) to sink the Miller current. With

the Miller-clamp function, the power-switch gate voltage is clamped to less than 2 V during the off state.

Figure 58 shows a typical application circuit of UCC5310M and UCC5350M.

10.4 Device Functional Modes

Table 4 lists the functional modes for the UCC53x0 devices assuming VCC1 and VCC2 are in the recommended

range.

Table 4. Function Table for UCC53x0S

IN+ IN– OUTH OUTL

Low X Hi-Z Low

X High Hi-Z Low

High Low High High-Z

Table 5. Function Table for UCC53x0M and UCC53x0E

IN+ IN– OUT

Low X Low

X High Low

High Low High

l TEXAS INSTRUMENTS GNDI szg

VCC1

IN+

IN±

GND1 VEE2

OUTL

OUTH

VCC2

18 V

5.5 V

35 V

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

10.4.1 ESD Structure

Figure 56 shows the multiple diodes involved in the ESD protection components of the UCC53x0 devices . This

provides pictorial representation of the absolute maximum rating for the device.

Figure 56. ESD Structure

‘5‘ TEXAS INSTRUMENTS

VCC1

IN+

IN±

GND1

VEE2

VCC2

OUTH

OUTL

5 V

PWM

Signal Emitter

Power Emitter

C3 C4

15 V

RGON

RGOFF

Rin

Cin

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

The UCC53x0 is a family of simple, isolated gate drivers for power semiconductor devices, such as MOSFETs,

IGBTs, or SiC MOSFETs. The family of devices is intended for use in applications such as motor control, solar

inverters, switched-mode power supplies, and industrial inverters.

The UCC53x0 family of devices has three pinout configurations, featuring split outputs, Miller clamp, and UVLO

with reference to GND2. The UCC5320SC, UCC5350SB, and UCC5390SC have a split output, OUTH and

OUTL. The two pins can be used to separately decouple the power transistor turnon and turnoff commutations.

The UCC5310MC and UCC5350MC feature active Miller clamping, which can be used to prevent false turn-on of

the power transistors induced by the Miller current. The UCC5320EC and UCC5390EC offer true UVLO

protection by monitoring the voltage between the VCC2 and GND2 pins to prevent the power transistors from

operating in a saturation region. The UCC53x0 family of devices comes in an 8-pin D and 8-pin DWV package

options and have a creepage, or clearance, of 4 mm and 8.5 mm respectively, which are suitable for applications

where basic or reinforced isolation is required. Different drive strengths enable a simple driver platform to be

used for applications demanding power transistors with different power ratings. Specifically, the UCC5390 device

offers a 10-A minimum drive current which can help remove the external current buffer used to drive high power

transistors.

11.2 Typical Application

The circuits in Figure 57,Figure 58, and Figure 59 show a typical application for driving IGBTs.

Figure 57. Typical Application Circuit for UCC53x0S to Drive IGBT

{L} TEXAS INSTRUMENTS ﬂ 3%: M ﬂ 3%

VCC1

IN+

IN±

GND1

VEE2

OUT

GND2

VCC2

5 V

Signal Emitter

Power Emitter

± 8 V

C3 C4

15 V

PWM Rin

Cin

C5 C3

VCC1

IN+

IN±

GND1

VEE2

VCC2

OUT

CLAMP

C3 C4

15 V

5 V

Signal Emitter

Power Emitter

PWM Rin

Cin

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

Typical Application (continued)

Figure 58. Typical Application Circuit for UCC5310M and UCC5350M to Drive IGBT

Figure 59. Typical Application Circuit for UCC5320E and UCC5390E to Drive IGBT

11.2.1 Design Requirements

Table 6 lists the recommended conditions to observe the input and output of the UCC5320S split-output gate

driver with the IN– pin tied to the GND1 pin.

Table 6. UCC5320S Design Requirements

PARAMETER VALUE UNIT

VCC1 3.3 V

VCC2 15 V

IN+ 3.3 V

IN– GND1 -

Switching frequency 10 kHz

IGBT IKW50N65H5 -

l TEXAS INSTRUMENTS ( lo '0 NMOS OH ON GFETilm 0L OFF GFETilm

CC2

OL OL OFF GFET _Int

V15 V

I 1.4 A

R R R 0.65 10 0

  :  :  :

CC2

OL OL OFF GFET _Int

I min 4.4 A,R R R

§ ·

¨ ¸

 

CC2

OH NMOS OH ON GFET _Int

V15 V

I 1.8 A

R ||R R R 4.5 ||12 5.1 0

  : :  :  :

CC2

OH NMOS OH ON GFET _Int

I min 4.3 A,R || R R R

§ ·

¨ ¸

 

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

11.2.2 Detailed Design Procedure

11.2.2.1 Designing IN+ and IN– Input Filter

TI recommends that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the

signal at the output. However, a small input filter, RIN-CIN, can be used to filter out the ringing introduced by

nonideal layout or long PCB traces.

Such a filter should use an RIN resistor with a value from 0 Ωto 100 Ωand a CIN capacitor with a value from 10

pF to 1000 pF. In the example, the selected value for RIN is 51 Ωand CIN is 33 pF, with a corner frequency of

approximately 100 MHz.

When selecting these components, pay attention to the trade-off between good noise immunity and propagation

delay.

11.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, RG(ON) and RG(OFF) are used to:

1. Limit ringing caused by parasitic inductances and capacitances

2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery

3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss

4. Reduce electromagnetic interference (EMI)

The output stage has a pullup structure consisting of a P-channel MOSFET and an N-channel MOSFET in

parallel. The combined peak source current is 4.3 A for the UCC5320 family and 17 A for the UCC5390 family.

Use Equation 1 to estimate the peak source current using the UCC5320S as an example.

where

• RON is the external turnon resistance.

• RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will

assume 0Ωfor our example

• IOH is the peak source current which is the minimum value between 4.3 A, the gate-driver peak source current,

and the calculated value based on the gate-drive loop resistance. (1)

In this example, the peak source current is approximately 1.8 A as calculated in Equation 2.

(2)

Similarly, use Equation 3 to calculate the peak sink current.

where

• ROFF is the external turnoff resistance.

• IOL is the peak sink current which is the minimum value between 4.4 A, the gate-driver peak sink current, and

the calculated value based on the gate-drive loop resistance. (3)

In this example, the peak sink current is the minimum of Equation 4 and 4.4 A.

(4)

l TEXAS INSTRUMENTS Pane: cmx vccﬂ 002x 0022 W PGSW: 002>< gxsw="" pesw="" :="" x="" x="" :="" w="">

GDO 18 mW 12 || 4.5 0.65

P 4.1mW

2 12 || 4.5 5.1 0 0.65 10 0

§ ·

: : :

 |

¨ ¸

: :  :  : :  :  :

GSW OH NMOS OL

GDO OH NMOS ON GFET _Int OL OFF GFET _Int

P R ||R R

P 2 R || R R R R R R

§ ·



¨ ¸

   

GSW

P 15 V 120 nC 10 kHz 18 mWu u

CC2GSW G SW

P V Q f

u u

GDQ CC1 VCC1 CC2 CC2

P V I V I 22mW u  u |

UCC5310

UCC5320

UCC5350

UCC5390

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Product Folder Links: UCC5310 UCC5320 UCC5350 UCC5390

NOTE

The estimated peak current is also influenced by PCB layout and load capacitance.

Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and

introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-

driver loop should be minimized. Conversely, the peak source and sink current is

dominated by loop parasitics when the load capacitance (CISS) of the power transistor is

very small (typically less than 1 nF) because the rising and falling time is too small and

close to the parasitic ringing period.

11.2.2.3 Estimate Gate-Driver Power Loss

The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC53x0 device and the

power losses in the peripheral circuitry, such as the external gate-drive resistor.

The PGD value is the key power loss which determines the thermal safety-related limits of the UCC53x0 device,

and it can be estimated by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as

driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is

measured on the bench with no load connected to the OUT or OUTH and OUTL pins at a given VCC1, VCC2,

switching frequency, and ambient temperature. In this example, VCC1 is 3.3V and VCC2 is 15 V. The current on

each power supply, with PWM switching from 0 V to 3.3 V at 10 kHz, is measured to be ICC1 = 1.67 mA and ICC2

= 1.11 mA. Therefore, use Equation 5 to calculate PGDQ.

(5)

The second component is the switching operation loss, PGDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Use Equation 6 to calculate the total dynamic loss

from load switching, PGSW.

where

• QGis the gate charge of the power transistor at VCC2. (6)

So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated

in Equation 7.

(7)

QGrepresents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change

with different testing conditions. The UCC5320S gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO

is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the

gate driver-loss will be dissipated inside the UCC5320S. If an external turn-on and turn-off resistance exists, the

total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-

transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the

source/sink current is not saturated to 4.3 A/4.4 A, however, it will be non-linear if the source/sink current is

saturated. Therefore, PGDO is different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

(8)

In this design example, all the predicted source and sink currents are less than 4.3 A and 4.4 A, therefore, use

Equation 9 to estimate the UCC53x0 gate-driver loss.

(9)

Case 2 - Nonlinear Pull-Up/Down Resistor:

l TEXAS INSTRUMENTS PGD : GDQ + GDO : T1: C+WJTX GD mW

J C JT GD

T T P  < u

GD GDQ GDO

P P P 22mW 4.1mW 26.1mW  

 

R _ Sys F _ Sys

T T

GDO SW OUTH OCC2 UTL

0 0

P f 4.3 A V V (t) dt 4.4 A V (t)dt

ª º

« »

u u   u

« »

¬ ¼

³ ³

UCC5310

UCC5320

UCC5350

UCC5390

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SLLSER8F –JUNE 2017–REVISED JANUARY 2019

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where

• VOUTH/L(t) is the gate-driver OUTH and OUTL pin voltage during the turnon and turnoff period. In cases where

the output is saturated for some time, this value can be simplified as a constant-current source (4.3 A at turnon

and 4.4 A at turnoff) charging or discharging a load capacitor. Then, the VOUTH/L(t) waveform will be linear and

the TR_Sys and TF_Sys can be easily predicted. (10)

For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is

a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based

on this discussion.

Use Equation 11 to calculate the total gate-driver loss dissipated in the UCC53x0 gate driver, PGD.

(11)

11.2.2.4 Estimating Junction Temperature

Use Equation 12 to estimate the junction temperature (TJ) of the UCC53x0 family.

where

• TCis the UCC53x0 case-top temperature measured with a thermocouple or some other instrument.

•ΨJT is the junction-to-top characterization parameter from the Thermal Information table. (12)

Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance

(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,

such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will

inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming

that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the

application environment. As long as the recommended layout guidelines are observed, junction temperature

estimations can be made accurately to within a few degrees Celsius.

11.2.3 Selecting VCC1 and VCC2 Capacitors

Bypass capacitors for the VCC1 and VCC2 supplies are essential for achieving reliable performance. TI

recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with

sufficient voltage ratings, temperature coefficients, and capacitance tolerances.

NOTE

DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V,

1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.

11.2.3.1 Selecting a VCC1 Capacitor

A bypass capacitor connected to the VCC1 pin supports the transient current required for the primary logic and the

total current consumption, which is only a few milliamperes. Therefore, a 50-V MLCC with over 100 nF is

recommended for this application. If the bias power-supply output is located a relatively long distance from the

VCC1 pin, a tantalum or electrolytic capacitor with a value greater than 1 μF should be placed in parallel with the

MLCC.

11.2.3.2 Selecting a VCC2 Capacitor

A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the CVCC2 capacitor. If the bias power supply

output is located a relatively long distance from the VCC2 pin, a tantalum or electrolytic capacitor with a value

greater than 10 μF should be used in parallel with CVCC2.

‘5‘ TEXAS INSTRUMENTS

VCC1

IN+

IN±

GND1

VEE2

VCC2

OUT

GND2 Signal Emitter

CA2

CA1

VCC1

IN+

IN±

GND1

VEE2

VCC2

OUTH

OUTL Signal Emitter

20 V

RGON

RGOFF

CA2

CA1

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11.2.3.3 Application Circuits With Output Stage Negative Bias

When parasitic inductances are introduced by nonideal PCB layout and long package leads (such as TO-220

and TO-247 type packages), ringing in the gate-source drive voltage of the power transistor could occur during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, unintended turnon and shoot-through

could occur. Applying a negative bias on the gate drive is a popular way to keep such ringing below the

threshold. A few examples of implementing negative gate-drive bias follow.

Figure 60 shows the first example with negative bias turnoff on the output using a Zener diode on the isolated

power-supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply is

equal to 20 V, the turnoff voltage is –5.1 V and the turnon voltage is 20 V – 5.1 V ≈15 V.

Figure 60. Negative Bias With Zener Diode on Iso-Bias Power-Supply Output

Figure 61 shows another example which uses two supplies (or single-input, double-output power supply). The

power supply across VCC2 and GND2 determines the positive drive output voltage and the power supply across

VEE2 and GND2 determines the negative turnoff voltage. This solution requires more power supplies than the first

example, however, it provides more flexibility when setting the positive and negative rail voltages.

Figure 61. Negative Bias With Two Iso-Bias Power Supplies (UCC5320E and UCC5390E)

l TEXAS INSTRUMENTS Aullenl 7“ Azqumm ‘. \W stnw ‘fW‘——————————D[ mm ‘u mm»: mm 4 w 13w

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11.2.4 Application Curve

VCC2 = 20 V VEE2 = GND fSW = 10 kHz

Figure 62. PWM Input And Gate Voltage Waveform

12 Power Supply Recommendations

The recommended input supply voltage (VCC1) for the UCC53x0 device is from 3 V to 15 V. The lower limit of the

range of output bias-supply voltage (VCC2) is determined by the internal UVLO protection feature of the device.

The VCC1 and VCC2 voltages should not fall below their respective UVLO thresholds for normal operation, or else

the gate-driver outputs can become clamped low for more than 50 μs by the UVLO protection feature. For more

information on UVLO, see the Undervoltage Lockout (UVLO) section. The higher limit of the VCC2 range depends

on the maximum gate voltage of the power device that is driven by the UCC53x0 device, and should not exceed

the recommended maximum VCC2 of 33 V. A local bypass capacitor should be placed between the VCC2 and VEE2

pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an additional 100-nF capacitor in

parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as

close to the device as possible. Low-ESR, ceramic surface-mount capacitors are recommended. Similarly, a

bypass capacitor should also be placed between the VCC1 and GND1 pins. Given the small amount of current

drawn by the logic circuitry within the input side of the UCC53x0 device, this bypass capacitor has a minimum

recommended value of 100 nF.

If only a single, primary-side power supply is available in an application, isolated power can be generated for the

secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such

applications, detailed power supply design and transformer selection recommendations are available in SN6501

Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for

Isolated Power Supplies data sheet.

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13 Layout

13.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the UCC53x0. Some key

guidelines are:

• Component placement:

– Low-ESR and low-ESL capacitors must be connected close to the device between the VCC1 and GND1

pins and between the VCC2 and VEE2 pins to bypass noise and to support high peak currents when turning

on the external power transistor.

– To avoid large negative transients on the VEE2 pins connected to the switch node, the parasitic

inductances between the source of the top transistor and the source of the bottom transistor must be

minimized.

• Grounding considerations:

– Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area

is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of

the transistors. The gate driver must be placed as close as possible to the transistors.

• High-voltage considerations:

– To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces

or copper below the driver device. A PCB cutout or groove is recommended in order to prevent

contamination that may compromise the isolation performance.

• Thermal considerations:

– A large amount of power may be dissipated by the UCC53x0 if the driving voltage is high, the load is

heavy, or the switching frequency is high (for more information, see the Estimate Gate-Driver Power Loss

section). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-

board thermal impedance (θJB).

– Increasing the PCB copper connecting to the VCC2 and VEE2 pins is recommended, with priority on

maximizing the connection to VEE2. However, the previously mentioned high-voltage PCB considerations

must be maintained.

– If the system has multiple layers, TI also recommends connecting the VCC2 and VEE2 pins to internal

ground or power planes through multiple vias of adequate size. These vias should be located close to the

IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different

high voltage planes are overlapping.

TEXAS INSTRUMENTS

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13.2 Layout Example

Figure 63 shows a PCB layout example with the signals and key components labeled.

(1) No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.

Figure 63. Layout Example

‘5‘ TEXAS INSTRUMENTS

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Layout Example (continued)

Figure 64 and Figure 65 show the top and bottom layer traces and copper.

Figure 64. Top-Layer Traces and Copper

Figure 65. Bottom-Layer Traces and Copper (Flipped)

i TEXAS INSTRUMENTS TEXAS 3 ‘NSTRUMENTS O '— C15C14C12 ('0 1:1- ‘._ @& For evaluation onw- no: Fcc approved for vesale. E ('3 n F E| — INTOSSﬂ 2

10 mils

40 mils FR-4

0r ~ 4.5

Keep this space

free from planes,

traces, pads, and

vias

Ground plane

Power plane

Low-speed traces

High-speed traces

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Layout Example (continued)

Figure 66 shows the 3D layout of the top view of the PCB.

(1) The location of the PCB cutout between primary side and secondary sides ensures isolation performance.

Figure 66. 3-D PCB View

13.3 PCB Material

Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of

lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-

extinguishing flammability-characteristics.

Figure 67 shows the recommended layer stack.

Figure 67. Recommended Layer Stack

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14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Digital Isolator Design Guide

• Texas Instruments, Isolation Glossary

• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet

• Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet

• Texas Instruments, UCC53x0xD Evaluation Module user's guide

14.2 Certifications

UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate

Number: 20170718-E181974,

14.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 7. Related Links

PARTS PRODUCT FOLDER ORDER NOW TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

UCC5310 Click here Click here Click here Click here Click here

UCC5320 Click here Click here Click here Click here Click here

UCC5350 Click here Click here Click here Click here Click here

UCC5390 Click here Click here Click here Click here Click here

14.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

14.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.6 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

14.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

l TEXAS INSTRUMENTS

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14.8 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

l TEXAS INSTRUMENTS wwwu com

www.ti.com

PACKAGE OUTLINE

TYP-.244.228

-6.195.80[ ]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

TYP-.010.005

-0.250.13[ ]

0- 8 -.010.004

-0.250.11[ ]

.010

[0.25]

-.050.016

-1.270.41[ ]

.041

[1.04]

NOTE 3

-.197.189

-5.004.81[ ]

NOTE 4

-.157.150

-3.983.81[ ]

SOIC

SOIC - 1.75 mm max height

D0008B

4221445/B 04/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15], per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

TYPICAL

DETAIL A

SCALE 2.800

UCC5310

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‘5‘ TEXAS INSTRUMENTS 4L www.“ com

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27] (.217)

[5.5]

8X (.061 )

[1.55]

8X (.024)

[0.6]

8X (.055)

[1.4]

8X (.024)

[0.6]

6X (.050 )

[1.27]

SOIC

SOIC - 1.75 mm max height

D0008B

4221445/B 04/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

OPENING

SOLDER MASK DETAILS

SOLDER MASK METAL

SOLDER MASK

DEFINED

SCALE:6X

LAND PATTERN EXAMPLE

SYMM

SEE

DETAILS

IPC-7351 NOMINAL

.150 [3.85] CLEARANCE / CREEPAGE

SYMM

HV / ISOLATION OPTION

.162 [4.1] CLEARANCE / CREEPAGE

SYMM

SEE

DETAILS

SYMM

UCC5310

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www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27]

(.213)

[5.4]

8X (.055)

[1.4]

8X (.024)

[0.6]

6X (.050 )

[1.27]

(.217)

[5.5]

SOIC

SOIC - 1.75 mm max height

D0008B

4221445/B 04/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

HV / ISOLATION OPTION

.162 [4.1] CLEARANCE / CREEPAGE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SOLDER PASTE EXAMPLE

SCALE:6X

SYMM

IPC-7351 NOMINAL

.150 [3.85] CLEARANCE / CREEPAGE

SYMM

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I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples Samples Samples Samples Sample: Sample: Samples Samples Samples Samples Samples Samples Samples Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UCC5310MCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5310M

UCC5310MCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5310M

UCC5310MCDWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5310MC

UCC5310MCDWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5310MC

UCC5320ECD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5320E

UCC5320ECDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5320E

UCC5320SCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5320S

UCC5320SCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5320S

UCC5320SCDWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5320SC

UCC5320SCDWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5320SC

UCC5350MCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5350M

UCC5350MCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5350M

UCC5350MCDWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5350MC

UCC5350MCDWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5350MC

UCC5350SBD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5350SB

UCC5350SBDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5350SB

UCC5390ECD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 53X0E

UCC5390ECDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 53X0E

UCC5390ECDWV ACTIVE SOIC DWV 8 64 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5390EC

UCC5390ECDWVR ACTIVE SOIC DWV 8 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 5390EC

I TEXAS INSTRUMENTS Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UCC5390SCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 53X0S

UCC5390SCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 53X0S

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC5350, UCC5390 :

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 3

•Automotive: UCC5350-Q1, UCC5390-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I‘KO '«Pt» Reel DlameIer A0 Dimension designed to accommodate the component Width Bo Dimension designed to accommodate the component Iength K0 Dimension designed to accommodate the component thickness 7 w Overau Wiotn onhe carrier Iape i P1 Pitch between successive cawty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE QOODOOOO ,,,,,,,,,,, ‘ User DIreCIIOn 0' Feed SprockeI Hoies Pockel Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UCC5310MCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC5310MCDWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1

UCC5320ECDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC5320SCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC5320SCDWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1

UCC5350MCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC5350MCDWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1

UCC5350SBDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC5390ECDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

UCC5390ECDWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1

UCC5390SCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jul-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC5310MCDR SOIC D 8 2500 350.0 350.0 43.0

UCC5310MCDWVR SOIC DWV 8 1000 350.0 350.0 43.0

UCC5320ECDR SOIC D 8 2500 350.0 350.0 43.0

UCC5320SCDR SOIC D 8 2500 350.0 350.0 43.0

UCC5320SCDWVR SOIC DWV 8 1000 350.0 350.0 43.0

UCC5350MCDR SOIC D 8 2500 350.0 350.0 43.0

UCC5350MCDWVR SOIC DWV 8 1000 350.0 350.0 43.0

UCC5350SBDR SOIC D 8 2500 350.0 350.0 43.0

UCC5390ECDR SOIC D 8 2500 350.0 350.0 43.0

UCC5390ECDWVR SOIC DWV 8 1000 350.0 350.0 43.0

UCC5390SCDR SOIC D 8 2500 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Jul-2020

Pack Materials-Page 2

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

DWV0008A

www.ti.com

PACKAGE OUTLINE

TYP

11.5 0.25

2.8 MAX

TYP

0.33

0.13

0-8

6X 1.27

8X 0.51

0.31

3.81

0.46

0.36

1.0

0.5

0.25

GAGE PLANE

NOTE 3

5.95

5.75

NOTE 4

7.6

7.4

(2.286)

(2)

4218796/A 09/2013

SOIC - 2.8 mm max heightDWV0008A

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

0.25 C A B

AREA

PIN 1 ID

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.000

DWV0008A j? ,,,,,,,,,,,,,,,,,,,, :L H WE \ pm ‘ CE

www.ti.com

EXAMPLE BOARD LAYOUT

(10.9)

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

8X (1.8)

8X (0.6)

6X (1.27)

4218796/A 09/2013

SOIC - 2.8 mm max heightDWV0008A

SOIC

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL

SOLDER MASK

DEFINED

DWV0008A

www.ti.com

EXAMPLE STENCIL DESIGN

8X (1.8)

8X (0.6)

6X (1.27)

(10.9)

4218796/A 09/2013

SOIC - 2.8 mm max heightDWV0008A

SOIC

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

SYMM

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

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Texas Instruments 的 UCC53x0 规格书

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