Texas Instruments 的 CD54,74HC(T)534,564 规格书

U Ordering & Technical Design a 3 Support 5 o . quahly documentation development (raming I TEXAS INSTRUMENTS
CDx4HC534, CDx4HCT534, CDx4HC564, CDx4HCT564 High-Speed CMOS Logic Octal
D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered
1 Features
• Buffered inputs
• Common three-state output-enable control
• Three-state outputs
• Bus line driving capability
• Typical propagation delay = 13 ns at VCC = 5 V,
CL = 15 pF, TA = 25℃ (clock to output)
• Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads
– Bus driver outputs: 15 LSTTL loads
• Wide operating temperature range: –55℃ to 125℃
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
Logic ICs
• HC types
– 2 V to 6 V operation
– High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5 V
• HCT types
– 4.5 V to 5.5 V operation
– Direct LSTTL input logic compatibility,
VIL = 0.8 V (max), VIH = 2 V (min)
– CMOS input compatibility, II ≤ 1 μA at VOL, VOH
2 Description
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are
high speed Octal D-Type Flip-Flops manufactured
with silicon gate CMOS technology. They possess the
low power consumption of standard CMOS integrated
circuits, as well as the ability to drive 15 LSTTL loads.
Due to the large output drive capability and the three-
state feature, these devices are ideally suited for
interfacing with bus lines in a bus organized system.
The two types are functionally identical and differ only
in their pinout arrangements.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD74HC564M SOIC (20) 12.80 mm × 7.50 mm
CD74HCT564M SOIC (20) 12.80 mm × 7.50 mm
CD74HC534E PDIP (20) 25.40 mm × 6.35 mm
CD74HC564E PDIP (20) 25.40 mm × 6.35 mm
CD74HCT534E PDIP (20) 25.40 mm × 6.35 mm
CD74HCT564E PDIP (20) 25.40 mm × 6.35 mm
CD54HC534F3A CDIP (20) 26.92 mm × 6.92 mm
CD54HCT534F3A CDIP (20) 26.92 mm × 6.92 mm
CD54HCT564F3A CDIP (20) 26.92 mm × 6.92 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet
Functional Diagram
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings(1) ....................................4
5.2 Recommended Operating Conditions ........................4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................5
5.5 Prerequisite for Switching Characteristics.................. 6
5.6 Switching Characteristics............................................7
6 Parameter Measurement Information............................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Device Functional Modes..........................................10
8 Power Supply Recommendations................................11
9 Layout............................................................................. 11
9.1 Layout Guidelines..................................................... 11
10 Device and Documentation Support..........................12
10.1 Receiving Notification of Documentation Updates..12
10.2 Support Resources................................................. 12
10.3 Trademarks............................................................. 12
10.4 Electrostatic Discharge Caution..............................12
10.5 Glossary..................................................................12
11 Mechanical, Packaging, and Orderable
Information.................................................................... 12
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2004) to Revision D (January 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com
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CD54HCT564 CD74HCT564
l TEXAS INSTRUMENTS 4:: amfififimmmmm a==qm=°m% GND fill an a D1 :1 n2 [1 n: a ma US. can m E GND IE dlfillidlfllfillillsllflLflLEl .5 o \8‘8‘2‘8‘2‘fl2‘ 00 1‘4
4 Pin Configuration and Functions
HC/HCT534
J or N package
20-Pin CDIP or PDIP
Top View
HC/HCT564
J, N, or DW package
20-Pin CDIP, PDIP, or SOIC
Top View
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CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022
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5 Specifications
5.1 Absolute Maximum Ratings(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input diode current For VI < –0.5 V or VI > VCC + 0.5 V ±20 mA
IOK Output diode current For VO < –0.5 V or VO > VCC + 0.5 V ±20 mA
IODrain current, per output For –0.5 V < VO < VCC + 0.5 V ±35 mA
IOOutput source or sink current per output pin For VO > –0.5 V or VO < VCC + 0.5 V ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature 150 °C
Tstg Storage temperature range –65 150 °C
Lead temperature (Soldering 10s) (SOIC - lead tips only) 300 °C
(1) Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied.
5.2 Recommended Operating Conditions
MIN MAX UNIT
VCC Supply voltage range HC types 2 6 V
HCT types 4.5 5.5
VI, VOInput or output voltage 0 VCC V
ttInput rise and fall time
2 V 1000
ns4.5 V 500
6 V 400
TATemperature range –55 125 ℃
5.3 Thermal Information
THERMAL METRIC
D (SOIC) N (PDIP)
UNIT16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance(1) 58 69 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com
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TEXAS INSTRUMENTS
5.4 Electrical Characteristics
PARAMETER TEST
CONDITIONS(2) VCC (V) 25℃–40℃ to 85℃–55℃ to 125℃
UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
VIH
High level input
voltage
2 1.5 1.5 1.5
V4.5 3.15 3.15 3.15
6 4.2 4.2 4.2
VIL
Low level input
voltage
2 0.5 0.5 0.5
V4.5 1.35 1.35 1.35
6 1.8 1.8 1.8
VOH
High level output
voltage
IOH = –20 µA 2 1.9 1.9 1.9
V
IOH = –20 µA 4.5 4.4 4.4 4.4
IOH = –20 µA 6 5.9 5.9 5.9
High level output
voltage
IOH = –6 mA 4.5 3.98 3.84 3.7
IOH = –7.8 mA 6 5.48 5.34 5.2
VOL
Low level output
voltage
IOL = 20 µA 2 0.1 0.1 0.1
V
IOL = 20 µA 4.5 0.1 0.1 0.1
IOL = 20 µA 6 0.1 0.1 0.1
Low level output
voltage
IOL = 6 mA 4.5 0.26 0.33 0.4
IOL = 7.8 mA 6 0.26 0.33 0.4
II
Input leakage
current VI = VCC or GND 6 ±0.1 ±1 ±1 µA
ICC Supply current VI = VCC or GND 6 8 80 160 µA
IOZ
Three-state leakage
current VO = VCC or GND 6 ±0.5 ±5.0 ±10 µA
HCT TYPES
VIH
High level input
voltage
4.5 to
5.5 2 2 2 V
VIL
Low level input
voltage
4.5 to
5.5 0.8 0.8 0.8 V
VOH
High level output
voltage VOH = –20 µA 4.5 4.4 4.4 4.4
V
High level output
voltage VOH = –6 mA 4.5 3.98 3.84 3.7
VOL
Low level output
voltage VOL = 20 µA 4.5 0.1 0.1 0.1
V
Low level output
voltage VOL = 6 mA 4.5 0.26 0.33 0.4
II
Input leakage
current VI = VCC and GND 5.5 ±0.1 ±1 ±1 µA
ICC Supply current VI = VCC and GND 5.5 8 80 160 µA
IOZ
Three-state leakage
current VO = VCC or GND 5.5 ±0.5 ±5.0 ±10 µA
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CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022
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TEXAS INSTRUMENTS
5.4 Electrical Characteristics (continued)
PARAMETER TEST
CONDITIONS(2) VCC (V) 25℃–40℃ to 85℃–55℃ to 125℃
UNIT
MIN TYP MAX MIN MAX MIN MAX
ΔICC (1) Additional supply
current per input pin
D0 - D7 inputs held
at VCC –2.1
4.5 to
5.5 100 54 67.5 73.5
µA
CP input held at
VCC –2.1
4.5 to
5.5 100 108 135 147
OE input held at
VCC –2.1
4.5 to
5.5 100 198 247.5 269.5
(1) For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
(2) VI = VIH or VIL.
5.5 Prerequisite for Switching Characteristics
PARAMETER VCC(V) 25℃–40℃ to 85℃–55℃ to 125℃
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
fMAX Maximum clock frequency
2 6 5 4
MHz4.5 30 25 20
6 35 29 23
tWClock pulse width
2 80 100 120
ns4.5 16 20 24
6 14 17 20
tSU Setup time data to clock
2 60 75 90
ns4.5 12 15 18
6 10 13 15
tHHold time data to clock
2 5 5 5
ns4.5 5 5 5
6 5 5 5
HCT TYPES
fMAX Maximum clock frequency 4.5 25 20 16 MHz
tWClock pulse width 4.5 20 25 30 ns
tSU Setup time data to clock 4.5 20 25 30 ns
tH
Hold time
Data to clock (534) 4.5 5 5 5 ns
tH
Hold time
Data to clock (564) 4.5 3 3 3 ns
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com
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TEXAS INSTRUMENTS
5.6 Switching Characteristics
CL = 50 pF, Input tr, tf = 6 ns
PARAMETER VCC (V) 25℃–40℃ to 85℃–55℃ to 125℃
UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL Propagation delay clock to output
2 165 205 250
ns4.5 13(3) 33 41 50
6 28 35 43
tPL, tPHZ Output disable to Q (534)
2 150 190 225
ns4.5 12(3) 30 38 45
6 26 33 38
tPLZ, tPHZ Output disable to Q (564)
2 135 170 205
ns4.5 12(3) 27 34 41
6 23 29 35
tPZL, tPZH Output enable to Q
2 150 190 225
ns4.5 12(3) 30 38 45
6 26 33 38
fMAX Maximum clock frequency 5 60(4) MHz
tTHL, tTLH Output transition time
2 60 75 90
ns4.5 12 15 18
6 10 13 15
CIInput capacitance 10 10 10 10 pF
COThree-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1) (2) 5 32 pF
HCT TYPES
tPHL, tPLH Propagation delay clock to output 4.5 14(3) 35 44 53 ns
tPLZ, tPHZ Output disable to Q 4.5 12(3) 30 38 45 ns
tPHL, tPZH Output enable to Q 4.5 14(3) 35 44 53 ns
fMAX Maximum clock frequency 5 50(4) MHz
tTLH, tTHL Output transition time 4.5 12 15 18 ns
CIInput capacitance 10 10 10 10 pF
COThree-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1) (2) 5 36 pF
(1) CPD is used to determine the dynamic power consumption, per package.
(2) PD = CPD VCC 2 fi + Σ CL VCC 2 fO where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage.
(3) CL = 15 pF and VCC = 5 V.
(4) CL = 15 pF.
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CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022
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I TEXAS INSTRUMENTS \ 77* DH ‘ \ \ HF \ DH ‘ ax. 777 VOL \ \ 4" I" o
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
CL(1)
RL
From Output
Under Test
VCC
Test
Point
S1
S2
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for 3-State Outputs
CL(1)
From Output
Under Test
Test
Point
(1) CL includes probe and test-fixture capacitance.
Figure 6-2. Load Circuit for Push-Pull Outputs
50%Input 50%
VCC
0 V
50% 50%
VOH
VOL
tPLH(1) tPHL(1)
VOH
VOL
tPHL(1) tPLH(1)
Output
Output 50% 50%
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Setup Propagation Delays
50%
Output
Control 50%
VCC
0 V
50%
50%
§9CC
VOL
tPZL(3) tPLZ(4)
90%
VOH
§0 V
tPZH(3) tPHZ(4)
Output
Waveform 1
S1 at VLOAD(1)
Output
Waveform 2
S1 at GND(2)
10%
(1) tPLZ and tPHZ are the same as tdis.
(2) tPZL and tPZH are the same as ten.
Figure 6-4. Voltage Waveforms, Standard CMOS
Inputs Propagation Delays
VOH
VOL
Output
VCC
0 V
Input
tf(1)
tr(1)
90%
10%
90%
10%
tr(1)
90%
10%
tf(1)
90%
10%
(1) The greater between tr and tf is the same as tt.
Figure 6-5. Voltage Waveforms, Input and Output Transition Times for Standard CMOS Input Devices
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
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I TEXAS INSTRUMENTS 77777 3" 3v I 1 1 :4—>F H x I r 7 7 ~ 1 ‘ 1 = w \ W“ \ s \ \ \ \ 7 7 \HF H k—>F r ‘ ‘ H x , , w ‘ % ‘ ‘ 5 52 CLOSED = u v
1.3VInput 1.3V
3V
0 V
50% 50%
VOH
VOL
tPLH
(1) tPHL
(1)
VOH
VOL
tPHL
(1) tPLH
(1)
Output
Waveform 1
Output
Waveform 2 50% 50%
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-6. Voltage Waveforms, TTL-Compatible
CMOS Inputs Propagation Delays
1.3VInput 1.3V
3V
0 V
50%
50%
VCC
VOL
tPZL
(1) tPLZ
(2)
90%
VOH
0 V
tPZH
(1) tPHZ
(2)
Output
Waveform 1
S1 CLOSED,
S2 OPEN
Output
Waveform 2
S1 OPEN,
S2 CLOSED
10%
(1) tPLZ and tPHZ are the same as tdis.
(2) tPZL and tPZH are the same as ten.
Figure 6-7. Voltage Waveforms, TTL-Compatible
CMOS Inputs Propagation Delays
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CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022
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TEXAS INSTRUMENTS
7 Detailed Description
7.1 Overview
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon
gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well
as the ability to drive 15 LSTTL loads. Due to the large output drive capability and the three-state feature, these
devices are ideally suited for interfacing with bus lines in a bus organized system. The two types are functionally
identical and differ only in their pinout arrangements.
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive edge triggered flip-flops. Data at the D inputs, meeting
the setup and hold time requirements, are inverted and transferred to the Q outputs on the positive going
transition of the CLOCK input. When a high logic level is applied to the OUTPUT ENABLE input, all outputs go
to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
The HCT logic family is speed, function, and pin compatible with the standard LS logic family.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Truth Table(1)
INPUTS OUTPUT
OE CP Dn Qn
L ↑ H L
L ↑ L H
L L X No change
H X X Z
(1) H = high level (steady state), L = low level (steady state),
X= don’t care, ↑ = transition from low to high level, Z = High
impedance state
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
SCHS188D – FEBRUARY 1998 – REVISED JANUARY 2022 www.ti.com
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I TEXAS INSTRUMENTS
8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
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l TEXAS INSTRUMENTS Am
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
CD54HC534, CD74HC534, CD54HC564, CD74HC564
CD54HCT534, CD74HCT534, CD54HCT564, CD74HCT564
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{I} TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8681401RA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8681401RA
CD54HC534F3A Samples
5962-8681501RA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8681501RA
CD54HC564F3A Samples
5962-8984901RA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8984901RA
CD54HCT534F3A Samples
CD54HC534F3A ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8681401RA
CD54HC534F3A Samples
CD54HC564F3A ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8681501RA
CD54HC564F3A Samples
CD54HCT534F3A ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8984901RA
CD54HCT534F3A Samples
CD54HCT564F3A ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 CD54HCT564F3A Samples
CD74HC534E ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC534E Samples
CD74HC534EE4 ACTIVE PDIP N 20 20 TBD Call TI Call TI -55 to 125 Samples
CD74HC564E ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC564E Samples
CD74HC564M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC564M Samples
CD74HC564M96 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC564M Samples
CD74HC564M96E4 ACTIVE SOIC DW 20 2000 TBD Call TI Call TI -55 to 125 Samples
CD74HCT534E ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT534E Samples
CD74HCT564E ACTIVE PDIP N 20 20 RoHS &
Non-Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT564E Samples
CD74HCT564M ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT564M Samples
CD74HCT564MG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT564M Samples
(1) The marketing status values are defined as follows:
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC534, CD54HC564, CD54HCT534, CD54HCT564, CD74HC534, CD74HC564, CD74HCT534, CD74HCT564 :
•Catalog : CD74HC534, CD74HC564, CD74HCT534, CD74HCT564
•Military : CD54HC534, CD54HC564, CD54HCT534, CD54HCT564
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
Addendum-Page 2
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2022
•Military - QML certified for Military and Defense Applications
Addendum-Page 3
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC564M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC564M96 SOIC DW 20 2000 367.0 367.0 45.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Aug-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC534E N PDIP 20 20 506 13.97 11230 4.32
CD74HC564E N PDIP 20 20 506 13.97 11230 4.32
CD74HC564M DW SOIC 20 25 507 12.83 5080 6.6
CD74HCT534E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT564E N PDIP 20 20 506 13.97 11230 4.32
CD74HCT564M DW SOIC 20 25 507 12.83 5080 6.6
CD74HCT564MG4 DW SOIC 20 25 507 12.83 5080 6.6
Pack Materials-Page 3
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
DW0020A I
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DW0020A
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DW0020A $$$$$fififiifi%
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
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