Texas Instruments 的 BQ2201 规格书

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Features
➤Power monitoring and switching
for 3-volt battery-backup applica-
tions
➤Write-protect control
➤3-volt primary cell inputs
➤Less than 10ns chip-enable
propagation delay
➤5% or 10% supply operation
General Description
The CMOS bq2201 SRAM Nonvolatile
Controller Unit provides all necessary
functions for converting a standard
CMOS SRAM into nonvolatile
read/write memory.
A precision comparator monitors the
5V VCC input for an out-of-tolerance
condition. When out of tolerance is
detected, a conditioned chip-enable
output is forced inactive to write-
protect any standard CMOS SRAM.
During a power failure, the external
SRAM is switched from the VCC
supply to one of two 3V backup sup-
plies. On a subsequent power-up, the
SRAM is write-protected until a
power-valid condition exists.
The bq2201 is footprint- and timing-
compatible with industry stan-
dards with the added benefit of a
chip-enable propagation delay of
less than 10ns.
1
SRAM Nonvolatile Controller Unit
bq2201
Oct. 1998 D
Pin Names
VOUT Supply output
BC1—BC23-volt primary backup cell inputs
THS Threshold select input
CE chip-enable active low input
CECON Conditioned chip-enable output
VCC +5-volt supply input
VSS Ground
NC No Connect
Functional Description
Pin Connections
An external CMOS static RAM can be battery-backed
using the VOUT and the conditioned chip-enable output
pin from the bq2201. As VCC slews down during a power
failure, the conditioned chip-enable output CECON is
forced inactive independent of the chip-enable input CE.
This activity unconditionally write-protects external
SRAM as VCC falls to an out-of-tolerance threshold VPFD.
VPFD is selected by the threshold select input pin, THS.
If THS is tied to VSS, power-fail detection occurs at 4.62V
typical for 5% supply operation. If THS is tied to VCC,
power-fail detection occurs at 4.37V typical for 10% sup-
ply operation. The THS pin must be tied to VSS or VCC for
proper operation.
If a memory access is in process during power-fail detec-
tion, that memory cycle continues to completion before the
memory is write-protected. If the memory cycle is not ter-
minated within time tWPT, the CECON output is uncondi-
tionally driven high, write-protecting the memory.
1
PN220101.eps
8-Pin Narrow DIP or SOIC
2
3
4
8
7
6
5
VCC
BC1
CECON
CE
VOUT
BC2
THS
VSS
1
PN2201E.eps
16-Pin SOIC
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
V
CC
NC
BC
1
NC
CE
CON
NC
CE
NC
V
OUT
NC
BC
2
NC
THS
NC
VSS
rrdiow VLU L" 130$ aflc £11 7 (lm M—U—l
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to one of the two external
backup energy sources. CECON is held high by the VOUT
energy source.
During power-up, VOUT is switched back to the VCC sup-
ply as VCC rises above the backup cell input voltage
sourcing VOUT. The CECON output is held inactive for
time tCER (120 ms maximum) after the supply has
reached VPFD, independent of the CE input, to allow for
processor stabilization.
During power-valid operation, the CE input is fed
through to the CECON output with a propagation delay
of less than 10ns. Nonvolatility is achieved by hardware
hookup, as shown in Figure 1.
Energy Cell Inputs—BC1,BC
2
Two primary backup energy source inputs are provided
on the bq2201. The BC1and BC2inputs accept a 3V pri-
mary battery, typically some type of lithium chemistry.
If no primary cell is to be used on either BC1or BC2, the
unused input should be tied to VSS.
If both inputs are used, during power failure the VOUT
output is fed only by BC1as long as it is greater than
2.5V. If the voltage at BC1falls below 2.5V, an internal
isolation switch automatically switches VOUT from BC1
to BC2.
To prevent battery drain when there is no valid data to
retain, VOUT and CECON are internally isolated from
BC1and BC2by either of the following:
■Initial connection of a battery to BC1or BC2,or
■Presentation of an isolation signal on CE.
A valid isolation signal requires CE low as VCC crosses
both VPFD and VSO during a power-down. See Figure 2.
Between these two points in time, CE must be brought
to the point of (0.48 to 0.52)*VCC and held for at least
700ns. The isolation signal is invalid if CE exceeds
0.54*VCC at any point between VCC crossing VPFD and
VSO.
The appropriate battery is connected to VOUT and CECON
immediately on subsequent application and removal of VCC.
2
FG220101.eps
VCC
CE
BC1
THS
VSS
VOUT
CECON
BC2
bq2201
VCC
CE
CMOS
SRAM
5V
From Address Decoder
3V
Primary
Cell
3V
Primary
Cell
Figure 1. Hardware Hookup (5% Supply Operation)
Oct. 1998 D
TD220101.eps
VCC
CE
VPFD
VSO
0.5 VCC
700ns
Figure 2. Battery Isolation Signal
bq2201
3
Absolute Maximum Ratings
Symbol Parameter Value Unit Conditions
VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V
VTDC voltage applied on any pin excluding VCC
relative to VSS -0.3 to 7.0 V VT≤VCC + 0.3
TOPR Operating temperature
0 to +70 °C Commercial
-40 to +85 °C Industrial “N”
TSTG Storage temperature -55 to +125 °C
TBIAS Temperature under bias -40 to +85 °C
TSOLDER Soldering temperature 260 °C For 10 seconds
IOUT VOUT current 200 mA
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Recommended DC Operating Conditions (TA=T
OPR)
Symbol Parameter Minimum Typical Maximum Unit Notes
VCC Supply voltage
4.75 5.0 5.5 V THS = VSS
4.50 5.0 5.5 V THS = VCC
VSS Supply voltage 0 0 0 V
VIL Input low voltage -0.3 - 0.8 V
VIH Input high voltage 2.2 - VCC + 0.3 V
VBC1,
VBC2 Backup cell voltage 2.0 - 4.0 V
THS Threshold select -0.3 - VCC + 0.3 V
Note: Typical values indicate operation at TA= 25°C, VCC = 5V or VBC.
Oct. 1998 D
bq2201
4
DC Electrical Characteristics (TA=T
OPR,V
CC = 5V ±10%)
Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes
ILI Input leakage current - - ±1µAV
IN =V
SS to VCC
VOH Output high voltage 2.4 - - V IOH = -2.0mA
VOHB VOH, BC supply VBC - 0.3 - - V VBC >V
CC,I
OH = -10µA
VOL Output low voltage - - 0.4 V IOL = 4.0mA
ICC Operating supply current - 3 5 mA No load on VOUT and CECON.
VPFD Power-fail detect voltage
4.55 4.62 4.75 V THS = VSS
4.30 4.37 4.50 V THS = VCC
VSO Supply switch-over voltage - VBC -V
I
CCDR Data-retention mode
current - - 100 nA
VOUT data-retention current
to additional memory not in-
cluded.
VOUT1 VOUT voltage VCC - 0.2 - - V VCC >V
BC,I
OUT = 100mA
VCC - 0.3 - - V VCC >V
BC,I
OUT = 160mA
VOUT2 VOUT voltage VBC - 0.3 - - V VCC <V
BC,I
OUT = 100µA
VBC Active backup cell
voltage
-V
BC2 -VV
BC1 < 2.5V
-V
BC1 -VV
BC1 > 2.5V
IOUT1 VOUT current - - 160 mA VOUT >V
CC - 0.3V
IOUT2 VOUT current - 100 - µAV
OUT >V
BC - 0.2V
Note: Typical values indicate operation at TA= 25°C, VCC = 5V or VBC.
Oct. 1998 D
bq2201
510$) L
5
AC Test Conditions
Parameter Test Conditions
Input pulse levels 0V to 3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5V (unless otherwise specified)
Output load (including scope and jig) See Figure 3
FG220102.eps
5V
960
100pF
CECON
510
Figure 3. Output Load
Capacitance (TA= 25°C, F = 1MHz, VCC = 5.0V)
Symbol Parameter Minimum Typical Maximum Unit Conditions
CIN Input capacitance - - 8 pF Input voltage = 0V
COUT Output capacitance - - 10 pF Output voltage = 0V
Note: This parameter is sampled and not 100% tested.
Oct. 1998 D
bq2201
6
TD220102.eps
VCC
CECON
tPF
tFS
4.75
VPFD
4.25 VSO
tWPT VOHB
CE
Power-Down Timing
Power-Fail Control (TA = TOPR)
Symbol Parameter Minimum Typical Maximum Unit Notes
tPF VCC slew, 4.75V to 4.25V 300 - - µs
tFS VCC slew, 4.25V to VSO 10 - - µs
tPU VCC slew, 4.25V to 4.75V 0 - - µs
tCED Chip-enable propagation
delay - 7 10 ns
tCER Chip-enable recovery 40 80 120 ms
Time during which SRAM is
write-protected after VCC
passes VPFD on power-up.
tWPT Write-protect time 40 100 150 µs
Delay after VCC slews down
past VPFD before SRAM is
write-protected.
Note: Typical values indicate operation at TA= 25°C.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Oct. 1998 D
bq2201
‘W F
7
Oct. 1998 D
TD220103.eps
VCC
tPU
CE
CECON VOHB
VSO
4.25 VPFD
4.75
tCER
tCED tCED
Power-Up Timing
bq2201
Dimension Minimum Maximum maria uvuu e m : Dimension Minimum Maximum 3 4L J; : # D 77 7 fl ‘ B :
8
Oct. 1998 D
8-Pin SOIC Narrow (SN)
Dimension Minimum Maximum
A 0.060 0.070
A1 0.004 0.010
B 0.013 0.020
C 0.007 0.010
D 0.185 0.200
E 0.150 0.160
e 0.045 0.055
H 0.225 0.245
L 0.015 0.035
All dimensions are in inches.
8-Pin SOIC Narrow (SN)
8-Pin DIP Narrow (PN)
Dimension Minimum Maximum
A 0.160 0.180
A1 0.015 0.040
B 0.015 0.022
B1 0.055 0.065
C 0.008 0.013
D 0.350 0.380
E 0.300 0.325
E1 0.230 0.280
e 0.300 0.370
G 0.090 0.110
L 0.115 0.150
S 0.020 0.040
All dimensions are in inches.
8-Pin DIP Narrow (PN)
bq2201
HMHHHHH UUUUUUUU q if g”? Lumumui W fl Dimension Minimum Maximum
9
bq2201
Oct. 1998 D
S: 16-Pin SOIC
e
DB
E
H
A1
A
C
L
.004
16-Pin S (SOIC)
Dimension Minimum Maximum
A 0.095 0.105
A1 0.004 0.012
B 0.013 0.020
C 0.008 0.013
D 0.400 0.415
E 0.290 0.305
e 0.045 0.055
H 0.395 0.415
L 0.020 0.040
All dimensions are in inches.
10
bq2201
Oct. 1998 D
Data Sheet Revision History
Change No. Page No. Description Nature of Change
1 Added industrial temperature range
2 1, 3, 4 10% supply operation Was: THS tied to VOUT
Is: THS tied to VCC
3 1, 9, 11 Added 16-pin package option
Note: Change 1 = Sept. 1991 B changes from Sept. 1990 A.
Change 2 = Aug. 1997 C changes from Sept. 1991 B.
Change 3 = Oct. 1998 D changes from Aug. 1997 C.
11
Ordering Information
bq2201
Package Option:
PN = 8-pin narrow plastic DIP
SN = 8-pin narrow SOIC
S = 16-pin SOIC
Device:
bq2201 Nonvolatile SRAM Controller
Temperature Range:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)
bq2201
Oct. 1998 D
I TEXAS INSTRUMENTS Samples Samples
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
BQ2201SN-N ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2201
-N
BQ2201SN-NTR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2201
-N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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I TEXAS INSTRUMENTS
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Addendum-Page 2
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ2201SN-NTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Feb-2018
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ2201SN-NTR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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