STIPN2M50T-HL 规格书

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NDIP-26L in line

Features

• IPM 2 A, 500 V, RDS(on) = 1.7 Ω, 3-phase MOSFET inverter bridge including

control ICs for gate driving

• Optimized for low electromagnetic interference

• 3.3 V, 5 V, 15 V CMOS/TTL input comparators with hysteresis and pull-down/

pull-up resistors

• Undervoltage lockout

• Internal bootstrap diode

• Interlocking function

• Shutdown function

• Comparator for fault protection against overtemperature and overcurrent

• Op-amp for advanced current sensing

• Optimized pinout for easy board layout

• NTC for temperature control (UL 1434 CA 2 and 4)

• Up to ±2 kV ESD protection (HBM C = 100 pF, R = 1.5 kΩ)

Applications

•3-phase inverters for motor drives

•Dish washers

•Refrigerator compressors

•Air-conditioning fans

•Draining and recirculation pumps

Description

This SLLIMM (small low-loss intelligent molded module) nano provides a compact,

high-performance AC motor drive in a simple, rugged design. It is composed of six

MOSFETs and three half-bridge HVICs for gate driving, providing low

electromagnetic interference (EMI) characteristics with optimized switching speed.

The package is optimized for thermal performance and compactness in built-in motor

applications, or other low power applications where assembly space is limited. This

IPM includes an operational amplifier, completely uncommitted, and a comparator

that can be used to design a fast and efficient protection circuit. SLLIMM is a

trademark of STMicroelectronics.

Product status link

STIPN2M50T-HL

Product summary

Order code STIPN2M50T-HL

Marking IPN2M50T-HL

Package NDIP-26L

Packing Tube

SLLIMM-nano IPM, 3-phase inverter, 2 A, 1.7 Ω max., 500 V MOSFET

STIPN2M50T-HL

Datasheet

DS11753 - Rev 5 - March 2020

For further information contact your local STMicroelectronics sales office.

www.st.com

1Internal schematic diagram and pin configuration

Figure 1. Internal schematic diagram

NTC

GND(1 )

T/SD/OD (2)

VccW(3 )

HinW(4 )

LinW(5 )

OP+(6 )

OPOUT(7 )

OP-(8 )

VccV(9 )

HinV(10)

LinV(11 )

Cin(12)

VccU(13 )

HinU(14)

T/SD/OD(15)

LinU(16 ) (17)Vboot U

(18) P

(19)U,OUT U

(20)N U

(21)Vboot V

(22)V,OUT V

(23)N V

(24)Vboot W

(25)W,OUT W

(26)N W

GND

LIN

VCC

HVG

CIN

SD/OD

OUT

LVG

Vboot

HIN

GND

OPOUT

LIN

VCC

HVG

OP+

OP-

SD/OD

OUT

LVG

Vboot

HIN

GND

LIN

VCC

HVG

SD/OD

OUT

LVG

Vboot

HIN

GIPD120120170806SA

STIPN2M50T-HL

Internal schematic diagram and pin configuration

DS11753 - Rev 5 page 2/23

Table 1. Pin description

Pin Symbol Description

1 GND Ground

2 T/SD/OD NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)

3VCC W Low voltage power supply W phase

4 HIN W High-side logic input for W phase

5 LIN W Low-side logic input for W phase

6 OP+ Op-amp non inverting input

7OPOUT Op-amp output

8 OP- Op-amp inverting input

9VCC V Low voltage power supply V phase

10 HIN V High-side logic input for V phase

11 LIN V Low-side logic input for V phase

12 CIN Comparator input

13 VCC U Low voltage power supply for U phase

14 HIN U High-side logic input for U phase

15 T/SD/OD NTC thermistor terminal / shutdown logic input (active low) / open-drain (comparator output)

16 LIN U Low-side logic input for U phase

17 VBOOT U Bootstrap voltage for U phase

18 P Positive DC input

19 U, OUTUU phase output

20 NUNegative DC input for U phase

21 VBOOT V Bootstrap voltage for V phase

22 V, OUTVV phase output

23 NVNegative DC input for V phase

24 VBOOT W Bootstrap voltage for W phase

25 W, OUTWW phase output

26 NWNegative DC input for W phase

STIPN2M50T-HL

Internal schematic diagram and pin configuration

DS11753 - Rev 5 page 3/23

PIN 26 MU‘iULfLﬂJ‘i"JLF MN 17 /\ \ ,/ m \/ PIN 1 PIN 16

Figure 2. Pin layout (top view)

(*) (*)

(*) Dummy pin internally connected to P (positive DC input).

GADG130720161515FSR

PIN #1 ID

STIPN2M50T-HL

Internal schematic diagram and pin configuration

DS11753 - Rev 5 page 4/23

2Electrical ratings

2.1 Absolute maximum ratings

Table 2. Inverter part

Symbol Parameter Value Unit

VDSS MOSFET blocking voltage (or drain-source voltage) for each MOSFET (VIN(1)= 0 V) 500 V

± IDContinuous drain current each MOSFET (TC = 25 °C) 2 A

± IDP (2) Peak drain current each MOSFET (less than 1 ms) 4 A

PTOT Total power dissipation for each MOSFET (TC = 25 °C) TC = 25 °C 10.4 W

1. Applied between HINi, LINi and GND for i = U, V, W.

2. Pulse width limited by max. junction temperature.

Table 3. Control part

Symbol Parameter Min. Max. Unit

VOUT

Output voltage applied between OUTU, OUTV, OUTW -

GND Vboot - 21 Vboot + 0.3 V

VCC Low voltage power supply - 0.3 21 V

VCIN Comparator input voltage - 0.3 VCC + 0.3 V

Vop+ Op-amp non-inverting input - 0.3 VCC + 0.3 V

Vop- Op-amp inverting input - 0.3 VCC + 0.3 V

Vboot Bootstrap voltage - 0.3 620 V

VIN Logic input voltage applied between HIN, LIN and GND - 0.3 15 V

VT/SD/OD Open-drain voltage - 0.3 15 V

dVOUT/dt Allowed output slew rate 50 V/ns

Table 4. Total system

Symbol Parameter Value Unit

VISO Isolation withstand voltage applied between each pin and heat sink plate

(AC voltage, t = 60 s) 1000 Vrms

TJPower chip operating junction temperature range -40 to 150 °C

TCModule case operation temperature range -40 to 125 °C

STIPN2M50T-HL

Electrical ratings

DS11753 - Rev 5 page 5/23

2.2 Thermal data

Table 5. Thermal data

Symbol Parameter Value Unit

Rth(j-c) Thermal resistance junction-case single MOSFET 10.6 °C/W

Rth(j-c) Thermal resistance junction-ambient (per module) 22 °C/W

STIPN2M50T-HL

Thermal data

DS11753 - Rev 5 page 6/23

3Electrical characteristics

TJ = 25 °C unless otherwise specified.

3.1 Inverter part

Table 6. Static

Symbol Parameter Test conditions Min. Typ. Max. Unit

IDSS Zero-gate voltage drain current VDS = 500 V, VCC = 15 V, VBoot =

15 V 1 mA

V(BR)DSS Drain-source breakdown voltage VCC= Vboot = 15 V, VIN (1)= 0 V,

ID = 1 mA 500 V

RDS(on) Static drain-source turn-on

resistance

VCC = Vboot = 15 V, VIN(1)= 0 to 5

V, ID = 1.2 A 1.5 1.7 Ω

VSD Drain-source diode forward

voltage VIN(1)= 0 “logic state”, ID = 2 A 0.9 1.6 V

1. Applied between HINx, LINx and GND for x = U, V, W.

Table 7. Inductive load switching time and energy

Symbol Parameter Test conditions Min. Typ. Max. Unit

ton (1) Turn-on time

VDD = 300 V,

VCC = Vboot = 15 V,

VIN(2)= 0 to 5 V,

IC = 1.2 A

(see Figure 4. Switching time

definition )

- 267 -

tc(on) (1) Crossover time (on) - 153 -

toff (1) Turn-off time - 265 -

tc(off) (1) Crossover time (off) - 46 -

trr Reverse recovery time - 192 -

Eon Turn-on switching energy - 61 -

µJ

Eoff Turn-off switching energy - 4 -

1. tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of MOSFET

itself under the internally given gate driving conditions.

2. Applied between HINx, LINx and GND for x = U, V, W.

STIPN2M50T-HL

Electrical characteristics

DS11753 - Rev 5 page 7/23

5" Input UV LIN Vbooti Vbeot>Vcc RSD 7 WSW!» HIN HVG vcc OUT LVG —{ GND

Figure 3. Switching time test circuit

GIPD161120151702RV

Figure 4. Switching time definition

VDS IDID

VIN

tON

tC(ON)

VIN(ON) 10% ID 90% ID 10% VDS

(a) turn-on (b) turn-off

trr

100% ID 100% ID

VIN

VDS

tOFF tC(OFF)

VIN(OFF) 10% VDS 10% ID

AM09223V2

Figure 4. Switching time definition refers to HIN, LIN inputs (active high).

STIPN2M50T-HL

Inverter part

DS11753 - Rev 5 page 8/23

3.2 Control part

VCC = 15 V unless otherwise specified

Table 8. Low voltage power supply

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC_hys VCC UV hysteresis 1.2 1.5 1.8 V

VCC_thON VCC UV turn-ON threshold 11.5 12 12.5 V

VCC_thOFF VCC UV turn-OFF threshold 10 10.5 11 V

Iqccu Undervoltage quiescent supply

current

VCC = 15 V, T/SD/OD = 5 V; LIN = 0 V;

HIN = 0 V, CIN = 0 V 150 µA

Iqcc Quiescent current Vcc = 15 V, T/SD/OD = 5 V; LIN = 0 V;

HIN = 0 V, CIN = 0 V 1 mA

Vref Internal comparator (CIN)

reference voltage 0.5 0.54 0.58 V

Table 9. Bootstrapped voltage

Symbol Parameter Test conditions Min. Typ. Max. Unit

VBS_hys VBS UV hysteresis 1.2 1.5 1.8 V

VBS_thON VBS UV turn-ON threshold 11.1 11.5 12.1 V

VBS_thOFF VBS UV turn-OFF threshold 9.8 10 10.6 V

IQBSU

Undervoltage VBS quiescent

current

VBS < 9 V T/SD/OD = 5 V; LIN = 0 V and

HIN = 5 V; CIN = 0 V 70 110 µA

IQBS VBS quiescent current VBS = 15 V T/SD/OD = 5 V; LIN = 0 V

and HIN = 5 V; CIN = 0 V 200 300 µA

RDS(on) Bootstrap driver on-resistance LVG ON 120 Ω

Table 10. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

Vil Low logic level voltage 0.8 V

Vih High logic level voltage 2.25 V

IHINh HIN logic “1” input bias current HIN = 15 V 20 40 100 µA

IHINI HIN logic “0” input bias current HIN = 0 V 1 µA

ILINI LIN logic “1” input bias current LIN = 15 V 20 40 100 µA

ILINh LIN logic “0” input bias current LIN = 0 V 1 µA

ISDh SD logic “0” input bias current SD = 15 V 200 350 500 µA

ISDI SD logic “1” input bias current SD = 0 V 3 µA

Dt Dead time See Figure 9. Dead time and

interlocking waveform definitions 180 ns

STIPN2M50T-HL

Control part

DS11753 - Rev 5 page 9/23

Table 11. Op-amp characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Vio Input offset voltage Vic = 0 V, Vo = 7.5 V 6 mV

Iio Input offset current

Vic = 0 V, Vo = 7.5 V

4 40 nA

Iib Input bias current (1) 100 200 nA

VOL Low level output voltage RL = 10 kΩ to VCC 75 150 mV

VOH High level output voltage RL = 10 kΩ to GND 14 14.7 V

IoOutput short-circuit current

Source, Vid = +1 V; Vo = 0 V 16 30 mA

Sink, Vid = -1 V; Vo = VCC 50 80 mA

SR Slew rate Vi = 1 - 4 V; CL = 100 pF; unity gain 2.5 3.8 V/µs

GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz

Avd Large signal voltage gain RL = 2 kΩ 70 85 dB

SVR Supply voltage rejection ratio vs. VCC 60 75 dB

CMRR Common mode rejection ratio 55 70 dB

1. The direction of the input current is out of the IC.

Table 12. Sense comparator characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

Iib Input bias current VCIN = 1 V 1 µA

Vod Open-drain low level output

voltage Iod = 3 mA 0.5 V

RON_OD Open-drain low level output

resistance Iod = 3 mA 166 Ω

RPD_SD SD pull-down resistor (1) 125 kΩ

td_comp Comparator delay T/SD/OD pulled to 5 V through 100 kΩ

resistor 90 130 ns

SR Slew rate CL = 180 pF; Rpu = 5 kΩ 60 V/µs

tsd Shutdown to high / low-side

driver propagation delay VOUT = 0 V, Vboot = VCC, VIN = 0 to 3.3 V 50 125 200

tisd

Comparator triggering to high /

low-side driver turn-off

propagation delay

Measured applying a voltage step

from 0 V to 3.3 V to pin CIN 50 200 250

1. Equivalent values are as a result of the resistances of three drivers in parallel.

STIPN2M50T-HL

Control part

DS11753 - Rev 5 page 10/23

%\ “H_Hiﬂvxﬂ—o —_ _----

Table 13. Truth table

Conditions

Logic input (VI)Output

T/SD/OD LIN HIN LVG HVG

Shutdown enable half-bridge tri-state L X (1) X(1) L L

Interlocking half-bridge tri-state H H H L L

0 “logic state” half-bridge tri-state H L L L L

1 “logic state” low-side direct driving H H L H L

1 “logic state” high-side direct driving H L H L H

1. X: do not care.

3.2.1 NTC thermistor

Figure 5. Internal structure of SD and NTC

T/SD/OD

Vbias

RPD_SD

NTC

LIN

HIN

VCC

GND CIN

LVG

OUT

HVG

Vboot

SD/OD

R SD

C SD

RPD_SD: equivalent value as result of resistances of three drivers in parallel.

STIPN2M50T-HL

Control part

DS11753 - Rev 5 page 11/23

Figure 6. Equivalent resistance (NTC//RPD_SD)

100

120

140

-40 -20 0 20 40 60 80 100 120

Equivalent Resistance (kΩ)

Temperature (°C)

Figure 7. Equivalent resistance (NTC//RPD_SD) zoom

70 80 90 100 110 120

Equivalent Resistance (kΩ)

Temperature (°C)

STIPN2M50T-HL

Control part

DS11753 - Rev 5 page 12/23

Figure 8. Voltage of T/SD/OD pin according to NTC temperature

2.0

2.5

3.0

3.5

4.0

4.5

5.0

25 50 75 100 125

VSD(V)

Temperature (°C)

VBias = 5 V

RSD = 2.2 kΩ

SD/OD: high

VBias = 3.3 V

RSD = 1.0 kΩ

STIPN2M50T-HL

Control part

DS11753 - Rev 5 page 13/23

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3.3 Waveform definitions

Figure 9. Dead time and interlocking waveform definitions

INTERL

OCKING

INTERL

OCKING

INTERL

OCKING

INTERL

OCKING

STIPN2M50T-HL

Waveform definitions

DS11753 - Rev 5 page 14/23

SHUTDOWN cchun Var! ’ Van Va v, 7 v0 nan lu< a)="" s,="" a="" 5="">17; m (Mu VA =(Ra~,oul/Rsnl/Rpuu/l Rrrn)‘cs Ro~,an‘C:n '5 : (kw/ﬂnuol/ ch) ‘ Cm //Rr snl/ Rm: Ramon/”(rust)” Rm) + Rx Vow RM an 7’. VM Rump + Rn: Rm 317/] "M: Van : m m' VanVm S15

4Shutdown function

The device is equipped with three half-bridge IC gate drivers and integrates a comparator for fault detection.

The comparator has an internal voltage reference VREF connected to the inverting input, while the non-inverting

input pin (CIN) can be connected to an external shunt resistor for current monitoring.

Since the comparator is embedded in the U IC gate driver, in case of fault it disables directly the U outputs,

whereas the shutdown of V and W IC gate drivers depends on the RC value of the external SD circuitry, which

fixes the disabling time.

For an effective design of the shutdown circuit, please refer to Application note AN4966.

Figure 10. Shutdown timing waveforms

∗

≅

∗

RSD and CSD external circuitry must be designed to ensure

Please refer to AN4966 for further details.

* RNTC to be considered only when the NTC is internally connected to the T/SD/OD pin.

HIN or LIN

HVG or LVG

open -drain gate

(interna l)

VREF

CI N

PROTECT ION

SD/OD

T/SD/OD

U V, W

GADG250120171515FSR

STIPN2M50T-HL

Shutdown function

DS11753 - Rev 5 page 15/23

—«h HH‘

5Application circuit example

Figure 11. Application circuit example

ADC

PWR_GN D

SGN_GND

GND(1 )

T/SD/OD(15 )

HinW(4 )

VccW(3 )

OP+(6 )

LinW(5 )

VccV(9 )

OP-(8 )

OPOUT(7 )

Cin(12 )

LinV(11 )

HinV(10 )

HinU(14 )

VccU(13 )

LinU(16 )

T/SD/OD(2 )

(17)Vboot U

(18) P

(19)U,OUT U

(20)N U

(21)Vboot V

(22)V,OUT V

(23)N V

(24)Vboot W

(26)N W

(25)W,OUT W

R1 R2

RSD

RSF

Rshunt

CSF

C OP

CSD

CbootU

CbootV

CbootW

Cvdc

VDC

Vcc DZ1

DZ2

5V/3.3V

Cvcc C2

GND

LIN

VCC

LVG

SD/OD

OUT

HVG

Vboot

HIN

MICROCONTROLLE R

Temp.

Monitoring

HIN U

LIN U

LIN V

HIN V

LIN W

HIN W

ADC

NTC

GND

LIN

VCC

LVG

CIN

SD/OD

OUT

HVG

Vboot

HIN

GND

OPOUT

LIN

VCC

LVG

OP+

OP-

SD/OD

OUT

HVG

Vboot

HIN

GADG100620160912FSR

Application designers are free to use a different scheme according to the specifications of the device.

STIPN2M50T-HL

Application circuit example

DS11753 - Rev 5 page 16/23

5.1 Guidelines

• Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull-down resistor is built-in for each input. To

avoid input signal oscillation, the wiring of each input should be as short as possible, and the use of RC

filters (R1, C1) on each input signal is suggested. The filters should be with a time constant of about 100 ns

and placed as close as possible to the IPM input pins.

• The use of a bypass capacitor CVCC (aluminum or tantalum) can reduce the transient circuit demand on the

power supply. Also, to reduce any high-frequency switching noise distributed on the power lines, a

decoupling capacitor C2 (100 to 220 nF, with low ESR and low ESL) should be placed as close as possible

to the Vcc pin and in parallel with the bypass capacitor.

• The use of an RC filter (RSF, CSF) is recommended to prevent protection circuit malfunction. The time

constant (RSF x CSF) should be set to 1 μs and the filter must be placed as close as possible to the CIN pin.

• The SD is an input/output pin (open-drain type if it is used as output). A built-in thermistor NTC is internally

connected between the SD pin and GND. The voltage VSD-GND decreases as the temperature increases,

due to the pull-up resistor RSD. In order to keep the voltage always higher than the high-level logic threshold,

the pull-up resistor should be set to 1 kΩ or 2.2 kΩ for 3.3 V or 5 V MCU power supply, respectively. The

capacitor CSD of the filter on SD should be fixed no higher than 3.3 nF in order to assure the SD activation

time τA ≤ 500 ns. Besides, the filter should be placed as close as possible to the SD pin.

• The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR and low ESL), in parallel with each

Cboot, filters high-frequency disturbance. Both Cboot and C3 (if present) should be placed as close as

possible to the U, V, W and Vboot pins. Bootstrap negative electrodes should be connected to U, V, W

terminals directly and separated from the main output wires.

• To avoid overvoltage on the Vcc pin, a Zener diode (Dz1) can be used. Similarly on the Vboot pin, a Zener

diode (Dz2) can be placed in parallel with each Cboot.

• The use of the decoupling capacitor C4 (100 to 220 nF, with low ESR and low ESL) in parallel with the

electrolytic capacitor Cvdc is useful to prevent surge destruction. Both capacitors C4 and Cvdc should be

placed as close as possible to the IPM (C4 has priority over Cvdc).

• By integrating an application-specific type HVIC inside the module, direct coupling to the MCU terminals

without an opto-couplers is possible.

• Low-inductance shunt resistors have to be used for phase leg current sensing.

• In order to avoid malfunctions, the wiring on N pins, the shunt resistor and PWR_GND should be as short as

possible.

• The connection of SGN_GND to PWR_GND on one point only (close to the shunt resistor terminal) can

reduce the impact of power ground fluctuation.

These guidelines ensure the device specifications for application designs. For further details, please refer to the

relevant application note.

Table 14. Recommended operating conditions

Symbol Parameter Test conditions Min. Typ. Max. Unit

VPN Supply voltage Applied between P-Nu, Nv, Nw 300 400 V

VCC Control supply voltage Applied between VCC-GND 13.5 15 18 V

VBS High-side bias voltage

Applied between VBOOTx-OUT

for x = U, V, W

13 18 V

tdead

Blanking time to prevent

arm-short For each input signal 1 μs

fPWM PWM input signal

-40 °C < TC < 100 °C

-40 °C < TJ < 125 °C 25 kHz

TCCase operation temperature 100 °C

STIPN2M50T-HL

Guidelines

DS11753 - Rev 5 page 17/23

mm Pmmq BASE MHAL/ u L L P‘" 1 ' ' PM 15 A m b = MN :5 PW l7 Em \ L 1 mm m ‘ PW ‘ PM 15 e r\ PIN 25 L \

6Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,

depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product

status are available at: www.st.com. ECOPACK is an ST trademark.

6.1 NDIP-26L in line package information

Figure 12. NDIP-26L in line package outline

8278949_7

STIPN2M50T-HL

Package information

DS11753 - Rev 5 page 18/23

Table 15. NDIP-26L in line mechanical data

Dim.

Min. Typ. Max.

A 4.40

A1 0.80 1.00 1.20

A2 3.00 3.10 3.20

A3 1.70 1.80 1.90

A4 5.70 5.90 6.10

b 0.53 0.72

b1 0.52 0.60 0.68

b2 0.83 1.02

b3 0.82 0.90 0.98

c 0.46 0.59

c1 0.45 0.50 0.55

D 29.05 29.15 29.25

D1 0.55 0.77 1.00

D2 0.35 0.53 0.70

D3 29.55

E 12.35 12.45 12.55

e 1.70 1.80 1.90

e1 2.40 2.50 2.60

eB1 14.25 14.55 14.85

L 0.90 1.05 1.20

STIPN2M50T-HL

NDIP-26L in line package information

DS11753 - Rev 5 page 19/23

6.2 NDIP-26L packing information

Figure 13. NDIP-26L tube (dimensions are in mm)

Notes:

1- Material: extrused/transparent PVC 0.80 ±0.1 mm thickness 10E6~10E11/SQ PVC

2- General tolerance unless otherwise specified: ±0.25 mm

8313150_3

Table 16. Shipping details

Parameter Value

Base quantity 17 pieces

Bulk quantity 476 pieces

STIPN2M50T-HL

NDIP-26L packing information

DS11753 - Rev 5 page 20/23

Contents

1Internal schematic diagram and pin configuration ..................................2

2Electrical ratings ..................................................................5

2.1 Absolute maximum ratings.......................................................5

2.2 Thermal data ..................................................................6

3Electrical characteristics...........................................................7

3.1 Inverter part ...................................................................7

3.2 Control part ...................................................................9

3.2.1 NTC thermistor .........................................................11

3.3 Waveform definitions ..........................................................14

4Shutdown function ...............................................................15

5Application circuit example .......................................................16

5.1 Guidelines ...................................................................17

6Package information..............................................................18

6.1 NDIP-26L in line package information ............................................18

6.2 NDIP-26L packing information...................................................20

Revision history .......................................................................22

STIPN2M50T-HL

Contents

DS11753 - Rev 5 page 21/23

Revision history

Table 17. Document revision history

Date Revision Changes

13-Jul-2016 1 Initial release.

11-Oct-2016 2 Document status promoted from preliminary to production data.

12-Jan-2017 3 Updated Table 8: "Inductive load switching time and energy".

Minor text changes.

01-Feb-2017 4 Modified description on cover page

02-Mar-2020 5

Updated Section Features, Section Applications, Table 2. Inverter part, Table 3. Control part,

Table 4. Total system,Table 6. Static, Table 7. Inductive load switching time and energy, Section

3.2 Control part,Section 4 Shutdown function Section 5.1 Guidelines

STIPN2M50T-HL

DS11753 - Rev 5 page 22/23

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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service

names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

STIPN2M50T-HL

DS11753 - Rev 5 page 23/23

STIPN2M50T-HL 规格书

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