onsemi 的 2N/V7002K 规格书

0N Semicnndnctorg www.0nsemi.com
© Semiconductor Components Industries, LLC, 2007
March, 2019 − Rev. 17
1Publication Order Number:
2N7002K/D
2N7002K, 2V7002K
Small Signal MOSFET
Single N-Channel, 60 V, 380 mA, 1.6 Ohm, SOT-23
Features
•ESD Protected
•Low RDS(on)
•Surface Mount Package
•2V Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•Low Side Load Switch
•Level Shift Circuits
•DC−DC Converter
•Portable Applications i.e. DSC, PDA, Cell Phone, etc.
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS 60 V
Gate−to−Source Voltage VGS ±20 V
Drain Current (Note 1)
Steady State 1 sq in Pad TA = 25°C
TA = 85°C
ID380
270
mA
Drain Current (Note 2)
Steady State Minimum Pad TA = 25°C
TA = 85°C
ID320
230
mA
Power Dissipation
Steady State 1 sq in Pad
Steady State Minimum Pad
PD420
300
mW
Pulsed Drain Current (tp = 10 ms) IDM 5.0 A
Operating Junction and Storage
Temperature Range
TJ, TSTG −55 to
+150
°C
Source Current (Body Diode) IS300 mA
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Gate−Source ESD Rating
(HBM, Method 3015)
ESD 2000 V
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq in pad size with 1 oz Cu.
2. Surface−mounted on FR4 board using 0.08 sq in pad size with 1 oz Cu.
Device Package Shipping†
ORDERING INFORMATION
2N7002KT1G,
2V7002KT1G
3000 / Tape & Reel
SIMPLIFIED SCHEMATIC
SOT−23
CASE 318
STYLE 21
704 MG
G
MARKING DIAGRAM
& PIN ASSIGNMENT
3
21
Drain
Gate
2
1
3
Source
SOT−23
(Pb−Free)
60 V 1.6 W @ 10 V
RDS(on) MAX
380 mA
ID MAXV(BR)DSS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
2.5 W @ 4.5 V
Gate
Source
Drain
3
2
1
(Top View)
704 = Specific Device Code*
M = Date Code*
G= Pb−Free Package
2N7002KT7G 3500 / Tape & ReelSOT−23
(Pb−Free)
*Specific Device Code, Date Code or overbar
orientation and/or location may vary depend-
ing upon manufacturing location. This is a
representation only and actual devices may
not match this drawing exactly.
(Note: Microdot may be in either location)
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2N7002K, 2V7002K
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2
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Junction−to−Ambient − Steady State (Note 3) RqJA 300 °C/W
Junction−to−Ambient − t ≤ 5 s (Note 3) 92
Junction−to−Ambient − Steady State (Note 4) 417
Junction−to−Ambient − t ≤ 5 s (Note 4) 154
3. Surface−mounted on FR4 board using 1 sq in pad size with 1 oz Cu.
4. Surface−mounted on FR4 board using 0.08 sq in pad size with 1 oz Cu.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA60 V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ71 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 60 V
TJ = 25°C 1 mA
TJ = 125°C 10
VGS = 0 V,
VDS = 50 V
TJ = 25°C 100 nA
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±10 mA
VDS = 0 V, VGS = ±10 V 450 nA
VDS = 0 V, VGS = ±5.0 V 150 nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA1.0 2.3 V
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ4.0 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 500 mA 1.19 1.6 W
VGS = 4.5 V, ID = 200 mA 1.33 2.5
Forward Transconductance gFS VDS = 5 V, ID = 200 mA 530 mS
CHARGES AND CAPACITANCES
Input Capacitance CISS
VGS = 0 V, f = 1 MHz,
VDS = 20 V
24.5 45 pF
Output Capacitance COSS 4.2 8.0
Reverse Transfer Capacitance CRSS 2.2 5.0
Total Gate Charge QG(TOT)
VGS = 4.5 V, VDS = 10 V;
ID = 200 mA
0.7 nC
Threshold Gate Charge QG(TH) 0.1
Gate−to−Source Charge QGS 0.3
Gate−to−Drain Charge QGD 0.1
SWITCHING CHARACTERISTICS, VGS = V (Note 6)
Turn−On Delay Time td(ON)
VGS = 10 V, VDD = 25 V,
ID = 500 mA, RG = 25 W
12.2 ns
Rise Time tr9.0
Turn−Off Delay Time td(OFF) 55.8
Fall Time tf29
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 200 mA
TJ = 25°C 0.8 1.2 V
TJ = 85°C 0.7
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%
6. Switching characteristics are independent of operating junction temperatures
S‘C V : 125‘0 \ Jr v55:45v Ves :mv
2N7002K, 2V7002K
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3
TYPICAL CHARACTERISTICS
5.0 V
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
6420
0
0.4
0.8
1.2
1.6
6420
0
0.4
0.8
1.2
Figure 3. On−Resistance vs. Drain Current and
Temperature
Figure 4. On−Resistance vs. Drain Current and
Temperature
ID, DRAIN CURRENT (A)
1.21.00.80.60.40.20
0
0.4
0.8
1.2
1.6
2.0
3.2
Figure 5. On−Resistance vs. Gate−to−Source
Voltage
Figure 6. On−Resistance Variation with
Temperature
VGS, GATE−TO−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C)
108642
0.4
0.8
1.6
2.4
1251007550250−25−50
0.6
1.0
1.4
1.8
2.2
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
VGS = 10 V
7.0 V
8.0 V
9.0 V 4.5 V
4.0 V
6.0 V
3.5 V
3.0 V
2.5 V
TJ = −55°C
TJ = 125°C
TJ = 25°C
TJ = −55°C
TJ = 125°C
TJ = 25°C
TJ = 85°C
VGS = 4.5 V
ID, DRAIN CURRENT (A)
1.21.00.80.60.40.20
0
0.8
1.6
2.4
3.2
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
TJ = −55°C
TJ = 125°C
TJ = 25°C
TJ = 85°C
VGS = 10 V
ID = 500 mA
ID = 200 mA
150
ID = 0.2 A
VGS = 4.5 V
VGS = 10 V
1.2
2.0
2.4
2.8
0.4
1.2
2.0
2.8
2N7002K, 2V7002K
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Qg, TOTAL GATE CHARGE (nC)
0.80.60.40.20
0
1
2
3
4
5
Figure 9. Diode Forward Voltage vs. Current
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
1.21.00.80.60.4
0.01
1
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
IS, SOURCE CURRENT (A)
TJ = 25°C
ID = 0.2 A
201612840
0
10
20
30
C, CAPACITANCE (pF)
Ciss
Coss
Crss
TJ = 25°C
VGS = 0 V
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
TJ = 25°CTJ = 85°C
VGS = 0 V
0.1
Figure 10. Threshold Voltage with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
1.0
1.4
1.8
2.2
VGS(TH), THRESHOLD VOLTAGE (V)
15
0
ID = 250 mA
1.2
1.6
2.0
2.4
1.3
1.7
2.1
2.5
1.1
1.5
1.9
2.3
2N7002K, 2V7002K
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5
TYPICAL CHARACTERISTICS
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 100
0
Figure 11. Thermal Response − 1 sq in pad
t, PULSE TIME (s)
RqJA(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
0.02
0.2
0.01
0.05
Duty Cycle = 0.5
SINGLE PULSE
0.1
1 10 100
1000
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 100
0
Figure 12. Thermal Response − minimum pad
t, PULSE TIME (s)
RqJA(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
0.02
0.2
0.01
0.05
Duty Cycle = 0.5
SINGLE PULSE
0.1
1 10 100
1000
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SOT−23 (TO−236)
CASE 318−08
ISSUE AS
DATE 30 JAN 2018
SCALE 4:1
D
A1
3
12
1
XXXMG
G
XXX = Specific Device Code
M = Date Code
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
SOLDERING FOOTPRINT
VIEW C
L
0.25
L1
e
EE
b
A
SEE VIEW C
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.89 1.00 1.11 0.035
INCHES
A1 0.01 0.06 0.10 0.000
b0.37 0.44 0.50 0.015
c0.08 0.14 0.20 0.003
D2.80 2.90 3.04 0.110
E1.20 1.30 1.40 0.047
e1.78 1.90 2.04 0.070
L0.30 0.43 0.55 0.012
0.039 0.044
0.002 0.004
0.017 0.020
0.006 0.008
0.114 0.120
0.051 0.055
0.075 0.080
0.017 0.022
NOM MAX
L1
H
STYLE 22:
PIN 1. RETURN
2. OUTPUT
3. INPUT
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
STYLE 7:
PIN 1. EMITTER
2. BASE
3. COLLECTOR
STYLE 8:
PIN 1. ANODE
2. NO CONNECTION
3. CATHODE
STYLE 9:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
STYLE 11:
PIN 1. ANODE
2. CATHODE
3. CATHODE−ANODE
STYLE 12:
PIN 1. CATHODE
2. CATHODE
3. ANODE
STYLE 13:
PIN 1. SOURCE
2. DRAIN
3. GATE
STYLE 14:
PIN 1. CATHODE
2. GATE
3. ANODE
STYLE 15:
PIN 1. GATE
2. CATHODE
3. ANODE
STYLE 16:
PIN 1. ANODE
2. CATHODE
3. CATHODE
STYLE 17:
PIN 1. NO CONNECTION
2. ANODE
3. CATHODE
STYLE 18:
PIN 1. NO CONNECTION
2. CATHODE
3. ANODE
STYLE 19:
PIN 1. CATHODE
2. ANODE
3. CATHODE−ANODE
STYLE 23:
PIN 1. ANODE
2. ANODE
3. CATHODE
STYLE 20:
PIN 1. CATHODE
2. ANODE
3. GATE
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
STYLE 1 THRU 5:
CANCELLED
STYLE 24:
PIN 1. GATE
2. DRAIN
3. SOURCE
STYLE 25:
PIN 1. ANODE
2. CATHODE
3. GATE
STYLE 26:
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
STYLE 27:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
2.10 2.40 2.64 0.083 0.094 0.104
HE
0.35 0.54 0.69 0.014 0.021 0.027
c
0−−− 10 0 −−− 10
T°°°°
T
3X
TOP VIEW
SIDE VIEW
END VIEW
2.90
0.80
DIMENSIONS: MILLIMETERS
0.90
PITCH
3X
3X 0.95
RECOMMENDED
STYLE 28:
PIN 1. ANODE
2. ANODE
3. ANODE
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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SOT−23 (TO−236)
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