Texas Instruments 的 LMK61PD0A2 规格书

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LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator
1 Features 3 Description
The LMK61PD0A2 is an ultra-low jitter PLLatinumTM
1• Ultra-low Noise, High Performance pin selectable oscillator that generates commonly
– Jitter: 90 fs RMS typical fOUT > 100 MHz used reference clocks. The device is pre-
– PSRR: -70 dBc, robust supply noise immunity programmed in factory to support seven unique
reference clock frequencies that can be selected by
• Flexible Output Frequency and Format; User pin-strapping each of FS[1:0] to VDD, GND or NC (no
Selectable connect). Output format is selected between
– Frequencies: 62.5 MHz, 100 MHz, 106.25 LVPECL, LVDS, or HCSL by pin-strapping OS to
MHz, 125 MHz, 156.25 MHz, 212.5 MHz, VDD, GND or NC. Internal power conditioning provide
312.5 MHz excellent power supply ripple rejection (PSRR),
reducing the cost and complexity of the power
– Formats: LVPECL, LVDS or HCSL delivery network. The device operates from a single
• Total frequency tolerance of ± 50 ppm 3.3 V ± 5% supply.
• Internal memory stores multiple start-up
configurations, selectable through pin control Device Information(1)
• 3.3V operating voltage PART NUMBER PACKAGE BODY SIZE (NOM)
• Industrial temperature range (-40ºC to +85ºC) LMK61PD0A2 8-pin QFM (SIA) 7.0 mm x 5.0 mm
• 7 mm x 5 mm 8-pin package (1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• High-performance replacement for crystal-, SAW-,
or silicon-based Oscillators
• Switches, Routers, Network Line Cards, Base
Band Units (BBU), Servers, Storage/SAN
• Test and Measurement
• Medical Imaging
• FPGA, Processor Attach
Pinout and Simplified Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.15 Additional Reliability and Qualification.................... 9
1 Features.................................................................. 17.16 Typical Performance Characteristics .................... 10
2 Applications ........................................................... 18 Parameter Measurement Information ................ 11
3 Description ............................................................. 18.1 Device Output Configurations................................. 11
4 Revision History..................................................... 29 Detailed Description............................................ 13
5 Device Control........................................................ 39.1 Overview ................................................................. 13
6 Pin Configuration and Functions......................... 49.2 Functional Block Diagram....................................... 13
7 Specifications......................................................... 59.3 Feature Description................................................. 13
7.1 Absolute Maximum Ratings ...................................... 510 Application and Implementation........................ 14
7.2 ESD Ratings ............................................................ 510.1 Application Information.......................................... 14
7.3 Recommended Operating Conditions....................... 510.2 Typical Application ................................................ 14
7.4 Thermal Information.................................................. 511 Power Supply Recommendations ..................... 16
7.5 Electrical Characteristics - Power Supply................. 612 Layout................................................................... 17
7.6 LVPECL Output Characteristics................................ 612.1 Layout Guidelines ................................................. 17
7.7 LVDS Output Characteristics.................................... 613 Device and Documentation Support ................. 19
7.8 HCSL Output Characteristics.................................... 713.1 Community Resources.......................................... 19
7.9 OE Input Characteristics........................................... 713.2 Trademarks........................................................... 19
7.10 OS, FS[1:0] Input Characteristics ........................... 713.3 Electrostatic Discharge Caution............................ 19
7.11 Frequency Tolerance Characteristics ..................... 713.4 Glossary................................................................ 19
7.12 Power-On/Reset Characteristics (VDD).................. 8
7.13 PSRR Characteristics ............................................. 814 Mechanical, Packaging, and Orderable
Information ........................................................... 19
7.14 PLL Clock Output Jitter Characteristics .................. 9
4 Revision History
Changes from Original (October 2015) to Revision A Page
• Product Preview to Production Data Release ....................................................................................................................... 1
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5 Device Control
Table 1. Output Frequency Mapping for FS[1:0] Selection
FS1 FS0 OUT FREQUENCY (MHz) RELEVANT STANDARDS
0 0 100 PCI Express
0 NC 312.5 10 Gbps Ethernet
0 1 125 1 Gbps Ethernet
NC 0 106.25 Fiber Channel
NC NC 156.25 10 Gbps Ethernet
NC 1 212.5 Fiber Channel
1 0 62.5 1 Gbps Ethernet
1 NC Reserved n/a
1 1 Reserved n/a
Table 2. Output Type Mapping for OS, OE Selection
OS OE OUTPUT TYPE
X 0 Disabled (PLL functional)
0 1 LVPECL
NC 1 LVDS
1 1 HCSL
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OS OUTN
VDDOE
GND OUTP
FS0
FS1
1 6
2 5
43
7
8
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6 Pin Configuration and Functions
SIA Package
8 pin QFM
Table 3. Pin Functions
PIN I/O DESCRIPTION
NAME NO.
POWER
GND 3 Ground Device Ground.
VDD 6 Analog 3.3 V Power Supply.
OUTPUT BLOCK
OUTP, 4, 5 Universal Differential Output Pair (LVPECL, LVDS or HCSL).
OUTN
DIGITAL CONTROL / INTERFACES
FS[1:0] 7, 8 LVCMOS Output Frequency Select. Refer toTable 1.
OE 1 LVCMOS Output Enable (internal pullup). Refer toTable 2.
OS 3 LVCMOS Output Type Select. Refer toTable 2.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Device Supply Voltage -0.3 3.6 V
VIN Output Voltage Range for Logic Inputs -0.3 VDD + 0.3 V
VOUT Output Voltage Range for Clock Outputs -0.3 VDD + 0.3 V
TJJunction Temperature 150 °C
TSTG Storage Temperature -40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1500
C101(2)
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Device Supply Voltage 3.135 3.3 3.465 V
TAAmbient Temperature -40 25 85 °C
TJJunction Temperature 125 °C
tRAMP VDD Power-Up Ramp Time 0.1 100 ms
7.4 Thermal Information
LMK61PD0A2 (2) (3) (4)
QFM (SIA)
THERMAL METRIC(1) UNIT
8 PINS
Airflow (LFM) 0 Airflow (LFM) 200 Airflow (LFM) 400
RθJA Junction-to-ambient thermal resistance 54 44 41.2
RθJC(top) Junction-to-case (top) thermal resistance 34 n/a n/a
RθJB Junction-to-board thermal resistance 36.7 n/a n/a °C/W
ψJT Junction-to-top characterization parameter 11.2 16.9 21.9
ψJB Junction-to-board characterization parameter 36.7 37.8 38.9
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The package thermal resistance is calculated on a 4 layer JEDEC board.
(3) Connected to GND with 3 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations
section for more information on ensuring good system reliability and quality.
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7.5 Electrical Characteristics - Power Supply(1)
VDD = 3.3 V ± 5%, TA= -40C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD Device Current Consumption LVPECL(2) 162 208 mA
LVDS 152 196
HCSL 155 196
IDD-PD Device Current Consumption OE = GND 136
when output is disabled
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation.
7.6 LVPECL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA= -40C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output Frequency(2) 62.5 312.5 MHz
VOD Output Voltage Swing 700 800 1200 mV
(VOH - VOL)(2)
VOUT, DIFF, PP Differential Output Peak-to- 2 x V
Peak Swing |VOD|
VOS Output Common Mode VDD – V
Voltage 1.55
tR/ tFOutput Rise/Fall Time (20% to 120 200 ps
80%)(3)
PN-Floor Output Phase Noise Floor 156.25 MHz -165 dBc/Hz
(fOFFSET > 10 MHz)
ODC Output Duty Cycle(3) 45% 55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(3) Ensured by characterization.
7.7 LVDS Output Characteristics(1)
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output Frequency(1) 62.5 312.5 MHz
VOD Output Voltage Swing 300 390 480 mV
(VOH - VOL)(1)
VOUT, DIFF, PP Differential Output Peak-to- 2 x V
Peak Swing |VOD|
VOS Output Common Mode 1.2 V
Voltage
tR/ tFOutput Rise/Fall Time (20% to 150 250 ps
80%)(2)
PN-Floor Output Phase Noise Floor 156.25 MHz -162 dBc/Hz
(fOFFSET > 10 MHz)
ODC Output Duty Cycle(2) 45% 55%
ROUT Differential Output Impedance 125 Ohm
(1) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(2) Ensured by characterization.
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7.8 HCSL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output Frequency 62.5 312.5 MHz
VOH Output High Voltage 600 850 mV
VOL Output Low Voltage -100 100 mV
VCROSS Absolute Crossing 250 475 mV
Voltage(2)(3)
VCROSS-DELTA Variation of VCROSS(2)(3) 0 140 mV
dV/dt Slew Rate(4) 0.8 2 V/ns
PN-Floor Output Phase Noise Floor 100 MHz -164 dBc/Hz
(fOFFSET > 10 MHz)
ODC Output Duty Cycle(4) 45% 55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential
zero crossing.
(3) Ensured by design.
(4) Ensured by characterization.
7.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Voltage 1.4 V
VIL Input Low Voltage 0.6 V
IIH Input High Current VIH = VDD -40 40 uA
IIL Input Low Current VIL = GND -40 40 uA
CIN Input Capacitance 2 pF
7.10 OS, FS[1:0] Input Characteristics
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Voltage 1.4 V
VIL Input Low Voltage 0.4 V
IIH Input High Current VIH = VDD -40 40 uA
IIL Input Low Current VIL = GND -40 40 uA
CIN Input Capacitance 2 pF
7.11 Frequency Tolerance Characteristics(1)
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fTTotal Frequency Tolerance All output formats, frequency bands and -50 50 ppm
device junction temperature up to 125°C;
includes initial freq tolerance, temperature &
supply voltage variation, solder reflow and
aging (10 years)
(1) Ensured by characterization.
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7.12 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTHRESH Threshold Voltage(1) 2.72 2.95 V
VDROOP Allowable Voltage Droop(2) 0.1 V
tSTARTUP Startup Time (1) Time elapsed from VDD at 3.135 V to output 10 ms
enabled
tOE-EN Output enable time(2) Time elapsed from OE at VIH to output enabled 50 us
tOE-DIS Output disable time(2) Time elapsed from OE at VIL to output disabled 50 us
(1) Ensured by characterization.
(2) Ensured by design.
7.13 PSRR Characteristics(1)
VDD = 3.3 V, TA= 25°C, FS[1:0] = NC, NC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PSRR Spurs Induced by 50 mV Sine wave at 50 kHz -70 dBc
Power Supply Ripple(2)(3) at Sine wave at 100 kHz -70
156.25 MHz output, all Sine wave at 500 kHz -70
output types
Sine wave at 1 MHz -70
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
(3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
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7.14 PLL Clock Output Jitter Characteristics(1)(2)
VDD = 3.3 V ± 5%, TA= -40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RJ RMS Phase Jitter(3) fOUT ≥100 MHz, All output frequencies and 100 200 fs RMS
(12 kHz – 20 MHz) output types
(1 kHz – 5 MHz)
RJ RMS Phase Jitter(3) fOUT = 62.5 MHz, All output frequencies and 200 400 fs RMS
(12 kHz – 20 MHz) output types
(1 kHz – 5 MHz)
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
(3) Ensured by characterization.
7.15 Additional Reliability and Qualification
PARAMETER CONDITION / TEST METHOD
Mechanical Shock MIL-STD-202, Method 213
Mechanical Vibration MIL-STD-202, Method 204
Moisture Sensitivity Level J-STD-020, MSL3
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Output Frequency (MHz)
Output Differential Swing (Vp-p)
0 50 100 150 200 250 300 350
0.7
0.75
0.8
0.85
0.9
0.95
D017
Output Frequency (MHz)
Output Differential Swing (Vp-p)
0 50 100 150 200 250 300 350
1.42
1.43
1.44
1.45
1.46
1.47
1.48
D018
Output Frequency (MHz)
Output Differential Swing (Vp-p)
0 50 100 150 200 250 300 350
1.5
1.55
1.6
1.65
1.7
1.75
1.8
D016
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7.16 Typical Performance Characteristics
Figure 1. Phase Noise of LVPECL Differential Output at Figure 2. Phase Noise of LVDS Differential Output at 156.25
156.25 MHz with FS[1:0] = NC, NC, OS = GND MHz with FS[1:0] = NC, NC, OS = NC
Figure 4. LVPECL Differential Output Swing vs Frequency
Figure 3. Phase Noise of HCSL Differential Output at 156.25
MHz with FS[1:0] = NC, NC, OS = VDD
Figure 5. LVDS Differential Output Swing vs Frequency Figure 6. HCSL Differential Output Swing vs Frequency
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LMK61PD0A2 LVPECL
150 150
Balun/
Buffer
Phase Noise/
Spectrum
Analyzer
LMK61PD0A2 HCSL
50
50
Oscilloscope
High impedance differential probe
LMK61PD0A2 LVDS Oscilloscope
High impedance differential probe
LMK61PD0A2 LVPECL
150 150
Oscilloscope
High impedance differential probe
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8 Parameter Measurement Information
8.1 Device Output Configurations
Figure 7. LVPECL Output DC Configuration during Device Test
Figure 8. LVDS Output DC Configuration during Device Test
Figure 9. HCSL Output DC Configuration during Device Test
Figure 10. LVPECL Output AC Configuration during Device Test
Figure 11. LVDS Output AC Configuration during Device Test
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VOD
OUT_P
OUT_N
VOUT,DIFF,PP = 2 x VOD
0 V
20%
80%
tRtF
Sine wave
Modulator
Power Supply
Balun Phase Noise/
Spectrum
Analyzer
LMK61PD0A2
150 (LVPECL)
Open (LVDS)
50 (HCSL)
150 (LVPECL)
Open (LVDS)
50 (HCSL)
LMK61PD0A2 HCSL
50 50
Balun/
Buffer
Phase Noise/
Spectrum
Analyzer
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Device Output Configurations (continued)
Figure 12. HCSL Output AC Configuration during Device Test
Figure 13. PSRR Test Setup
Figure 14. Differential Output Voltage and Rise/Fall Time
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Output
Control
Power Conditioning
VDD
3
3FS0
LVPECL
or LVDS
or HCSL
FS1
3 = tri-state
PLL
¥
ROM
(Pin Control)
3OS
Integrated
Oscillator
XO
N Div
™ûfractional
Integer Div
GND
OE
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9 Detailed Description
9.1 Overview
The LMK61PD0A2 is a pin selectable oscillator that generates commonly used reference clocks, greater than
100 MHz, with less than 200 fs, rms max random jitter.
9.2 Functional Block Diagram
NOTE
Control blocks are compatible with 1.8/2.5/3.3 V I/O voltage levels.
9.3 Feature Description
9.3.1 Device Block-Level Description
The LMK61PD0A2 comprises of an integrated oscillator that includes a 50 MHz crystal, a fractional PLL with
integrated VCO. Completing the device is the combination of an integer output divider and a universal differential
output buffer. The on-chip ROM contains seven pre-programmed output frequency plans that selects the
appropriate settings for the integrated oscillator, PLL blocks and output divider. Table 1 lists the supported output
frequency plans that can be selected by pin-strapping FS[1:0] as required. Table 2 lists the supported output
types that can be selected by pin-strapping OS and OE as required. The device is powered by on-chip low
dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive
analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs
provide isolation from any noise in the external power supply rail with a PSRR of better than -70 dBc at 50 kHz to
1 MHz ripple frequencies at 3.3 V device supply.
9.3.2 Device Configuration Control
The LMK61PD0A2 selects an output frequency plan and output type using control pins FS[1:0].
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The LMK61PD0A2 is an ultra-low jitter pin selectable oscillator that can be used to provide reference clocks for
high-speed serial links resulting in improved system performance.
10.2 Typical Application
10.2.1 Jitter Considerations in Serdes Systems
Jitter-sensitive applications such as 10 Gbps or 100 Gbps Ethernet, deploy a serial link utilizing a Serializer in the
transmit section (TX) and a De-serializer in the receive section (RX). These SERDES blocks are typically
embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of
the TX PLL bandwidth and the RX CDR bandwidth.
As can be seen in Figure 15, the pass band region between the TX low pass cutoff and RX high pass cutoff
frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of
the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec
or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR
bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC
or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification
that needs to be met, as related to the RX CDR bandwidth.
The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example,
IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10 Gbps Ethernet should be no more than
0.28 * UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter.
The jitter contributing elements are made up of the reference clock, generated potentially from a device like
LMK61PD0A2, the transmit medium, transmit driver etc. Only a portion of the overall allowable transmit jitter is
allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter, for a 20%
clock jitter budget, is 5.43 ps, p-p.
Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or
mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other
uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout
buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern
fanout buffers have low additive random jitter (less than 100 fs, rms) with no substantial contribution to the
deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the
primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is
to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This
amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For
serial link systems that need to meet a bit error rate (BER) of 10-12, the allowable random jitter in root-mean-
square is 0.29 ps, rms. This is calculated by dividing the p-p jitter by 14 for a BER of 10-12. Accounting for
random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps, rms. This is
calculated by the root-mean-square subtraction from the desired jitter at the fanout buffer's output assuming 100
fs, rms of additive jitter from the fanout buffer.
With careful frequency planning techniques, like spur optimization (covered in the Spur Mitigation Techniques
section) and on-chip LDOs to suppress supply noise, the LMK61PD0A2 is able to generate clock outputs with
deterministic jitter that is below 1 ps, p-p and random jitter that is below 0.2 ps, rms. This gives the serial link
system with additional margin on the allowable transmit jitter resulting in a BER better than 10-12.
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l TEXAS INSTRUMENTS quev Tn (an dam} L s a Incre hand Less % budget
RX
Deserializer
TX
Serializer
TX PLL
Ref Clk
Parallel
Data
Jitter Transfer (on clock)
F1 = TX_PLL_BWmax
HTXPLL(f)
Sampler
CDR
Parallel
Data
Recovered
Clock
Serialized clock/data
Jitter Tolerance (on data)
F2 = RX_CDR_BWmin
HRXCDR(f)
Jitter Transfer (on clock)
F2 = RX_CDR_BWmin
HRXCDR(f)
Jitter Tolerance (on data)
H(f)
F2
SoC trend:
Increase stop band
Less % of jitter budget
Jitter Transfer (on clock)
F1
H(f)
F2
SoC trend:
Decrease stop band
Improved LO design
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Typical Application (continued)
Figure 15. Dependence of Clock Jitter in Serial Links
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11 Power Supply Recommendations
For best electrical performance of LMK61PD0A2, it is preferred to utilize a combination of 10 uF, 1 uF and 0.1 uF
on its power supply bypass network. It is also recommended to utilize component side mounting of the power
supply bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep
the connections between the bypass capacitors and the power supply on the device as short as possible. Ground
the other side of the capacitor using a low impedance connection to the ground plane. Figure 16 shows the
layout recommendation for power supply decoupling of LMK61PD0A2.
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SNAS675A –OCTOBER 2015–REVISED NOVEMBER 2015
12 Layout
12.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply
bypassing when using LMK61PD0A2 to ensure good thermal / electrical performance and overall signal integrity
of entire system.
12.1.1 Ensuring Thermal Reliability
The LMK61PD0A2 is a high performance device. Therefore careful attention must be paid to device configuration
and printed circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected
to the ground plane of the PCB through three vias or more, as shown in Figure 16, to maximize thermal
dissipation out of the package.
Equation 1 describes the relationship between the PCB temperature around the LMK61PD0A2 and its junction
temperature.
TB= TJ–ΨJB * P
where
• TB: PCB temperature around the LMK61PD0A2
• TJ: Junction temperature of LMK61PD0A2
•ΨJB: Junction-to-board thermal resistance parameter of LMK61PD0A2 (36.7°C/W without airflow)
• P: On-chip power dissipation of LMK61PD0A2 (1)
In order to ensure that the maximum junction temperature of LMK61PD0A2 is below 125°C, it can be calculated
that the maximum PCB temperature without airflow should be at 100°C or below when the device is optimized for
best performance resulting in maximum on-chip power dissipation of 0.68 W.
12.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK61PD0A2, it is recommended to
route vias into decoupling capacitors and then into the LMK61PD0A2. It is also recommended to increase the via
count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for
high frequency current flow. Figure 16 shows the layout recommendation for LMK61PD0A2.
Figure 16. LMK61PD0A2 Layout Recommendation for Power Supply and Ground
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Layout Guidelines (continued)
12.1.3 Recommended Solder Reflow Profile
It is recommended to follow the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferrable for the LMK61PD0A2
to be processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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I TEXAS INSTRUMENTS Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMK61PD0A2-SIAR ACTIVE QFM SIA 8 2500 RoHS & Green NIAU Level-3-260C-168 HR -40 to 85 LMK61
PD0A2
LMK61PD0A2-SIAT ACTIVE QFM SIA 8 250 RoHS & Green NIAU Level-3-260C-168 HR -40 to 85 LMK61
PD0A2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMK61PD0A2-SIAR QFM SIA 8 2500 330.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1
LMK61PD0A2-SIAT QFM SIA 8 250 178.0 16.4 5.5 7.5 1.5 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Apr-2022
Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMK61PD0A2-SIAR QFM SIA 8 2500 356.0 356.0 35.0
LMK61PD0A2-SIAT QFM SIA 8 250 208.0 191.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Apr-2022
Pack Materials-Page 2
SIAOOOBB 3(3) A63 ‘@ SVT I-I
www.ti.com
PACKAGE OUTLINE
C
2X
5.08
4X
2.54
6X (0.15)
6X 1.03
0.97
2X 0.83
0.77
1.15 MAX
6X 1.43
1.37
2X
2.865
6X 1.85
A 5±0.1 B
7±0.1
4X (0.26)
2X (0.24)
QFM - 1.15 mm max heightSIA0008B
QUAD FLAT MODULE
4221443/B 09/2015
PIN 1 INDEX
AREA
0.15 C
4X
0.1 C
0.1 C
0.1 C A B
0.05 C
1
34
7
8
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
6
SCALE 1.900
(D SIAOOOBB
www.ti.com
EXAMPLE BOARD LAYOUT
6X (1)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
6X (1.4)
(3.7)
4X (2.54)
(2.865)
2X ( 0.8)
(R ) TYP0.05
QFM - 1.15 mm max heightSIA0008B
QUAD FLAT MODULE
4221443/B 09/2015
SYMM
SYMM
1
34
7
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:8X
8
6
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SIAOOOBB
www.ti.com
EXAMPLE STENCIL DESIGN
12X (0.6)
2X ( 0.8)
12X (1)
4X (2.54)
(3.7)
2X
(2.865)
(R ) TYP0.05
(0.4) TYP
QFM - 1.15 mm max heightSIA0008B
QUAD FLAT MODULE
4221443/B 09/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
PADS 1-3 & 4-6: 86%
SCALE:10X
1
34
7
8
6
EXPOSED METAL
TYP
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