onsemi 的 6N137M, HCPL2601M/11M, HCPL2630M/31M 规格书

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© Semiconductor Components Industries, LLC, 2009
June, 2021 − Rev. 2
1Publication Order Number:
HCPL2631M/D
8-Pin DIP High-Speed
10 MBit/s Logic Gate
Optocouplers
Single-Channel: 6N137M,
HCPL2601M, HCPL2611M
Dual-Channel: HCPL2630M,
HCPL2631M
Description
The 6N137M, HCPL2601M, HCPL2611M single−channel and
HCPL2630M, HCPL2631M dual−channel optocouplers consist of a
850 nm AlGaAs LED, optically coupled to a very high speed
integrated photo−detector logic gate with a strobable output. This
output features an open collector, thereby permitting wired OR
outputs. The switching parameters are guaranteed over the
temperature range of −40°C to +85°C. A maximum input signal of
5 mA will provide a minimum output sink current of 13 mA (fan out
of 8).
An internal noise shield provides superior common mode rejection
of typically 10 kV/ms. The HCPL2601M and HCPL2631M has a
minimum CMR of 5 kV/ms. The HCPL2611M has a minimum CMR
of 10 kV/ms.
Features
•Very High Speed – 10 MBit/s
•Superior CMR – 10 kV/ms
•Fan−out of 8 Over −40°C to +85°C
•Logic Gate Output
•Strobable Output
•Wired OR−open Collector
•Safety and Regulatory Approvals
♦UL1577, 5,000 VACRMS for 1 Minute
♦DIN EN/IEC60747−5−5
•These are Pb−Free Devices
Applications
•Ground Loop Elimination
•LSTTL to TTL, LSTTL or 5 V CMOS
•Line Receiver, Data Transmission
•Data Multiplexing
•Switching Power Supplies
•Pulse Transformer Replacement
•Computer−peripheral Interface
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MARKING DIAGRAM
ON
6N137
VXXYYB
6N137 = Device Number
V = DIN EN/IEC60747−5−5 Option (only
appears on component ordered with
this option)
XX = Two−Digit Year Code, e.g., ‘16’
YY = Two−Digit Work Week, Ranging from
‘01’ to ‘53’
B = Assembly Package Code
See detailed ordering and shipping information on page 14 of
this data sheet.
ORDERING INFORMATION
PDIP8 6.6x3.81, 2.54P
CASE 646BW
PDIP8 9.655x6.6, 2.54P
CASE 646CQ
PDIP8 GW
CASE 709AC
PDIP8 GW
CASE 709AD
8
8
1
8
1
1
8
1
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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2
SCHEMATICS
Figure 1. Schematics
A 0.1 mF bypass capacitor must be connected between pins 8 and 5 (Note 1).
6N137M, HCPL2601M,
HCPL2611M
HCPL2630M,
HCPL2631M
1
2
3
4 5
6
7
8
N/C
_
VCC
VE
VO
GND
+
N/C
VF
1
2
3
4 5
6
7
8
+
_
VF1
VCC
V01
V02
GND
VF2
_
+
TRUTH TABLE (Positive Logic)
Input Enable Output
H H L
L H H
H L H
L L H
H NC L
L NC H
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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3
SAFETY AND INSULATION RATINGS (As per DIN EN/IEC 60747−5−5, this optocoupler is suitable for “safe electrical insulation”
only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.)
Parameter Characteristics
Installation Classifications per DIN VDE 0110/1.89 Table 1, For Rated Mains Voltage <150 VRMS I–IV
<300 VRMS I–IV
<450 VRMS I–III
<600 VRMS I–III
Climatic Classification 40/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Comparative Tracking Index 175
Symbol Parameter Value Unit
VPR Input−to−Output Test Voltage, Method A, VIORM x 1.6 = VPR,
Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC
1,335 Vpeak
Input−to−Output Test Voltage, Method B, VIORM x 1.875 = VPR,
100% Production Test with tm = 1 s, Partial Discharge < 5 pC
1,669 Vpeak
VIORM Maximum Working Insulation Voltage 890 Vpeak
VIOTM Highest Allowable Over−Voltage 6,000 Vpeak
External Creepage ≥8.0 mm
External Clearance ≥7.4 mm
External Clearance (for Option TV, 0.4” Lead Spacing) ≥10.16 mm
DTI Distance Through Insulation (Insulation Thickness) ≥0.5 mm
TSCase Temperature (Note 2) 150 °C
IS,INPUT Input Current (Note 2) 200 mA
PS,OUTPUT Output Power (Duty Factor ≤ 2.7%) (Note 2) 300 mW
RIO Insulation Resistance at TS, VIO = 500 V (Note 2) >109W
1. The VCC supply to each optoisolator must be bypassed by a 0.1 mF capacitor or larger. This can be either a ceramic or solid tantalum capacitor
with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device.
2. Safety limit value − maximum values allowed in the event of a failure.
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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4
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol Parameter Device Value Unit
TSTG Storage Temperature −40 to +125 °C
TOPR Operating Temperature −40 to +100 °C
TJJunction Temperature −40 to +125 °C
TSOL Lead Solder Temperature 260 for 10 s °C
EMITTER
IF (avg) DC/Average Forward Input Current Per Channel Single Channel 50 mA
Dual Channel 30
VEEnable Input Voltage Not to Exceed VCC by More than 500 mV Single Channel 5.5 V
VRReverse Input Voltage Per Channel All 5.0 V
PIInput Power Dissipation Per Channel Single Channel 100 mW
Dual Channel 45
DETECTOR
VCC Supply Voltage All −0.5 to 7.0 V
IO (avg) Average Output Current Per Channel All 25 mA
IO (pk) Peak Output Current Per Channel All 50 mA
VOOutput Voltage Per Channel All −0.5 to 7.0 V
POOutput Power Dissipation Per Channel Single Channel 85 mW
Dual Channel 60
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Supply Voltage 4.5 5.5 V
IFL Input Current, Low Level 0 250 mA
IFH Input Current, High Level 6.3 (Note 3) 20.0 mA
VEL Enable Voltage, Low Level 0 0.8 V
VEH Enable Voltage, High Level 2.0 VCC V
TAAmbient Operating Temperature −40 +85 °C
NFan Out (TTL Load) −8
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. 6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is 5.0 mA or less.
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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5
ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions Device Min Typ Max Unit
INDIVIDUAL COMPONENT CHARACTERISTICS (VCC = 5.5 V, TA = 0°C to 70°C unless otherwise specified)
EMITTER
VFInput Forward Voltage IF = 10 mA, TA = 25°CAll −1.45 1.70 V
IF = 10 mA − − 1.80
BVR Input Reverse Breakdown
Voltage
IR = 10 mAAll 5.0 − − V
CIN Input Capacitance VF = 0, f = 1 MHz All −60 −pF
DVF / DTATemperature Coefficient of
Forward Voltage
IF = 10 mA All − −1.4 −mV/°C
DETECTOR
ICCL Logic Low Supply Current IF = 10 mA, VO = Open, VE = 0.5 V Single Channel −8 13 mA
IF1 = IF2 = 10 mA, VO = Open Dual Channel −14 21
ICCH Logic High Supply Current IF = 0 mA, VO = Open, VE = 0.5 V Single Channel −6 10 mA
IF = 0 mA, VO = Open Dual Channel −10 15
IEL Low Level Enable Current VE = 0.5 V Single Channel − −0.7 −1.6 mA
IEH High Level Enable Current VE = 2.0 V Single Channel − −0.5 −1.6 mA
VEL Low Level Enable Voltage IF = 10 mA (Note 4) Single Channel − − 0.8 V
VEH High Level Enable Voltage IF = 10 mA Single Channel 2.0 − − V
TRANSFER CHARACTERISTICS (VCC = 5.5 V, TA = −40°C to +85°C unless otherwise specified)
IFT Input Threshold Current VO = 0.6 V, VE = 2.0 V, IOL = 13 mA All −3 5 mA
IOH HIGH Level Output Current VO = 5.5 V, IF = 250 mA, VE = 2.0 V All − − 100 mA
VOL LOW Level Output Voltage IF = 5 mA, VE = 2.0 V, IOL = 13 mA All −0.4 0.6 V
SWITCHING CHARACTERISTICS (VCC = 5 V, IF = 7.5 mA, TA = −40°C to +85°C unless otherwise specified)
tPHL Propagation Delay Time to
Logic LOW
RL = 350 W, CL = 15 pF, TA = 25°C
(Note 5) (Figure 23)
All 25 40 75 ns
RL = 350 W, CL = 15 pF (Note 5)
(Figure 23)
− − 100
tPLH Propagation Delay Time to
Logic HIGH
RL = 350 W, CL = 15 pF, TA = 25°C
(Note 6) (Figure 23)
All 20 40 75 ns
RL = 350 W, CL = 15 pF (Note 6)
(Figure 23)
− − 100
|tPHL–tPLH|Pulse Width Distortion RL = 350 W, CL = 15 pF (Figure 23) All −1 35 ns
tROutput Rise Time
(10% to 90%)
RL = 350 W, CL = 15 pF (Note 7)
(Figure 23)
All −30 −ns
tFOutput Fall Time
(90% to 10%)
RL = 350 W, CL = 15 pF(Note 8)
(Figure 23)
All −10 −ns
tEHL Enable Propagation Delay
Time to Output LOW Level
VEH = 3.5 V, RL = 350 W, CL = 15 pF
(Note 9) (Figure 24)
Single Channel −15 −ns
tELH Enable Propagation Delay
Time to Output HIGH Level
VEH = 3.5 V, RL = 350 W, CL = 15 pF
(Note 10) (Figure 24)
Single Channel −15 −ns
|CMH|Common Mode Transient
Immunity at Logic High
IF = 0 mA, VCM = 50 VPEAK,
RL = 350 W, TA = 25°C (Note 11)
(Figure 25)
6N137M,
HCPL2630M
−10,000 −V/ms
HCPL2601M,
HCPL2631M
5000 10,000 −
IF = 0 mA, VCM = 400 VPEAK,
RL = 350 W, TA = 25°C (Note 11)
(Figure 25) HCPL2611M
10,000 15,000 −
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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ELECTRICAL CHARACTERISTICS (continued)
Symbol UnitMaxTypMinDeviceTest ConditionsParameter
SWITCHING CHARACTERISTICS (VCC = 5 V, IF = 7.5 mA, TA = −40°C to +85°C unless otherwise specified)
|CML|Common Mode Transient
Immunity at Logic Low
VCM = 50 VPEAK, RL = 350 W,
TA = 25°C (Note 11) (Figure 25)
6N137M,
HCPL2630M
−10,000 −V/ms
HCPL2601M,
HCPL2631M
5000 10,000 −
VCM = 400 VPEAK, RL = 350 W,
TA = 25°C (Note 11) (Figure 25)
HCPL2611M 10,000 15,000 −
ISOLATION CHARACTERISTICS (TA = 25°C, unless otherwise noted)
VISO Withstand Insulation Test
Voltage
Relative Humidity ≤ 50%,
II−O ≤ 10 mA, t = 1 min, f = 50 Hz
(Note 12) (Note 13)
All 5,000 − − VACRMS
RI−OResistance (Input to Output) VI−O = 500 VDC (Note 12) All −1011 −W
CI−OCapacitance (Input to
Output)
f = 1 MHz, VI−O = 0 VDC (Note 12) All −1−pF
II−OInput−Output Insulation
Leakage Current
Relative Humidity ≤ 45%,
VI−I = 3000 VDC, t = 5 s (Note 12)
All − − 1.0 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
5. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on
the HIGH to LOW transition of the output voltage pulse.
6. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on
the LOW to HIGH transition of the output voltage pulse.
7. tR – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
8. tF – Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
9. tEHL – Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to the 1.5 V
level on the HIGH to LOW transition of the output voltage pulse.
10.tELH – Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to the 1.5 V
level on the LOW to HIGH transition of the output voltage pulse.
11. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode
pulse signal, VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0 V). Common mode transient immunity in logic low
level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will
remain in a logic low state (i.e., VO < 0.8 V).
12.Device is considered a two terminal device: pins 1, 2, 3 and 4 are shorted together and pins 5, 6, 7 and 8 are shorted together.
13.5000 VACRMS for 1 minute duration is equivalent to 6000 VACRMS for 1 second duration
Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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7
TYPICAL PERFORMANCE CURVES
(For Single−Channel Devices: 6N137M, HCPL2601M, and HCPL2611M)
0
0.9
−40 −20 0 20 40 60
−40 −20 0 20 40 60 80 100
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0 1.0 1.1 1.2 1.3 1.51.4
0.001
0.010
0.100
10
579111315
20
0
40
4.0
3.5
3.0
2.5
2.0
1.5
1.0
60
80
100
120
−40 −200 20406080100
20
25
30
35
40
45
50
21
0
1
2
3
4
5
6
1.6
80 100
3546
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
IF
, FORWARD CURRENT (mA)
IF
, FORWARD CURRENT (mA)
VF
, FORWARD VOLTAGE (V)
1
VOL, LOW LEVEL OUTPUT VOLTAGE (V)
IOL, LOW LEVEL OUTPUT CURRENT (mA) IF
, FORWARD CURRENT (mA)
TP
, PROPAGATION DELAY (ns)
VO, OUTPUT VOLTAGE (V)
IFT
, INPUT THRESHOLD CURRENT (mA)
IF = 5 mA
VE = 2 V
VCC = 5.5 V
IOL = 12.8 mA
IOL = 16 mA
IOL = 6.4 mA
IOL = 9.6 mA
VCC = 5 V
TA = 25°C
RL = 4 kW (tPHL)
RL = 1 kW (tPHL)
RL = 350 W (tPHL)
RL = 350 W (tPLH)
RL = 1 kW (tPLH)
RL = 4 kW (tPLH)
VCC = 5 V
VE = 2 V
VOL = 0.6 V
IF = 15 mA
IF = 10 mA
IF = 5 mA
VCC = 5 V
VE = 2 V
VOL = 0.6 V
RL = 350 W
RL = 1 kW
RL = 4 kW
RL = 350 W
RL = 1 kW
RL = 4 kW
Figure 2. Low Level Output Voltage vs.
Ambient Temperature
Figure 3. Input Diode Forward Voltage vs.
Forward Current
Figure 4. Switching Time vs. Forward Current Figure 5. Low Level Output vs.
Ambient Temperature
Figure 6. Input Threshold Current vs.
Ambient Temperature
Figure 7. Output Voltage vs. Input Forward Current
Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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8
TYPICAL PERFORMANCE CURVES (Continued)
(For Single−Channel Devices: 6N137M, HCPL2601M, HCPL2611M)
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
PWD, PULSE WIDTH DISTORTION (ns)
TP
, PROPAGATION DELAY (ns) tR / tF
, RISE AND FALL TIME (ns)
TE, ENABLE PROPAGATION DELAY (ns)
IOH, HIGH LEVEL OUTPUT CURRENT (mA)
Figure 8. Pulse Width Distortion vs. Temperature Figure 9. Rise and Fall Time vs. Temperature
Figure 10. Enable Propagation Delay vs. Temperature Figure 11. Switching Time vs. Temperature
Figure 12. High Level Output Current vs. Temperature
60
50
40
30
20
10
0
−10
−40 −200 20406080100
500
400
300
200
100
0
−100−40 −200 20406080100
100
80
60
40
20
0
−40 −200 20406080100
100
90
80
70
60
50
40
30
20−40 −200 20406080100
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0−40 −200 20406080100
IF = 7.5 mA
VCC = 5 V
RL = 350 W (tR)
RL = 1 kW (tR)
RL = 4 kW (tR)
IF = 7.5 mA
VCC = 5 V
IF = 7.5 mA
VCC = 5 V
IF = 7.5 mA
VCC = 5 V
RL = 4 kW (tPHL)
RL = 1 kW (tPHL)
RL = 350 W (tPHL)
RL = 350 W (tPLH)
RL = 1 kW (tPLH)
RL = 4 kW (tPLH)
RL = 1 kW (tELH)
RL = 4 kW (tELH)
RL = 4 kW / 1 kW / 360 W (tEHL)
RL = 350 W (tELH)
VCC = 5 V
VO = 5.5 V
VE = 2 V
IF = 250 mA
RL = 4 kW (tF)
RL = 1 kW (tF)
RL = 350 W (tF)
RL = 350 W
RL = 1 kW
RL = 4 kW
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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9
TYPICAL PERFORMANCE CURVES (Continued)
(For Dual−Channel Devices: HCPL2630M and HCPL2631M)
−40 −20 0 20 40 60 80 100 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
579111315
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
3
4
0
20
40
60
80
100
120
20
25
30
35
40
45
50
0
1
2
3
4
5
6
100
10
1
0.1
0.01
0.001
−40 −200 20406080100
−40 −20 0 20 40 60 80 100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
IF
, FORWARD CURRENT (mA)
IF
, FORWARD CURRENT (mA)
VF
, FORWARD VOLTAGE (V)
VOL, LOW LEVEL OUTPUT VOLTAGE (V)
IOL, LOW LEVEL OUTPUT CURRENT (mA) IF
, FORWARD CURRENT (mA)
TP
, PROPAGATION DELAY (ns)
VO, OUTPUT VOLTAGE (V)
IFT
, INPUT THRESHOLD CURRENT (mA)
IOL = 12.8 mA IOL = 16 mA
IOL = 6.4 mA
IOL = 9.6 mA
VCC = 5 V
TA = 25°C
RL = 1 kW
RL = 4 kW (TPHL)
RL = 350 W
RL = 350 W (TPLH)
RL = 1 kW (TPLH)
RL = 4 kW (TPLH)
VCC = 5 V
VOL = 0.6 V
IF = 15 mA
IF = 10 mA
IF = 5 mA
VCC = 5 V
VOL = 0.6 V
RL = 350 W
RL = 1 kW
RL = 4 kW
RL = 350 W
RL = 1 kW
RL = 4 kW
Figure 13. Low Level Output Voltage vs.
Ambient Temperature
Figure 14. Input Diode Forward Voltage vs.
Forward Current
Figure 15. Switching Time vs. Forward Current Figure 16. Low Level Output Current vs.
Ambient Temperature
Figure 17. Input Threshold Current vs.
Ambient Temperature
Figure 18. Output Voltage vs. Input Forward Current
IF = 5 mA
VCC = 5.5 V
0213546
// : 3509(1me L y
Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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10
TYPICAL PERFORMANCE CURVES (Continued)
(For Dual−Channel Devices: HCPL2630M and HCPL2631M)
100
−60 −40 −200 20406080100
−60 −40 −20 0 20 40 8060
−60 −40 −20 0 20 40 8060
−60 −40 −200 20406080100
80
60
40
20
0
600
500
400
300
200
0
20
40
60
80
100
120 1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
100
TA, TEMPERATURE (°C)
IOH, HIGH LEVEL OUTPUT CURRENT (mA)
VCC = 5.5 V
VO = 5.5 V
IF = 250 mA
TA, TEMPERATURE (°C)
TP
, PROPAGATION DELAY (ns)
IF = 7.5 mA
VCC = 5 V
RL = 350 W (TPLH)
RL = 1 kW (TPLH)
RL = 4 kW (TPLH)
TA, TEMPERATURE (°C) TA, TEMPERATURE (°C)
Tr / Tf, RISE AND FALL TIME (ns)
Figure 19. Pulse Width Distortion vs. Temperature Figure 20. Rise and Fall Time vs. Temperature
IF = 7.5 mA
VCC = 5 V
RL = 350 W (tr)
RL = 1 kW (tr)
RL = 4 kW (tr)
IF = 7.5 mA
VCC = 5 V
Figure 21. Switching Time vs. Temperature Figure 22. High Level Output Current vs. Temperature
RL = 350 W
RL = 1 kW
RL = 4 kW
RL = 1 kW
RL = 4 kW (tf)
RL = 350 W
PWD, PULSE WIDTH DISTORTION (ns)
RL = 1 kW
RL = 4 kW (TPHL)
RL = 350 W
Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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11
TEST CIRCUITS
Pulse
Generator
tr = 5 ns
ZO = 50 W
47
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
45
1
2
3
8
7
6
+5 V
PLH
t
I = 3.75 mA
F
f
tr
t
L
R
CL
(I )
Input
F
Monitor
.1 mF
bypass
GND
VCC
7.5 mA
+5 V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
Input
Monitor
(VE)
GND
VCC
O
(V )
Output
L
R
L
C
(V )
Output
O
EHL
tELH
5
6
O
(V )
Output
t
(V )
Input
E
(I )
Input
F
(V )
Output
O
(V )
Output
O
.1 mF
bypass
Figure 23. Test Circuit and Waveforms for tPLH, tPHL, tr and tf
Figure 24. Test Circuit tEHL and tELH
Pulse
Generator
tr = 5 ns
ZO = 50 W
Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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TEST CIRCUITS (Continued)
Figure 25. Test Circuit Common Mode Transient Immunity
+5 V
Peak
3
2
1
4
8
GND
VCC
O
(V )
Output
350 W
V
CM
FF
V
A
B
Pulse Gen
IF
CM
V
0 V
O
V
5 V Switching Pos. (A), I = 0
F
O
V (Max)
CM
0.5 V
O
V
H
CML
V (Min)
O
6
7
5
.1 mF
bypass
Switching Pos. (B), I = 7.5 mA
F
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Single−Channel: 6N137M, HCPL2601M, HCPL2611M Dual−Channel: HCPL2630M,
HCPL2631M
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13
REFLOW PROFILE
Time (seconds)
Temperature (°C)
Time 25°C to Peak
260
240
220
200
180
160
140
120
100
80
60
40
20
0
TL
ts
tL
tP
TP
Tsmax
Tsmin
120
Preheat Area
Max. Ramp−up Rate = 3°C/S
Max. Ramp−down Rate = 6°C/S
240 360
Profile Freature Pb−Free Assembly Profile
Temperature Minimum (Tsmin) 150°C
Temperature Maximum (Tsmax) 200°C
Time (tS) from (Tsmin to Tsmax) 60 to 120 s
Ramp−up Rate (tL to tP) 3°C/second maximum
Liquidous Temperature (TL) 217°C
Time (tL) Maintained Above (TL)60 to 150 s
Peak Body Package Temperature 260°C +0°C / –5°C
Time (tP) within 5°C of 260°C30 s
Ramp−down Rate (TP to TL) 6°C/s maximum
Time 25°C to Peak Temperature 8 minutes maximum
Figure 26. Reflow Profile
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HCPL2631M
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14
ORDERING INFORMATION (Note 14)
Part Number Package Shipping†
6N137M PDIP8 9.655x6.6, 2.54P, CASE 646CQ
DIP8−Pin
(Pb−Free)
50 Units / Tube
6N137SM PDIP8 GW, CASE 709AC
SMT 8−Pin (Lead Bend)
(Pb−Free)
50 Units / Tube
6N137SDM PDIP8 GW, CASE 709AC
SMT 8−Pin (Lead Bend)
(Pb−Free)
1000 / Tape & Reel
6N137VM PDIP8 9.655x6.6, 2.54P, CASE 646CQ
DIP 8−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
50 Units / Tube
6N137SVM PDIP8 GW, CASE 709AC
SMT 8−Pin (Lead Bend), DIN EN/IEC 60747−5−5 Option
(Pb−Free)
50 Units / Tube
6N137SDVM PDIP8 GW, CASE 709AC
SMT 8−Pin (Lead Bend), DIN EN/IEC 60747−5−5 Option
(Pb−Free)
1000 / Tape & Reel
6N137TVM PDIP8 6.6x3.81, 2.54P, CASE 646BW
DIP 8−Pin, 0.4” Lead Spacing, DIN EN/IEC60747−5−5 Option
(Pb−Free)
50 Units / Tube
6N137TSVM PDIP8 GW, CASE 709AD
SMT 8−Pin, 0.4” Lead Spacing, DIN EN/IEC60747−5−5 Option
(Pb−Free)
50 Units / Tube
6N137TSR2VM PDIP8 GW, CASE 709AD
SMT 8−Pin, 0.4” Lead Spacing, DIN EN/IEC60747−5−5 Option
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
14. The product orderable part number system listed in this table also applies to the HCPL2601M, HCPL2611M, HCPL2630M and HCPL2631M
product families.
0N Semiwndudw" m 9.40-9.91 EM HI {9’ 6.35-6.86 + 15.0° (MAX) 10.16 (TYP) E III? III? I:I£IiI 0.20-0.40/\ 5.08 (MAX) 3.68-3.94 0.51 (MIN) 1.14-1.78 3.05-3.90 .1. NOTES: A) NO STANDARD APPLIES TO THIS PACKAGE E) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS. MOLD FLASH, AND TIE EAR EXTRUSION gI 9"“"fi (0.7s) 0.41-0.56 2.54 BSC ON Samaanuaamn and J are Mademavks GI Samanaaaxan Cnmpunenls lndusmes Lu: dha ON Samaanaaaxan ar us saasmanas In the Umled Slates andJm mhev commas ON Samaanaaaxan vesewes me thI In make changes wurmm mnhev nauaa In any prawns nanan ON Semanduc‘m makes m7 wavvamy represenlalmn m guarantee regardmg the suIIahIIIly DI IL; pmducls Iur any pamcuIav purpase nnv dues ON Semumnduclm assume any Mammy ansmg umnI [he apphcahan m use HI any pmduclnv mum and specmcaIIy dIscIaIms any and SH IIahIIIly IncIudmg wmham IImIIa‘mn specIaI cansequenhaI m IncIdenlaI damages ON Sammnaaaxan dues nu| aanyay any IIcense under ms paler“ thls war [he
PDIP8 6.6x3.81, 2.54P
CASE 646BW
ISSUE O
DATE 31 JUL 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
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PDIP8 6.6X3.81, 2.54P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m 9.40-9.91 4 PH H31 a4 43/ + 6.35-6.86 IaJ as as L44 5 0.20-0.40 5.08 (MAX) 7.62 (TYP) 3.68-3.94 0.51 (MIN) 3.05-3.90 NOTES: A) NO STANDARD APPLIES TO THIS PACKAGE B) ALL DIMENSIONS ARE IN MILLIMETERS. C)D|MENSIONS ARE EXCLUSIVE OF EURRS. MOLD FLASH, AND TIE BAR EXTRUSION -___-_-4 gI | | I | ! ILI 0.41-0.56 ‘_ 2.54 BSC (0.78) ON SemIcunduclm and are lIadEmavks aI SemIcanduclur Cnmpunenls lnduslIIes LLC dba ON SemIcanduclar ar Ils suhsIdIarIes In Ina Unnau sxaxaa andJnI mhev cmm‘nes ON SemIcunduclar vesewes Ina IIgM Ia make changes mnam InnheI nauaa Ia any pruduns heIeIn ON Semenduc‘nv makes m7 wananIy represenlalmn m guarantee regardmg Ina suItahIIIh/ nI IVS manuals Inr any paflIcuIav purpase nnv dues ON SemIcnnduclm assume any IIahIII|y avIsIng umnI Ina appIIca‘Ian m use In any pmduclnv cIrcuI| and spEcIIIcaIIy dIscIaIms any and aII IIahIII|y IncIudIng wnnam IInmaIIan specIaI cansequemIaI m IncIdenlaI damages ON SemImnduclar dues nn| aanyay any IIcense under na paIanI ngnua Ivar Ina ngma av n|hers
PDIP8 9.655x6.6, 2.54P
CASE 646CQ
ISSUE O
DATE 18 SEP 2017
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13446G
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
PDIP8 9.655X6.6, 2.54P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
0N Semiwndudw" m 9.40-9.91 (1.75) (2-54) m 4 1 P|N1 * I IA % I’Jh AI ( I I I ' I i ‘° {9 I no. 0 - + 3 Q a no '9. v ‘9 I\ IL?‘ 50 5'? I V 5 5 I . I . I I I I I | I | a (0.76) 5.08 MAX # LAND PATTERN RECOMMENDATION 3.68-3.94 0.51 (MIN) 4 M Jr | 0.20-0.40 I I . . I I I I 0.40 (MIN) 2.54BSC 0.41-0.56 m 8.00 (MIN) NOTES 10.30 (MAX) A) NO STANDARD APPLIES TO THIS PACKAGE BIALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS. MOLD FLASHI AND TIE BAR EXTRUSION I. I....IIIIIII II II I....IIIII IIIIII. IIIIIII I. II. I. IIIIIIII II .IIIIIIII II III I... III III I. IIIIIIIII I. III. II I... III. IIIII II I) IIIIII. I. .IIIIIIIIII II )III.) II III.. IIIIIIII .I. III.) II I. III.-. .II I) III... I. .IIIIIIIIIII I) III.) III III IIIIIIII II I. I) IIIIIIIII I.....) III.-. I) II II III.) III... IIIIII .I.III.I.I II IIIIIIII IIIII I. .IIIIIIII III III.) I) III III. III. IIIIIIIII.
PDIP8 GW
CASE 709AC
ISSUE O
DATE 31 JUL 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON13447G
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PAGE 1 OF 1
PDIP8 GW
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
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1
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