Analog Devices Inc. 的 AD8346 规格书

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0.8 GHz to 2.5 GHz
Quadrature Modulator
AD8346
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
High accuracy
1 degree rms quadrature error @ 1.9 GHz
0.2 dB I/Q amplitude balance @ 1.9 GHz
Broad frequency range: 0.8 GHz to 2.5 GHz
Sideband suppression: −46 dBc @ 0.8 GHz
Sideband suppression: −36 dBc @ 1.9 GHz
Modulation bandwidth: dc to 70 MHz
0 dBm output compression level @ 0.8 GHz
Noise floor: −147 dBm/Hz
Single 2.7 V to 5.5 V supply
Quiescent operating current: 45 mA
Standby current: 1 μA
16-lead TSSOP
APPLICATIONS
Digital and spread spectrum communication systems
Cellular/PCS/ISM transceivers
Wireless LAN/wireless local loop
QPSK/GMSK/QAM modulators
Single-sideband (SSB) modulators
Frequency synthesizers
Image reject mixer
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8BIAS
PHASE
SPLITTER
16
15
14
13
12
11
10
9
AD8346
IBBP
IBBN
COM1
COM1
LOIN
LOIP
VPS1
ENBL
QBBP
QBBN
COM4
COM4
VPS2
VOUT
COM3
COM2
05335-001
Figure 1.
GENERAL DESCRIPTION
The AD8346 is a silicon RFIC I/Q modulator for use from
0.8 GHz to 2.5 GHz. Its excellent phase accuracy and amplitude
balance allow high performance direct modulation to RF.
The differential LO input is applied to a polyphase network
phase splitter that provides accurate phase quadrature from
0.8 GHz to 2.5 GHz. Buffer amplifiers are inserted between
two sections of the phase splitter to improve the signal-to-
noise ratio. The I and Q outputs of the phase splitter drive the
LO inputs of two Gilbert-cell mixers. Two differential V-to-I
converters connected to the baseband inputs provide the
baseband modulation signals for the mixers. The outputs of
the two mixers are summed together at an amplifier which is
designed to drive a 50 Ω load.
This quadrature modulator can be used as the transmit mod-
ulator in digital systems such as PCS, DCS, GSM, CDMA, and
ISM transceivers. The baseband quadrature inputs are directly
modulated by the LO signal to produce various QPSK and
QAM formats at the RF output.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8346 comes in a 16-lead TSSOP package, measuring
6.5 mm × 5.1 mm × 1.1 mm. It is specified to operate over a
−40°C to +85°C temperature range and a 2.7 V to 5.5 V supply
voltage range. The device is fabricated on Analog Devices’ high
performance 25 GHz bipolar silicon process.
AD8346
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Equivalent Circuits ........................................................................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description......................................................................... 10
Overview...................................................................................... 10
LO Interface................................................................................. 10
V-to-I Converter......................................................................... 10
Mixers .......................................................................................... 10
Differential-to-Single-Ended Converter ................................. 10
Bias ............................................................................................... 10
Basic Connections...................................................................... 11
LO Drive...................................................................................... 11
RF Output.................................................................................... 11
Interface to AD9761 TXDAC® .................................................. 12
AC-Coupled Interface ............................................................... 13
Evaluation Board ............................................................................ 14
Characterization Setups................................................................. 16
SSB Setup..................................................................................... 16
CDMA Setup............................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Figures 30, 31, 32........................................................ 14
Update Outline Dimensions ......................................................... 18
Changes to Ordering Guide .......................................................... 18
3/99—Revision 0: Initial Version
AD8346
Rev. A | Page 3 of 20
SPECIFICATIONS
VS = 5 V; TA = 25°C; LO frequency = 1900 MHz; LO level = –10 dBm; BB frequency = 100 kHz; BB inputs are dc-biased to 1.2 V; BB input
level = 1.0 V p-p each pin for 2.0 V p-p differential drive; LO source and RF output load impedances are 50 Ω, dBm units are referenced
to 50 Ω unless otherwise noted.
Table 1.
Parameters Conditions Min Typ Max Unit
RF OUTPUT
Operating Frequency 0.8 2.5 GHz
Quadrature Phase Error See Figure 35 for setup 1 Degree rms
I/Q Amplitude Balance See Figure 35 for setup 0.2 dB
Output Power I and Q channels in quadrature −13 −10 −6 dBm
Output VSWR 1.25:1
Output P1 dB −3 dBm
Carrier Feedthrough −42 −35 dBm
Sideband Suppression −36 −25 dBc
IM3 Suppression −60 dBc
Equivalent Output IP3 20 dBm
Output Noise Floor 20 MHz offset from LO −147 dBm/Hz
RESPONSE TO CDMA IS95 BASEBAND SIGNALS
ACPR (Adjacent Channel Power Ratio) See Figure 35 for setup −72 dBc
EVM (Error Vector Magnitude) See Figure 35 for setup 2.5 %
Rho (Waveform Quality Factor) See Figure 35 for setup 0.9974
MODULATION INPUT
Input Resistance 12 kΩ
Modulation Bandwidth −3 dB 70 MHz
LO INPUT
LO Drive Level −12 −6 dBm
Input VSWR 1.9:1
ENABLE
ENBL HI Threshold 2.0 V
ENBL LO Threshold 0.5 V
ENBL Turn-On Time Settle to within 0.5 dB of final SSB
output power
2.5 μs
ENBL Turn-Off Time Time for supply current to drop below
2 mA
12 μs
POWER SUPPLIES
Voltage 2.7 5.5 V
Current Active (ENBL HI) 35 45 55 mA
Current Standby (ENBL LO) 1 20 μA
WARNING'
AD8346
Rev. A | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Min Rating
Supply Voltage VPS1, VPS2 5.5 V
Input Power LOIP, LOIN (relative to 50 Ω) 10 dBm
Min Input Voltage IBBP, IBBN, QBBP, QBBN 0 V
Max Input Voltage IBBP, IBBN, QBBP, QBBN 2.5 V
Internal Power Dissipation 500 mW
θJA 125°C/W
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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AD8346
Rev. A | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IBBP QBBP
AD8346
TOP VIEW
(Not to Scale)
IBBN QBBN
COM1 COM4
COM1 COM4
LOIN VPS2
LOIP VOUT
VPS1 COM3
ENBL COM2
05335-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
Equivalent
Circuit
1 IBBP I Channel Baseband Positive Input Pin. Input should be dc-biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential input
2 V p-p when IBBN is 180 degrees out of phase from IBBP.
Circuit A
2 IBBN I Channel Baseband Negative Input Pin. Input should be dc-biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential input
2 V p-p when IBBN is 180 degrees out of phase from IBBP.
Circuit A
3 COM1 Ground Pin for the LO phase splitter and LO buffers.
4 COM1 Ground Pin for the LO phase splitter and LO buffers.
5 LOIN LO Negative Input Pin. Internal dc bias (approximately VPS1 to 800 mV) is supplied. This
pin must be ac coupled.
Circuit B
6 LOIP LO Positive Input Pin. Internal dc bias (approximately VPS1 to 800 mV) is supplied. This pin
must be ac-coupled.
Circuit B
7 VPS1 Power Supply Pin for the bias cell and LO buffers. This pin should be decoupled using
local 100 pF and 0.01 μF capacitors.
8 ENBL Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C
9 COM2 Ground Pin for the input stage of output amplifier.
10 COM3 Ground Pin for the output stage of output amplifier.
11 VOUT 50 Ω DC-Coupled RF Output. User must provide ac coupling on this pin. Circuit D
12 VPS2 Power Supply Pin for baseband input voltage to current converters and mixer core. This
pin should be decoupled using local 100 pF and 0.01 μF capacitors.
13 COM4 Ground Pin for baseband input voltage to current converters and mixer core.
14 COM4 Ground Pin for baseband input voltage to current converters and mixer core.
15 QBBN Q Channel Baseband Negative Input. Input should be dc biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when
QBBN is 180° out of phase from QBBP.
Circuit A
16 QBBP Q Channel Baseband Positive Input. Input should be dc-biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when
QBBN is 180° out of phase from QBBP.
Circuit A
------
AD8346
Rev. A | Page 6 of 20
EQUIVALENT CIRCUITS
3kΩ
9kΩ
VPS2
INPUT
BUFFER TO MIXER
CORE
ACTIVE LOADS
05335-003
Figure 3. Circuit A
VPS1
LOIN
LOIP
PHASE
SPLITTER
CONTINUES
05335-004
Figure 4. Circuit B
40kΩ
30kΩ
VPS1
TO BIAS FOR
STARTUP/
SHUTDOWN
780Ω
75kΩ
ENBL
75kΩ
05335-005
Figure 5. Circuit C
43Ω
43Ω
VPS2
V
OUT
05335-006
Figure 6. Circuit D
AD8346
Rev. A | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
LO FREQUENCY (MHz)
SSB POWER (dBm)
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15 1200 1600 2000 2400800 1400 1800 22001000
T = 25°C
V
P
= 5.5V
V
P
= 5V
V
P
= 2.7V
V
P
= 3V
05335-007
Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO).
I and Q inputs driven in quadrature at baseband frequency
(FBB) = 100 kHz with differential amplitude of 2.00 V p-p.
SSB OUTPUT POWER (dBm)
–6
–7
–8
–9
–10
–11
–12
–13
LO = 1900MHz, –10dBm
LO = 800MHz, –10dBm
LO = 1900MHz, –6dBm
LO = 800MHz, –6dBm
TEMPERATURE (°C)
–40 –20 0 20304050607080–30 –10 10
05335-008
Figure 8. SSB POUT vs. Temperature. I and Q inputs driven in quadrature
with differential amplitude of 2.00 V p-p at FBB = 100 kHz.
TEMPERATURE (°C)
CARRIER FEEDTHROUGH (dBm)
–35
–40 –20 0 20304050607080
–37
–39
–41
–43
–45
–47
–49
–51 –30 –10 10
V
P
= 5V
V
P
= 5.5V
V
P
= 3V
V
P
= 2.7V
05335-009
Figure 9. Carrier Feedthrough vs. Temperature.
FLO = 1900 MHz, LO input level = –10 dBm.
BASEBAND FREQUENCY (MHz)
OUTPUT POWER VARIATION (dB)
2
0.1 1 100
10
1
0
–1
–2
–3
–4
–5
–6
–7
–8
05335-010
Figure 10. I and Q Input Bandwidth. FLO =1900 MHz, I or Q inputs
driven with differential amplitude of 2.00 V p-p.
LO FREQUENCY (MHz)
SSB OUTPUT P1dB (dBm)
2
800
0
–2
–4
–6
–8
–10
–12
1000
–14 1200 1400 1600 1800 2000 2200 2400
V
P
= 2.7V
T = –40°C
V
P
= 2.7V
T = +85°C
V
P
= 5V
T = –40°C
V
P
= 5V
T = +85°C
05335-011
Figure 11. SSB Output 1 dB Compression Point (OP 1 dB) vs. FLO.
I and Q inputs driven in quadrature at FBB = 100 kHz.
CARRIER FEEDTHROUGH (dBm/
AFTER NULLING TO <–60dBm @ 25°C)
PERCENTAGE
30
–90
25
20
15
10
5
–86
0–82–78–74–70–66–62–58–54–50–46
T
= +85
°C
T
= –40°C
05335-012
Figure 12. Histogram Showing Carrier Feedthrough Distributions
at the Temperature Extremes after Nulling at Ambient
at FLO = 1900 MHz, LO Input Level = –10 dBm.
AD8346
Rev. A | Page 8 of 20
SSB OUTPUT POWER (dBm)
–7
–8
–9
–10
–11
–12
–13
–14
–15
VP = 5V
VP = 3V
VP = 5.5V
VP = 2.7V
TEMPERATURE (°C)
–40 –20 0 20304050607080–30 –10 10
05335-013
Figure 13. SSB POUT vs. Temperature. FLO = 1900 MHz, I and Q inputs driven in
quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz.
LO FREQUENCY (MHz)
CARRIER FEEDTHROUGH (dBm)
–36
–38
–40
–42
–44
–46
–48
–50
–52
–54
1200 1600 2000 2400800 1400 1800 22001000
T = 25°C
V
P
= 3V
V
P
= 5.5V
V
P
= 5V
V
P
= 2.7V
05335-014
Figure 14. Carrier Feedthrough vs. FLO.
LO input level = –10 dBm.
LO FREQUENCY (MHz)
SIDEBAND SUPPRESSION (dBc)
–32
–34
–36
–38
–40
–42
–44
–46
–48 1300 1700 2100 2500900 1500 1900 23001100
T = 25°C
V
P
= 3V
V
P
= 2.7V
V
P
= 5V
V
P
= 5.5V
05335-015
Figure 15. Sideband Suppression vs. FLO. VPOS = 2.7 V, I and Q inputs driven in
quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz.
BASEBAND FREQUENCY (MHz)
SB SUPPRESSION (dBc)
–30
0
–32
–34
–36
–38
–40
–42
–44 2 4 6 8 10 12 14 16 18 20
05335-016
V
P
= 3V V
P
= 5.5V
V
P
= 2.7V
V
P
= 5V
Figure 16. Sideband Suppression vs. FBB. FLO = 1900 MHz, I and Q inputs
driven in quadrature with differential amplitude of 2.00 V p-p.
INPUT THIRD HARMONIC
DISTORTION (dBc)
–35
–40
–45
–50
–55
–60
–65
–70
05335-017
TEMPERATURE (°C)
–40 –20 0 20304050607080–30 –10 10
V
P
= 5.5V
V
P
= 2.7V
V
P
= 3V
V
P
= 5V
Figure 17. Third Harmonic Distortion vs. Temperature.
FLO =1900 MHz, I and Q inputs driven in quadrature with
differential amplitude of 2.00 V p-p at FBB = 100 kHz.
FREQUENCY (MHz)
0
–2
–4
–6
–8
–10
–12
–14
800 1200 1600 2000
–20
RETURN LOSS (dB)
2400
–16
–18
1400 1800 22001000
05335-018
T = +25
°C
T = +85°C
T = –40°C
Figure 18. Return Loss of LOIN Input vs. FLO.
VPOS = 5.0 V, LOIP pin ac-coupled to ground.
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AD8346
Rev. A | Page 9 of 20
SB SUPPRESSION (dBc)
–30
–32
–34
–36
–38
–40
–42
–44
05335-019
TEMPERATURE (°C)
–40 –20 0 20304050607080–30 –10 10
V
P
= 5V
V
P
= 2.7V
V
P
= 3V
V
P
= 5.5V
Figure 19. Sideband Suppression vs. Temperature.
FLO = 1900 MHz, I and Q inputs driven in quadrature
with differential amplitude of 2.00 V p-p at FBB = 100 kHz.
BASEBAND DIFFERENTIAL INPUT
VOLTAGE (V
p-p)
INPUT THIRD HARMONIC
DISTORTION (dBc)
–30
0.5
–35
–40
–45
–50
–55
1.0 1.5 2.0 2.5 3.0
–60
–65
–70
–75
–80
–6
–8
–10
–12
–14
–16
–18
–20
–22
SSB OUTPUT POWER (dBm)
05335-020
SSB P
OUT
3RD HARMONIC
Figure 20. Third Harmonic Distortion and SSB Output
Power vs. Baseband Differential Input Voltage Level.
FLO = 1900 MHz, I and Q inputs driven in quadrature at FBB = 100 kHz.
FREQUENCY (MHz)
0
–5
–10
–15
–20
–25
–30
800 1200 1600 2000
–40
RETURN LOSS (dB)
2400
–35
1400 1800 22001000
05335-021
T = –40°C
T = +25°C
T = +85°C
Figure 21. Return Loss of VOUT Output vs. FLO.
VPOS = 2.7 V.
BASEBAND FREQUENCY (MHz)
INPUT THIRD HARMONIC
DISTORTION (dB)c
–40
0
–45
–50
–55
–60
–65 2468101214161820
05335-022
V
P
= 5V
V
P
= 5.5V
V
P
= 2.7V
V
P
= 3V
Figure 22. Third Harmonic Distortion vs. FBB.
FLO =1900 MHz, I and Q inputs driven in quadrature
with differential amplitude of 2.00 V p-p.
52
50
48
46
44
42
40
38
36
SUPPLY CURRENT (mA)
05335-023
TEMPERATURE (°C)
–40 –20 0 20 40 60 80
V
P
= 5V
V
P
= 2.7V
V
P
= 3V
V
P
= 5.5V
Figure 23. Power Supply Current vs. Temperature
FREQUENCY (MHz)
0
–5
–10
–15
–20
–25
–30
800 1200 1600 2000
–40
RETURN LOSS (dB)
2400
–35
1400 1800 22001000
05335-024
T = –40°C
T = +25°C
T = +85°C
Figure 24. Return Loss of VOUT Output vs. FLO.
VPOS = 5.0 V.
AD8346
Rev. A | Page 10 of 20
CIRCUIT DESCRIPTION
OVERVIEW
The AD8346 can be divided into the following sections: local
oscillator (LO) interface, mixer, voltage-to-current (V-to-I)
converter, differential-to-single-ended (D-to-S) converter, and
bias. A detailed block diagram of the part is shown in Figure 25.
The LO interface generates two LO signals, with 90° of phase
difference between them, to drive two mixers in quadrature.
Baseband voltage signals are converted into current form in
the V-to-I converters, feeding into two mixers. The output of
the mixers are combined to feed the D-to-S converter which
provides the 50 Ω output interface. Bias currents to each
section are controlled by the Enable (ENBL) signal. Detailed
descriptions of each section follows.
LO INTERFACE
The differential LO inputs allow the user to drive the LO differ-
entially in order to achieve maximum performance. The LO can
be driven single-endedly but the LO feedthrough performance
is degraded, especially towards the higher end of the frequency
range. The LO interface consists of interleaved stages of
polyphase network phase splitters and buffer amplifiers. The
phase-splitter contains resistors and capacitors connected in a
circular manner to split the LO signal into I and Q paths in
precise quadrature with each other. The signal on each path
goes through a buffer amplifier to make up for the loss and high
frequency roll-off. The two signals then go through another
polyphase network to enhance the quadrature accuracy. The
broad operating frequency range of 0.8 GHz to 2.5 GHz is
achieved by staggering the RC time constants in each stage of
the phase-splitters. The outputs of the second phase-splitter are
fed into the driver amplifiers for the mixers’ LO inputs.
V-TO-I CONVERTER
Each baseband input pin is connected to an op amp driving an
emitter follower. Feedback at the emitter maintains a current
proportional to the input voltage through the transistor. This
current is fed to the two mixers in differential form.
MIXERS
There are two double-balanced mixers, one for the in-phase
channel (I-channel) and one for the quadrature channel
(Q channel). Each mixer uses the gilbert cell design with four
cross-connected transistors. The bases of the transistors are
driven by the LO signal of the corresponding channel. The
output currents from the two mixers are summed together in
two resistors in series with two coupled on-chip inductors. The
signal developed across the R-L loads is sent to the D-to-S stage.
DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER
The differential-to-single-ended converter consists of two
emitter followers driving a totem-pole output stage. Output
impedance is established by the emitter resistors in the output
transistors. The output of this stage is connected to the output
(VOUT) pin.
BIAS
A band gap reference circuit based on the Δ-VBE principle
generates the proportional-to-absolute-temperature (PTAT)
currents used by the different sections as references. The band
gap voltage is also used to generate a temperature-stable current
in the V-to-I converters to produce a temperature-independent
slew rate. When the band gap reference is disabled by pulling
down the ENBL pin, all other sections are shut off accordingly.
MIXER
MIXER
V-TO-I V-TO-I
V-TO-I V-TO-I
D-TO-S
BIAS CELL
AD8346
LOIN
LOIP
ENBL
QBBP QBBN
V
OU
T
IBBNIBBP
PHASE
SPLITTER
1
PHASE
SPLITTER
2
05335-025
Figure 25. Detailed Block Diagram
U “7
AD8346
Rev. A | Page 11 of 20
BASIC CONNECTIONS
The basic connections for operating the AD8346 are shown in
Figure 27. A single power supply of between 2.7 V and 5.5 V is
applied to pins VPS1 and VPS2. A pair of ESD protection
diodes are connected internally between VPS1 and VPS2 so
these must be tied to the same potential. Both pins should be
individually decoupled using 100 pF and 0.01 μF capacitors,
located as close as possible to the device. For normal operation,
the enable pin, ENBL, must be pulled high. The turn-on
threshold for ENBL is 2 V. To put the device in its power-down
mode, ENBL must be pulled below 0.5 V. Pins COM1 to COM4
should all be tied to a low impedance ground plane.
The I and Q ports should be driven differentially. This is con-
venient as most modern high speed DACs have differential
outputs. For optimal performance, the drive signal should be a
2 V p-p (differential) signal with a bias level of 1.2 V, that is,
each input swings from 0.7 V to 1.7 V. The I and Q inputs have
input impedances of 12 kΩ. By dc coupling the DAC to the
AD8346 and applying small offset voltages, the LO feedthrough
can be reduced to well below its nominal value of −42 dBm
(see Figure 12).
LO DRIVE
The return loss of the LO port is shown in Figure 18. No add-
itional matching circuitry is required to drive this port from a
50 Ω source. For maximum LO suppression at the output, a
differential LO drive is recommended. In Figure 27, this is
achieved using a balun (M/A-COM Part Number ETC1-1-13).
The output of the balun is ac-coupled to the LO inputs which
have a bias level about 800 mV below supply. An LO drive
level of between −6 dBm and −12 dBm is required. For optimal
performance, a drive level of −10 dBm is recommended,
although a level of −6 dBm results in more stable temperature
performance (see Figure 8). Higher levels degrade linearity
while lower levels tend to increase the noise floor.
LOIP
LOIN
AD8346
100pF
100pF
LO
05335-026
Figure 26. Single-Ended LO Drive
The LO terminal can be driven single-ended, as shown in
Figure 26 at the expense of slightly higher LO feedthrough.
LOIN is ac coupled to ground using a capacitor and LOIP is
driven through a coupling capacitor from a (single-ended)
50 Ω source (this scheme could also be reversed with LOIP
being ac-coupled to ground).
RF OUTPUT
The RF output is designed to drive a 50 Ω load, but must be ac-
coupled, as shown in Figure 27. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power is
about −10 dBm (see Figure 7 for variations in output power
over frequency).
QBBP
IBBP
AD8346
QBBN
IBBN
COM4
COM1
COM4
COM1
VPS2
LOIN
VOUT
LOIP
COM3
VPS1
COM2
ENBL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C4
0.01μFC3
100pF
C6
100pF
C7
100pF
T1
ETC1-1-13
1
2
3
5
4
C2
0.01μF
C1
100pF
C5
100pF
IP
IN
LO
+V
S
QP
QN
+V
S
VOUT
05335-027
Figure 27. Basic Connections
AD8346
Rev. A | Page 12 of 20
INTERFACE TO AD9761 TXDAC®
Figure 28 shows a dc-coupled current output DAC interface.
The use of dual-integrated DACs, such as the AD9761 with
specified ±0.02 dB and ±0.004 dB gain and offset matching
characteristics, ensures minimum error contribution (over
temperature) from this portion of the signal chain. The use of a
precision thin-film resistor network sets the bias levels precisely
to prevent the introduction of offset errors, which increase LO
feedthrough. For instance, selecting resistor networks with a
0.1% ratio matching characteristics maintains 0.03 dB gain and
offset matching performance.
Using resistive division, the dc bias level at the I and Q inputs
to the AD8346 is set to approximately 1.2 V. Each of the four
current outputs of the DAC delivers a full-scale current of
10 mA, giving a voltage swing of 0 V to 1 V (at the DAC
output). This results in a 0.5 V p-p swing at the I and Q inputs
of the AD8346 (resulting in a 1 V p-p differential swing).
Note that the ratio matching characteristics of the resistive
network, as opposed to its absolute accuracy, is critical in
preserving the gain and offset balance between the I and Q
signal path.
By applying small dc offsets to the I and Q signals from the
DAC, the LO suppression can be reduced from its nominal
value of −42 dBm to as low as −60 dBm while holding to
approximately −50 dBm over temperature (see Figure 12 for
a plot of LO feedthrough over temperature for an offset
compensated circuit).
I
DAC
2
×
LATCH
IIOUTB
IOUTA
Q
DAC
2
×
LATCH
QQOUTB
QOUTA
MUX
CONTROL
SELECT
WRITE
CLOCK
AD9761
DVDD DCOM AVDD
0.1
μ
F
R
SET
2k
Ω
SLEEP FS ADJ REFIO
DAC
DATA
INPUTS
C
FILTER
100
Ω
100
Ω
C
FILTER
100
Ω
100
Ω
500
Ω
500
Ω
500
Ω
500
Ω
500
Ω
500
Ω
500
Ω
500
Ω
0.1
μ
F
634
Ω
5V
PHASE
SPLITTER
Σ
VOUT
IBBP
IBBN
QBBP
QBBN
AD8346
LOIP
LOIN
VPS1 VPS2
0.5V p-p EACH PIN
WITH V
CM
= 1.2V
+5V
05335-028
Figure 28. AD8346 Interface to AD9761 TxDAC
AD8346
Rev. A | Page 13 of 20
AC-COUPLED INTERFACE
An ac-coupled interface can also be implemented, as shown in
Figure 29. This is an advantage because there is almost no
voltage loss due to the biasing network, allowing the AD8346
inputs to be driven by the full 2 V p-p differential signal from
the AD9761 (each of the DAC’s 4 outputs delivering 1 V p-p).
As in the dc-coupled case, the bias levels on the I and Q inputs
should be set to as precise a level as possible, relative to each
other. This prevents the introduction of additional input offset
voltages. In Figure 29, the bias level on each input is set to
approximately 1.2 V. The 2.43 kΩ resistors should have a ratio
tolerance of 0.1% or better.
The network shown has a high-pass corner frequency of
approximately 14.3 kHz (note that the 12 kΩ input impedance
of the AD8346 has been factored into this calculation).
Increasing the resistors in the network or increasing the
coupling capacitance reduces the corner frequency further.
Note that the LO suppression can be manually optimized by
replacing a portion of the four top 2.43 kΩ resistors with
potentiometers. In this case, the bottom four resistors in the
biasing network no longer need to be precision devices.
2×
LATCH
IIOUTB
IOUTA
2×
LATCH
QQOUTB
QOUTA
MUX
CONTROL
SELECT
WRITE
CLOCK
AD9761
DVDD DCOM AVDD
0.1μF
R
SET
2kΩ
SLEEP FS ADJ REFIO
DAC
DATA
INPUTS
C
FILTER
100Ω
100Ω
C
FILTER
100Ω
100Ω
0.1μF
1kΩ
5V
PHASE
SPLITTER
Σ
VOUT
IBBP
IBBN
QBBP
QBBN
AD8346
LOIP
LOIN
VPS1 VPS2
1V p-p EACH PIN
WITH V
CM
= 1.2V
5V
0.01μF
0.01μF
0.01μF
0.01μF
I
DAC 2.43kΩ
2.43kΩ
2.43kΩ
2.43kΩ
2.43kΩ
2.43kΩ
2.43kΩ
2.43kΩ
Q
DAC
05335-029
Figure 29. AC-Coupled DAC Interface
AD8346
Rev. A | Page 14 of 20
EVALUATION BOARD
The schematic of the AD8346 evaluation board is shown in
Figure 30. This is a 4-layer FR4 board; the two center layers are
used as ground planes and the top and bottom layers are used
for signal and power. Figure 31 shows the layout and Figure 32
shows the silkscreen. The evaluation board circuit closely
follows the basic connections circuit shown in Figure 27.
Slide SW1 to the A position to connect the ENBL pin to +VS
via the 10 kΩ pull-up resistor REP. Slide SW1 to the B position
to disable the device by grounding the ENOP pin through the
49.9 Ω pull-down resistor REG. The device may be enabled via
an external voltage applied to the SMA connector ENOP or TP2.
All connectors are of the SMA type. The I and Q inputs are
provided with pads for implementing a simple RC filter
network. The local oscillator input is driven through a balun
(M/A-COM Part Number ETC1-1-13).
05335-030
C4
100pF C3
0.01
μ
F
QP
QN
CLOP
100pF
CLON
100pF
LO
RLOP
OPEN
RLON
OPEN
RLOS
OPEN
1
2
3
4
5
6
7
8
16
15
14
13
12
10
9
11
IBBP
IBBN
COM1
COM1
LOIN
LOIP
VPS1
ENBL
QBBP
QBBN
COM4
COM4
VPS2
VOUT
COM3
COM2
TP2
ENOP
IP
IN
ENOP
CVO
100pF
VOUT
+V
S
+V
S
AD8346
RQP
0
Ω
CQP
OPEN
RQN
0
Ω
R2
0
Ω
CIP
OPEN
RIP
0
Ω
RIN
0
Ω
CIN
OPEN
C1
0.01
μ
FC2
100pF
R7
0
Ω
T1
ETC1-1-13
1
2
3
5
4
RIS
OPEN RQS
OPEN
CQN
OPEN
REG
49.9k
Ω
REP
10k
Ω
A
B
SW1
Figure 30. Evaluation Board Schematic
1P op 1w 2 IN _ 7/ ON 6ND =~ 5 ; DUT 1 2 up W3 “ 3 ANALOG A01053A mix {a yflL DEVICES L0 c1» ‘* 0; \ CON mm § mo" 9V ‘1‘ R2 C3 EVAL BD m 7 91/ 4i 3‘ c4 cvo vvos 6ND vour J1
AD8346
Rev. A | Page 15 of 20
05335-031
Figure 31. Layout of Evaluation Board
05335-032
Figure 32. Silkscreen of Evaluation Board
AD8346
Rev. A | Page 16 of 20
CHARACTERIZATION SETUPS
SSB SETUP
Two main setups were used to characterize this product. These
setups are shown in Figure 33 and Figure 35. Figure 33 shows
the setup used to evaluate the product as an SSB. The AD8346
motherboard had circuitry that converted the single-ended
I and Q inputs from the arbitrary function generator to differ-
ential inputs with a dc bias of approximately 1.2 V. In addition,
the motherboard also provided connections for power supply
routing. The HP34970A and its associated plug-in 34901 were
used to monitor power supply currents and voltages being
supplied to the AD8346 evaluation board (a full schematic of
the AD8346 evaluation board can be found in Figure 30).
The two HP34907 plug-ins were used to provide additional
miscellaneous dc and control signals to the motherboard. The
LO was driven by an RF signal generator (through the balun on
the evaluation board to present a differential LO signal to the
device) and the output was measured with a spectrum analyzer.
With the I channel driven with a sine wave and the Q channel
driven with a cosine wave, the lower sideband is the single
sideband output. The typical SSB output spectrum is shown in
Figure 34.
VPS1
VN
GND
VP
AD8346
MOTHERBOARD
I IN
QIN
D1 D2 D3
P1 IN IP QP QN
IEEE
34901 34907 34907
D1 D2 D3
HP34970A
AD8346
EVAL BOARD
P1
IN
IP QP
QN
LO
ENBL VOUT
RFOUT
IEEE
HP8648C
+15V MAX
COM
+25V MAX
–25V MAX
IEEE
HP3631
IEEE
PC CONTROLLER
HP8593E
RF I/P
CAL OUT
28VOLT
IEEE
SPECTRUM
ANALYZER
SWEEP OUT
OUTPUT 1
OUTPUT 2IEEE
TEKAFG2020
ARB FUNC. GEN
05335-033
Figure 33. Evaluation Board SSB Test Setup
0
CENTER 1.9GHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–
100 50kHz/ SPAN 500kHz
05335-034
Figure 34. Typical SSB Output Spectrum
AD8346
Rev. A | Page 17 of 20
CDMA SETUP
For evaluating the AD8346 with CDMA waveforms, the setup
shown in Figure 35 was used. This is essentially the same setup
as that used for the single sideband characterization, except that
the AFG2020 was replaced with the AWG2021 for providing the
I and Q input signals, and the spectrum analyzer used to monitor
the output was changed to an FSEA30 Rohde & Schwarz analyzer
with vector demodulation capability. The I/Q input signals for
these measurements were IS95 baseband signals generated with
Tektronix I/Q SIM software and downloaded to the AWG2021.
For measuring ACPR, the I/Q input signals used were generated
with Pilot (Walsh Code 00), Sync (WC 32), Paging (WC 01),
and 6 Traffic (WC 08, 09, 10, 11, 12, 13) channels active. The
I/Q SIM software was set for 32× oversampling and was using a
BS equifilter. Figure 36 shows the typical output spectrum for
this configuration. The ACPR was measured 885 kHz away
from the carrier frequency.
For performing EVM, Rho, phase, and amplitude balance
measurements, the I/Q input signals used were generated with
only the pilot channel (Walsh Code 00) active. The I/Q SIM
software was set for 32× oversampling using a CDMA equifilter.
VPS1
VN
GND
VP
AD8346
MOTHERBOARD
I IN
QIN
D1 D2 D3
P1 IN IP QP QN
IEEE
34901 34907 34907
D1 D2 D3
HP34970A
AD8346
EVAL BOARD
P1
IN
IP QP
QN
LO
ENBL VOUT
RFOUT
IEEE
HP8648C
+15V MAX
COM
+25V MAX
–25V MAX
IEEE
HP3631
IEEE
PC CONTROLLER
FSEA30
RF I/P IEEE
SPECTRUM
ANALYZER
OUTPUT 1
OUTPUT 2IEEE
TEKAFG2020
ARB FUNC. GEN
05335-035
Figure 35. Evaluation Board CDMA Test Setup
–20
CENTER 1.9GHz
–30
–40
–50
–60
–70
–80
–90
–
100
–
110
–
120 187.5kHz/ SPAN 1.875MHz
CH PWR = –20.7dBm
ACP UPR = –71.8dBc
ACP LWR = –71.7dBc
05335-036
Figure 36. Typical CDMA Output Spectrum
AD8346
Rev. A | Page 18 of 20
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 37.16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8346ARU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
AD8346ARU-REEL −40°C to +85°C 16-Lead (TSSOP) 13" Tape and Reel RU-16
AD8346ARU-REEL7 −40°C to +85°C 16-Lead (TSSOP) 7" Tape and Reel RU-16
AD8346ARUZ-REEL1 −40°C to +85°C 16-Lead (TSSOP) 13" Tape and Reel RU-16
AD8346ARUZ-REEL71−40°C to +85°C 16-Lead (TSSOP) 7" Tape and Reel RU-16
AD8346-EVAL Evaluation Board
1 Z = Pb-free part.
AD8346
Rev. A | Page 19 of 20
NOTES
ANALOG DEVICES www.ana|ng.nnm
AD8346
Rev. A | Page 20 of 20
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C05335–0–6/05(A)