EPC 的 EPC8002 规格书

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eGaN® FET DATASHEET EPC8002
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EPC8002 – Enhancement Mode Power Transistor
VDS , 65 V
RDS(on) , 480 mΩ
ID , 2 A
EFFICIENT POWER CONVERSION
EPC8002 eGaN FETs are supplied only in
passivated die form with solder bars
Die Size: 2.1 mm x 0.85 mm
Applications
• Ultra High Speed DC-DC Conversion
• RF Envelope Tracking
• Wireless Power Transfer
• Game Console and Industrial Movement
Sensing (Lidar)
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
HAL
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 65 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 78
ID
Continuous (TA = 25°C, RθJA = 36°C/W) 2A
Pulsed (25°C, TPULSE = 300 µs) 2
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage –4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Static Characteristics (TJ= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 65 V
IDSS Drain-Source Leakage VDS = 52 V, VGS = 0 V 20 100 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.1 1mA
Gate-to-Source Reverse Leakage VGS = -4 V 20 100 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.1 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.5 A 380 480 mΩ
VSD Source-Drain Forward Voltage IS = 0.4 A, VGS = 0 V 2.6 V
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 8.2
°C/WRθJB Thermal Resistance, Junction-to-Board 16
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 82
Specifications are with substrate connected to source where applicable.
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
G
D
S
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Figure 4: Rm", vs Va; [or Vatious Temperatures
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EPC8002
Figure 1: Typical Output Characteristics at 25°C
VDS– Drain-to-Source Voltage (V)
ID– Drain Current (A)
1.5
1.0
2.0
0.5
0.5 1.5 1.0 2.0 2.5 3.0
VGS
GS
GS
GS
= 5 V
V = 4 V
V = 3 V
V = 2 V
0
0
1.5
1.0
2.0
0.5
0
VGS– Gate-to-Source Voltage (V)
ID– Drain Current (A)
0.5 1.0 1.5 2.0 3.02.5 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
1500
1200
900
600
300
0
V
GS
– Gate-to-Source Voltage (V)
2.5 3.0 3.5 4.54.0 5.0
Figure 3: RDS(on) vs VGS for Various Drain Currents
RDS(on)– Drain-to-Source Resistance (mΩ)
ID= 0.5 A
ID= 1.0 A
ID= 1.5 A
ID= 2.0 A
Figure 4: R
DS(on)
vs V
GS
for Various Temperatures
RDS(on) – Drain-to-Source Resistance (mΩ)
25˚C
125˚C
ID = 0.5 A
VGS – Gate-to-Source Voltage (V)
2.5 3.0 3.5 4.54.0 5.0
1500
1200
900
600
300
0
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance
VDS = 32.5 V, VGS = 0 V
20 24
pF
CRSS Reverse Transfer Capacitance 0.12 0.18
COSS Output Capacitance 6.7 10
COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 0 to 32.5 V, VGS = 0 V 8.9
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 10
RG Gate Resistance 0.3 Ω
QG Total Gate Charge VDS = 32.5 V, VGS = 5 V, ID = 0.5 A 133 167
pC
QGS Gate-to-Source Charge
VDS = 32.5 V, ID = 0.5 A
57
QGD Gate-to-Drain Charge 15 26
QG(TH) Gate Charge at Threshold 46
QOSS Output Charge VDS = 32.5 V, VGS = 0 V 334 500
QRR Source-Drain Recovery Charge 0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
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EPC8002
25
20
15
10
5
00 10 30 40 5020 60
Figure 5: Capacitance (Linear Scale)
V
DS
– Drain-to-Source Voltage (V)
C – Capacitance (pF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
10
1
0.1
0.01 0 10 403020 6050
Figure 5A: Capacitance (Log Scale)
VDS– Drain-to-Source Voltage (V)
C – Capacitance (pF)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
4
5
3
1
2
00.05 0.150.1
Figure 6: Gate Charge
Q
G
– Gate Charge (nC)
VGS – Gate-to-Source Voltage (V)
ID= 0.5 A
VDS = 32.5 V
0
25˚C
125˚C
2.0
1.5
1.0
0.5
0
V
SD
– Source-to-Drain Voltage (V)
ISD – Source-to-Drain Current (A)
0.5 0 1.0 1.5 2.0 3.02.5 3.5 4.0 4.5 5.0
Figure 7: Reverse Drain-Source Characteristics
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 5025 75 100 125 150
Figure 8: Normalized On-State Resistance vs Temperature
Normalized On-State Resistance – R
DS(on)
TJ – Junction Temperature (°C)
ID = 0.5 A
VGS = 5 V
ID = 0.1 mA
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
TJ– Junction Temperature (°C)
Normalized Threshold Voltage (V)
0 25 50 75 125100 150
Figure 9: Normalized Threshold Voltage vs Temperature
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EPC8002
1.0
0.9
0.8
0.7
1.2
1.4
1.6
1.8
2.0
0.6
0.5
0.4
0.3
0.2
0.1
3.0
6.0
8.0
10
5.0
4.0
20
RF Café
2002
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
1.0
0.9
0.8
0.7
1.2
1.4
1.6
1.8
2.0
3.0
6.0
8.0
10
5.0
4.0
0.6
0.5
0.4
0.3
0.2
0.1
20
S11 – Gate Reflection
S22 – Drain Reflection
Figure 11: Smith Chart
S-Parameter Characteristics
VGSQ = 1.17 V, VDSQ = 30 V, IDQ = 0.2 A
Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω
Figure 12: Gain Chart Figure 13: Device Reflection
Figure 14: Taper and Reference Plane details – Device Connection
Frequency Gate (ZGS) Drain (ZDS)
[MHz] [Ω] [Ω]
200 3.09 - j29.97 63.13 - j71.32
500 2.20 - j11.92 15.96 -j46.65
1000 1.14 - j4.46 3.35 - j23.47
1200 0.95 - j2.76 1.91 - j18.52
1500 0.87 - j0.55 1.66 - j12.66
2000 1.09 + j2.61 2.28 - j6.12
2400 1.44 + j4.87 4.35 - j2.80
3000 2.36 + j8.79 6.41 + j0.69
S-Parameter Table - Download S-parameter files at www.epc-co.com
ZDS
ZGS
Gate Circuit
Reference Plane
Drain Circuit
Reference Plane
Device Outline
914
1621
1621
149
1000
271
271
All dimensions in µm
914 355
Gmax
45
40
35
30
25
20
15
10
5
0100 1000
Amplitude (dB)
Frequency (MHz)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-0.2
25˚C
125˚C
0.30
0.25
0.20
0.15
0.10
0.05
0
10 32 4 5 6
Figure 10: Gate Leakage Current
VGS – Gate-to-Source Voltage (V)
IG – Gate Current (mA)
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
All measurements were done with substrate shortened to source.
h messes 5 100000000?" —— Dimension(mm) mm min max 3 000 7,90 030 0 175 1.65 1.35 c (seenale) 350 3.45 3.55 d 400 3.90 4.10 e 400 3.90 4.10 Hseenole) 200 1.95 2.05 g 1.5 1.5 16
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EPC8002
Figure 16: Safe Operating Area
0.1
1
0.1 1 10 100
ID - Drain Current (A)
VDS – Drain Voltage (V)
Pulse Width
100 ms
10 ms
1 ms
100 µs
10 µs
Limited by RDS(on)
tp– Rectangular Pulse Duration (s)
1
0.1
0.01
0.001
ZθJB Normalized Thermal Impedance
Single Pulse
Junction-to-Board
0.02
0.01
0.5
0.2
0.1
0.05
Duty Factors:
Duty Factor = tp/T
Peak TJ = PDM x ZθJB x RθJB + TB
Notes:
t
p
T
P
DM
Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
Notes:
t
p
T
P
DM
Single Pulse
0.02
0.01
0.5
0.2
0.1
0.05
Duty Factors:
10-4
10-5 10-3 10-2 10-1 1 10
10-4
10-5 10-3 10-2 10-1 1 10
tp– Rectangular Pulse Duration (s)
Junction-to-Case
ZθJC Normalized Thermal Impedance
1
0.1
0.01
0.001
8002
YYYY
ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC8002 8002 YYYY ZZZZ
DIE MARKINGS
YYYY
8002
ZZZZ
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7”reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
pad bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (see note) 2.00 1.95 2.05
g 1.5 1.5 1.6
EPC8002 (note 1)
U U \ / U
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EPC8002
850
570
2050
1 2
4
3
6
5
400
190
600
600
400
440
190
190
RECOMMENDED LAND PATTERN (measurements in µm)
Recommended stencil should be 4 mil (100 μm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Additional assembly resources available at: https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
DIE OUTLINE
Solder Bar View
Side View
Dim Micrometers
Min Nominal Max
A 2020 2050 2080
B 820 850 880
C 555 580 605
d 400 400 400
e 600 600 600
f 200 225 250
g 175 200 225
h 425 450 475
i 175 200 225
j 400 400 400
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate*
*Substrate pin should be connected to Source
RECOMMENDED STENCIL DRAWING (measurements in µm)
2050
R60
850
325 200 245 230 450 Blue = bump, Gray = stencil
275
272200
592
250200
1 2
4
3
6
5
B
A
i
1 2
3
4
5
6
j
g
x2
e
e
d f
h
C
i
X2
815 Max
100 +/- 20
Seating Plane
(685)
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability,
function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
The land pattern is solder mask defined.
Solder mask opening is 5 µm smaller per side than bump.
Information subject to
change without notice.
Revised August, 2019
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source
Pad no. 4 is Drain
Pad no. 6 is Substrate*
*Substrate pin should be connected to Source