IXYS Integrated Circuits Division 的 CPC7512 规格书

IIIIXYS @ ies Switches Open Contam Isolation up to 1 ks up to: ® fins.
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Features
•Up to ±320V Switch to Ground Potential
•Series Switches Open Contact Isolation up to +600V
•60dB Off Isolation at 1MHz
•Thermal Shutdown Protects Against Fault
Conditions
•Guaranteed Break-Before-Make
•Low, Matched RON
•Flexible Switch Configurations
•Smart Logic for Power-Up/Hot-Plug State Control
•5V Operation with Very Low Power Consumption
•TTL Logic-Level Inputs
•Input Latch
•Clean, Bounce-Free Switching
•Monolithic IC Reliability
Applications
•Multiplexed Ultrasonic Transducer Switching
•Battery Monitoring and Charging
•Automatic Test Equipment (ATE)
•Instrumentation
•Industrial Controls and Monitoring
Description
The CPC7512 dual 1-Form-A high-voltage,
high-frequency, shunt-isolated analog switch builds
upon IXYS Integrated Circuits Division’s design and
fabrication expertise for industrial applications. This
monolithic solid state device provides the switching
functionality of two normally open (1-Form-A) solid
state relays for high frequency applications in one
small economical package. Both switches incorporate
shunt isolation by means of a T-switch compensation
technique to minimize series capacitance through the
open off-state switches for improved off-state isolation
over frequency.
Designed to provide flexible single-ended or
differential access to high voltage networks, the
CPC7512 is functionally configured as two
independent logical switches. The self-biasing
switches do not require external high-voltage supplies
for proper operation.
An integrated thermal shutdown feature provides not
only enhanced protection for devices connected to
high voltage networks up to +320V, but also an
external signal to indicate the device is shut down.
Ordering Information
Figure 1. CPC7512 Block Diagram
Part # Description
CPC7512Z 20-Pin SOIC in Tubes (40/Tube)
CPC7512ZTR 20-Pin SOIC Tape & Reel (1000/Reel)
S1B
S1C
S1COM
S1A
TSD
LATCH1
S1IN0
S1IN1
Switch 1
Control
Logic
L
A
T
C
H
S2B
S2C
S2COM
S2A
LATCH2
Switch 2
Control
Logic
L
A
T
C
H
S2IN0
S2IN1
SW1ASW1B
SW1C
SW2ASW2B
SW2C
CPC7512
Dual 1-Form-A Shunt-Isolated
High-Voltage High-Frequency Analog Switch
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1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Switch Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7 Switch Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.8 VDD Voltage Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.9 Protection Circuitry Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.10 Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2. Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Under-Voltage Switch Lock-Out Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1 Data Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5.1 Dynamic High Frequency Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5.2 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Thermal Design Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Startup State Following Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Initial Configuration State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 Driving Channel 1 Ultrasonic Transducer X1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Ultrasonic Transducer X1 Drive Complete. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Driving Channel 2 Ultrasonic Transducer X2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1 CPC7512Z Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.2 CPC7512ZTR Tape & Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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1. Specifications
1.1 Package Pinout 1.2 Pin Descriptions
Pin Types:
P = Power
I = Digital Input
I/O = Digital Input / Output with internal pull up.
A = Analog I/O
S2B
TSD
S2A
VDD
LATCH2
S2IN0
S2IN1
S2C
S2COM
S1B
S1A
VDD
GND
LATCH
1
S1IN0
S1IN1
S1C
S1COM
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
N/C
N/C
Pin Name Type Description
6,14 VDD P Logic Supply Voltage
7 GND P Ground
9, 12 N/C - Not Connected
15 TSD I/O Thermal Shutdown
Switch 1
1S1CASwitch 1 Port C
2S1COM ASwitch 1 common node for all three
switches
8S1AASwitch 1 Port A
10 S1BASwitch 1 Port B
3S1IN1 I Switch 1 input control bit: Bit 1
4S1IN0 I Switch 1 input control bit: Bit 0
5LATCH1I Switch 1 configuration latch
Switch 2
20 S2CASwitch 2 Port C
19 S2COM ASwitch 2 common node for all three
switches
13 S2AASwitch 2 Port A
11 S2BASwitch 2 Port B
17 S2IN0 I Switch 2 input control bit: Bit 0
18 S2IN1 I Switch 2 input control bit: Bit 1
16 LATCH2I Switch 2 configuration latch
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1.3 Absolute Maximum Ratings
Absolute maximum electrical ratings are at 25C.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
1.4 General Conditions
Unless otherwise specified, minimum and maximum
values are guaranteed by production testing or design.
Typical values are characteristic of the device at 25°C,
and are the result of engineering evaluations. They are
provided for informational purposes only and are not
guaranteed by production testing.
Unless otherwise noted the specifications cover the
VDD operational range and the ambient operating
temperature range TA=-40Cto+85C. Testing is
performed with the logic low input voltage VIL =0V
DC
and the logic high input voltage VIH =V
DD.
Parameter Minimum Maximum Unit
VDD (+5V supply) -0.3 + 7 V
Logic input voltage -0.3 VDD + 0.3 V
Switch output to logic inputs
isolation -320V
Switch output to ground - 320 V
Series switch open-contact
isolation (Across any two series
switches)
-600V
Operating relative humidity,
Non-Condensing 595%
Junction operating temperature -40 +110 C
Ambient operating temperature -40 +85 C
Storage temperature -40 +150 C
'IIXYS Current Limit (1 g
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1.5 Switch Electrical Specifications
NOTE: VSW is the voltage across a switch or a pair of switches in series and VS is the voltage at a switch pin with respect to ground.
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Off-State Leakage Current VSW = SxA to SxCOM, SxBto SxCOM,
SxCto SxCOM; SxCOM = Gnd; All switches Off
+25C, VSW = +320V
-
+0.1
+1
+85C, VSW = +330V ISW +0.3 A
-40C, VSW = +310V +0.1
On Resistance:
SxA to SxB
SWxA = SWxB = On, SWxC = Off
ISW = ±10mA, ±40mA
+25C-29-
+85CRON --62
-40C-21-
On Resistance Matching:
SxA to SxB Per On Resistance Test Conditions RON -0.11
On Resistance: SWxC,
SxCto SxCOM
SWxA = SWxB = Off, SWxC = On
ISW = ±10mA, ±40mA
+25C-60-
+85CRON - 85 110
-40C-45-
Off-State Voltage Maximum Differential Voltage1,2, Switches Off VOFF - - 600 V
High Frequency Dynamic
Current Limit (t <0.5 s)
Apply ±1 kV 10x1000 s pulse with appropriate
protection in place 2, Switches On
ISW -1-A
Logic Input to Switch Output
Isolation
VS = SxAto Gnd, SxBto Gnd, SxCto Gnd,
SxCOM to Gnd; All switches Off.
+25C, VS = ±320V +0.1
+85C, VS = ±330V ISW -+0.3 +1A
-40C, VS = ±310V +0.1
Crosstalk 50 Termination, f=1MHz 3 --55 - -dB
Off-State Isolation 50 Termination, f=1MHz 4 -5060 -dB
Switch to Ground Capacitance All switches Off,
SxA,SxB, SxC, and SxCOM are open circuit
SxAto Gnd, SxBto Gnd -80-
SxCto Gnd C-40-pF
SxCOM to Gnd - 115 -
Transient Immunity 100VP-P Square Wave at 100Hz dV/dt 1500 2100 - V/s
1 Across any two inactive (Off) switches.
2 Maximum +/- 310V with respect to ground at any switch.
3 See “Figure 1. Crosstalk Test Configuration” on page 6.
4 See “Figure 2. Switch Off-State Isolation Test Configuration” on page 6.
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Figure 1. Crosstalk Test Configuration Figure 2. Switch Off-State Isolation Test Configuration
1.6 Digital I/O Electrical Specifications
1.7 Switch Timing Specifications
Crosstalk =
+20 log VM
VS
VM
+
50Ω
VS
Open
Open
AB
C
AB
C
Isolation =
+20 log V
S
V
M
V
M
+
V
S
50Ω
AB
C
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Input Characteristics
Input Voltage: (SxINx, LATCHx, TSD)
Logic High Threshold Input voltage rising VIH -1.52.0V
Logic Low Threshold Input voltage falling VIL 0.8 1 - V
Hysteresis VIN 500 mV
Input Leakage Current
Logic High:
SxINx
VIH =2.4V I
IH
-0.11
ALATCHx -10 -19 -175
TSD -10 -16 -50
Logic Low:
SxINx
VIL =0.4V I
IL
-0.11
ALATCHx --47 -250
TSD --16 -50
Output Characteristics
Output Voltage: TSD:
Logic High ITSD = 10AV
TSD_Off 2.4 VDD -V
Logic Low ITSD = 1mA VTSD_On -00.4V
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Switch turn on delay LATCHx = 0V, ISW_off = 0mA, ton @ ISW =9mA t
d_on - 0.25 1.0 ms
Switch turn off delay LATCHx = 0V, ISW_on = 10mA,
toff @I
SW =0.5mA td_off - 0.05 0.5 ms
No Overlap1
(Break-before-make)
SxA to SxC, SxB to SxC, td_off < td_on,
Both directions, 4.75 < VDD < 5.25V TRUE
1 This parameter ensures the turn off time for Switches A and B is less than the turn on time of Switch C and the turn off time of Switch C is less than the turn on
time of Switches A and B thereby assuring there is no conduction from either Switch A or B through Switch C when switching between complementary states.
IIIIXYS P m m < u="" a="" m="">
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1.8 VDD Voltage Supply Specifications
Note: To ensure compliance of the “No Overlap” parameter given in Section 1.7 "Switch Timing Specifications” on
page 6, the operational voltage range is reduced as listed above.
1.9 Protection Circuitry Thermal Specifications
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Voltage Requirements
Voltage operational range -VDD 4.5 5 5.5 V
No Overlap: See Note VDD 4.7555.25V
Current Specifications
VDD Current 4.5 < VDD < 5.5V, All States,
All logic I/O = Open
IDD 0.4 1.5 2.3 mA
Under Voltage Lockout Specifications
Thresholds VDD rising
UVLO
-3.4-
VVDD falling -3-
Hysteresis - 0.4 -
Parameter Conditions Symbol Minimum Typical Maximum Unit
Thermal Shutdown Temperature Specifications 1
Thermal shutdown activation
temperature Not production tested - limits are guaranteed by
design and Quality Control sampling audits
TTSD_on 110 125 150 C
Shutdown circuit hysteresis TTSD_off 10 - 25 C
1 Thermal shutdown flag (TSD) will be high during normal operation and low during thermal shutdown state.
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1.10 Truth Table
The truth table and block diagram are shown for Switch 1. Operation is the same for both switches, S1 and S2. Refer
to accompanying block diagram.
LATCH1S1IN1 S1IN0 TSD SW1ASW1BSW1CSwitch State
000
Z 2
OFF OFF OFF All-Off: All switches are open (Off) 1
001 OFF ON ON BC: S1B connected to S1C
010 ON ON OFF AB: S1A connected to S1B
011 OFF OFF ON C: S1C connected S1COM
1xx Unchanged Unchanged Unchanged Latest switch state persists
xxx
0 3 OFF OFF OFF Thermal shutdown active,
all switches are open (Off)
xxx
0 4,5 OFF OFF OFF All-Off: All switches are open (Off)
1 Default state following power up and after an under-voltage lock out event.
2 Z = High Impedance with a weak internal pull-up. Because TSD has an internal pull-up, it should be controlled with an open-collector or open-drain type device.
3 TSD outputs a logic low.
4 TSD driven to a logic low by an external device. External device output should be an open-collector or an open-drain type.
5 When TSD is released, the switches revert back to their previous state.
S1B
S1C
S1COM
S1A
LATCH1
S1IN0
S1IN1
Switch 1
Control
Logic
L
A
T
C
H
TSD
SW1ASW1B
SW1C
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2. Performance Data
Figure 3. On-State Insertion Loss: SxA to SxB Figure 4. Off-State Switch Isolation: SxA to SxB
Figure 5. Switch to Switch Cross Talk
VM
+
VS50Ω
+20 log VS
VM
Insertion Loss = AB
C
Frequency
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz 1GHz
Loss (dB)
10
8
6
4
2
0
Insertion Loss Into 50Ω
Frequency
Isolation (dB)
140
120
100
80
60
40
20
0
Off-State Isolation into 50Ω
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz
Isolation =
+20 log V
S
V
M
V
M
+
V
S
50Ω
AB
C
Frequency
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz
Transfer Gain (dB)
-140
-120
-100
-80
-60
-40
-20
0
Cross Talk into 50Ω
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3. Functional Description
3.1 Introduction
The CPC7512 Dual, 1Form-A, Shunt-Isolated
High-Voltage, High-Frequency, Analog Switch has two
symmetrical switch arrays with four operating states to
facilitate switching of high-frequency, high-voltage
signals using the AB and C switch states and the
flexibility to provide a variety of alternative switching
solutions for low-frequency high-voltage signal
applications. Operational states and logical behavior
of the device is shown in the “Truth Table” on
page 8. Switch organization consists of two channels,
each having three switches.
Within each channel there is an independent LATCH
input and a common Thermal Shutdown circuit that is
shared by the two channels. Other than the shared
TSD circuit, switch functionality under normal
operating conditions within each channel is
independent of the other channel. In designs where
the switches will be required to carry high load
currents or operate in higher temperature
environments, the thermal specifications should be
reviewed because the TSD circuit is shared by both
channels. An excess thermal condition in one channel
resulting in an active TSD event will cause an
interruption in the other channel as well when the TSD
protection circuit activates.
Solid-state switch construction of the CPC7512 offers
clean, bounce-free switching with simple TTL logic
level input control to provide access to high voltage
interfaces without the impulse noise generated by
traditional electromechanical switching techniques.
TTL logic level input control eliminates the additional
driver circuitry required by traditional techniques.
The low on-resistance (RON) symmetrical linear
switches utilized in the AB switch state are configured
as matched pairs, SW1A/SW1B and SW2A/SW2B, for
improved performance when differential access is
required. Their symmetrical construction provides an
additional degree of design flexibility allowing either
side of the switch to be connected to the high voltage
network.
Integrated into the CPC7512 switches are high
frequency dynamic current limiting and thermal
shutdown mechanisms to provide protection for the
electronics being connected to a high voltage network
during a fault condition. High frequency positive and
negative transient currents such as lightning are
reduced by the dynamic current limiting function while
protection from prolonged low frequency power-cross
and DC currents is provided by the thermal shutdown
circuitry.
To protect against a high voltage fault in excess of the
CPC7512’s maximum voltage rating, use of an
over-voltage protector is required. The protector must
limit the voltage seen at the switch terminals to a level
less than the switches’ breakdown voltage. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type protector is highly
recommended. With proper selection of the protector,
telecom applications using the CPC7512 will meet all
relevant ITU, LSSGR, TIA/EIA and IEC protection
requirements.
Operating from a single +5V supply the CPC7512 has
extremely low power consumption.
3.2 Under-Voltage Switch Lock-Out Circuitry
Smart logic in the CPC7512 provides for switch state
control during both power up and power loss
transients to prevent undesired connections to high
voltage networks. This is done by setting the switches’
logic to the All-Off state. An internal detector evaluates
the VDD supply against internally set thresholds to
determine when to de-assert the under-voltage switch
lock-out circuitry with a rising VDD, and when to assert
the under-voltage switch lock-out circuitry with a falling
VDD. Any time unsatisfactory low VDD conditions exist,
the lock-out circuit overrides user switch control by
blocking the external information applied to the input
pins, output by the internal latch, and conditioning the
internal switch commands to the All-Off state. Upon
restoration of VDD, the switches will remain off until the
LATCHx input is pulled low at which time proper
conditioning of the SxIN0 and SxIN1 inputs must be
made.
The rising VDD lock-out release threshold ensures all
internal logic is properly biased and functional before
accepting external switch commands from the inputs.
For a falling VDD event, the lock-out threshold is set to
assure proper logic and switch behavior up to the
moment the switches are forced off and external
inputs are suppressed.
the telecom GR-1089-CORE specified :
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3.3 Switch Logic
The CPC7512 under-voltage switch lock-out circuitry
monitors the VDD supply to ensure proper and safe
switch behavior whenever the supply voltage is
inadequate.
Under normal VDD supply conditions data applied to
the SxIN0 and SxIN1 inputs is controlled by the LATCH.
The LATCH, depending on the logic level applied to it’s
control input LATCHx, will either block the input data or
pass the input data to the switch control logic. Once
the input data is passed to the switch control logic, the
value from the inputs will be locked by the LATCH
when the LATCHx control is asserted to a logic HIGH.
3.3.1 Data Latch
The CPC7512 has two integrated transparent data
latches, one for each channel. The latch-enable
operation is controlled by TTL input logic levels at the
LATCHx pins. Inputs to the data latch are via the SxIN0
and SxIN1 input pins while the data latch outputs are
internal nodes used for state control. When LATCHx,
the latch enable control pin, is at a logic 0 the data
latch is transparent and the input control signals flow
directly through the data latch to the state control
circuitry. A change in input will be reflected by a
change in the switch state.
Whenever the latch enable control pin is at logic 1, the
data latch is active and the control data is locked.
Subsequent changes to the SxIN input control pins will
not result in a change to the control logic or affect the
existing switch states.
The switches will remain in the state they were in
when the LATCHx changes from logic 0 to logic 1, and
will not respond to subsequent changes in input as
long as the LATCHx is at logic 1. TSD however is not
constrained by the latch function. Since internal
thermal shutdown control is not affected by the state of
the latch enable input, TSD will override state control.
3.3.2 TSD Pin Description
The TSD pin is a bidirectional I/O structure with an
internal pull-up resistor sourced from VDD. As an
output, this pin indicates the status of the thermal
shutdown circuitry of the CPC7512. During normal
operation this pin will typically be pulled up to VDD but
under fault conditions that create excess thermal
loading, the entire device will enter thermal shutdown
and a logic low will be output at TSD.
As an input, the TSD pin can be used to place the
device into the All-Off state by simply pulling the input
low. This is a convenient way to temporarily place the
device’s switches into the off state without the need to
cycle the inputs and LATCH controls through an off
and then an on sequence. When TSD is released, the
device will revert back to it’s previous state.
When using TSD as an input, IXYS Integrated Circuits
Division recommends the use of an open-collector or
an open-drain type output to apply the logic LOW.
Forcing TSD to a logic 1 or tying it to VDD does not
affect the CPC7512 thermal shutdown functionality.
The device ignores this input level and still enters the
thermal shutdown state at high temperature. In other
words, the thermal shutdown feature can not be
overridden by an external pull-up on the TSD control.
3.4 Power Supplies
Only a +5V logic supply and ground are required by
the CPC7512. Switch state control is powered
exclusively by the +5V supply. As a result, the
CPC7512 exhibits extremely low power consumption
during active and idle states.
3.5 Protection
The CPC7512 provides protection for both the low
voltage side circuitry it connects to high voltage
networks and itself. Two separate layers of protection
are interleaved within the device to protect against
high-energy high-frequency transients and
high-power, low-frequency fault conditions.
3.5.1 Dynamic High Frequency Current Limit
While in a closed switch state, high-frequency
high-energy current is restricted by the CPC7512. For
the telecom GR-1089-CORE specified +1000V
10x1000s lightning pulse with a generator source
impedance of 10 applied to the high voltage network
though a properly clamped external protector, the
current seen at the CPC7512 low voltage side
interface will be a pulse with a typical magnitude of 1A
and a duration less than 0.5s.
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3.5.2 Thermal Shutdown
The thermal-shutdown mechanism activates when the
device’s die temperature reaches a minimum of
110°C, placing the device into the All-Off state
regardless of logic input. During thermal shutdown
events the TSD pin will output a logic low with a
nominal 0V level. A logic high is output from the TSD
pin during normal operation with a typical output level
equal to VDD.
If presented with a short-duration transient, such as a
lightning event, the thermal-shutdown feature will
typically not activate. But, in an extended power-cross
event the device temperature will rise and the thermal
shutdown mechanism will activate, forcing the device’s
switches to the All-Off state. At this point the current
into the active switch will drop to zero. Once the device
enters thermal shutdown, it will remain in the All-Off
state until the internal temperature of the device drops
below the de-activation level of the thermal-shutdown
circuit. This permits the circuit to autonomously return
to normal operation. If the fault has not passed,
current will again flow and heating will resume,
causing the thermal-shutdown mechanism to
reactivate. This cycle of entering and exiting the
thermal-shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, with an external
over-voltage protector present, the external protector
will activate shunting the fault current to ground.
3.6 External Protection Elements
The CPC7512 requires only over-voltage protection
on the high-voltage side of the switch. Additional
external protection may be required on the low-voltage
side of the switch if the threshold of the high-voltage
side protector exceeds the safe operation of the
low-voltage side components. Because the fault
current seen by the low-voltage side protector is
limited by the switch’s high frequency dynamic current
limit, the low-voltage side protector need not be as
capable as that of the high-voltage side protector. The
high-voltage side protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC7512. A foldback or crowbar type protector on the
high-voltage side is recommended to minimize
stresses on the CPC7512.
3.7 Thermal Design Assessment
A successful design utilizing the CPC7512
High-Voltage Analog Switch Array is dependent on
careful consideration of the application’s environment
and the device’s thermal constraints. For matters
regarding the electrical design, this is simply a case of
following the parameters provided in the preceding
tables and for many this will be sufficient. However,
those designers wishing to push the operational limits
envelope with higher switch current and/or higher
ambient operating temperatures will need to consider
the thermal performance.
Being a real physical device the CPC7512 has a finite
thermal capability that when properly considered will
ensure appropriate behavior and performance.
Determination of the thermal constraint is easily
accomplished using the following power equations:
and
Where is the dissipated power drawn from the
VDD supply and is the total power dissipated by
all active switches. The VDD power can be calculated
from the “VDD Voltage Supply Specifications” on
page 7 while the power dissipated by the switches is
the sum of the concurrently active switches. Total
switch power is the sum of: the squared maximum
current through each active switch times the
On-Resistance of the switch (ISWx2xR
ON).
The second equation is used to calculate the
maximum ambient temperature the device can be
operated in based on the calculated total power of the
previous equation. PTOTAL, the value obtained in the
first equation; T, the junction temperature rise of the
CPC7512 from ambient; and JA, the thermal
impedance of the device package are used to
determine the maximum operating ambient
temperature.
PTOTAL PVDD PSW
+=
PTOTAL
T
JA
---------=
PVDD
PSW
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Using the junction temperature rise equation
T=T
J-T
A; the thermal impedance JA = 65.8C/W;
and a maximum junction temperature
TJ(max) = 110C, the equation reduces to:
To avoid entering thermal shutdown, the value for the
maximum junction temperature was set to 110C as
specified in the Absolute Maximum Ratings table.
Conversely, it is possible to rework the equations to
determine the maximum switch current for a maximum
ambient current.
When using the individual switches of the CPC7512
within their allowable operating region, no restrictions
are placed on any other switch.
TAmax
TJmax
PTOTAL JA
–=
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4. Design Example
The CPC7512 can be used to provide a multiplexer function in ultrasonic transducer applications allowing the
expense and the PCB real estate consumption of a transducer drive circuitry to be spread across multiple
transducers. The steps to implement this concept are shown in the minimal two channel example below.
To maximize isolation between the drive circuit and non-driven transducer receiver circuits, the SxC terminal must be
connected to ground.
4.1 Startup State Following Power Up
To facilitate a stable and safe power up transition or recovery from a supply voltage droop, all of the switches in the
CPC7512 are preconditioned to the All-Off state upon power up. As can be seen in the figure below, all of the
switches are open.
Figure 6: Power Up Default State
4.2 Initial Configuration State
Following power up, the switches should be placed in the high impedance shunt isolation state. To provide maximum
shunt isolation, switches SW1C and SW2C must be terminated to ground and the switches enabled (Closed). This
state minimizes signal transfer through the open A and B switches.
Figure 7: Switches A and B Open With Shunt Isolation Enabled
S1B
S1C
S1COM
S1A
S2B
S2C
S2COM
S2A
SW1ASW1B
SW1C
SW2ASW2B
SW2C
X1
X2
To Receiver Circuit 1
To Receiver Circuit 2
S1B
S1C
S1COM
S1A
S2B
S2C
S2COM
S2A
SW1ASW1B
SW1C
SW2ASW2B
SW2C
X1
X2
To Receiver Circuit 1
To Receiver Circuit 2
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4.3 Driving Channel 1 Ultrasonic Transducer X1
To drive X1, the first transducer, switches SW1A and SW1B are closed and switch SW1C is opened. The closed
switches pass the high voltage 40-50kHz signal output by the drive circuitry through the series resistor to the
transducer.
In Channel 2, the portion of the high-voltage, high-frequency signal output by the drive circuitry that passes through
the open SW2A switch is shunted to ground through the closed SW2C switch.
Figure 8: Driving Ultrasonic Transducer X1
4.4 Ultrasonic Transducer X1 Drive Complete
Once the transducer is energized it is separated from the generator by opening Switches SW1A and SW1B. This
prevents the large stimulus source voltage from overwhelming the transducer’s much smaller output voltage created
from the energy of the reflected ultrasonic pulse. To assist in minimizing corruption of the X1 transducer’s output
signal, SW1C is closed. This enhances switch isolation. The X1 transducer’s output voltage is picked up by Receiver
Circuit 1 and sent on to the microcontroller.
Figure 9: Separating Drive Circuitry From Transducer X1
S1B
S1C
S1COM
S1A
S2B
S2C
S2COM
S2A
SW1ASW1B
SW1C
SW2ASW2B
SW2C
X1
X2
To Receiver Circuit 1
To Receiver Circuit 2
S1B
S1C
S1COM
S1A
S2B
S2C
S2COM
S2A
SW1ASW1B
SW1C
SW2ASW2B
SW2C
X1
X2
To Receiver Circuit 1
To Receiver Circuit 2
$3: W W K§§K
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4.5 Driving Channel 2 Ultrasonic Transducer X2
Following the driving of transducer X1, the second transducer can be stimulated. The procedure for Channel 2 is the
same as that of Channel 1.
Figure 10: Driving Ultrasonic Transducer X2
For larger systems additional CPC7512’s can be used allowing expansion of the single drive circuitry to as many
transducers as needed.
S1B
S1C
S1COM
S1A
S2B
S2C
S2COM
S2A
SW1ASW1B
SW1C
SW2ASW2B
SW2C
X1
X2
To Receiver Circuit 1
To Receiver Circuit 2
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5. Manufacturing Information
5.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
5.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
5.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
5.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
Device Moisture Sensitivity Level (MSL) Rating
CPC7512Z MSL 1
Device Maximum Temperature x Time Maximum Reflow Cycles
CPC7512Z 260°C for 30 seconds 3
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5.5 Mechanical Dimensions
5.5.1 CPC7512Z Package Dimensions
5.5.2 CPC7512ZTR Tape & Reel Specification
(inches)
mm
DIMENSIONS
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
0.254 / +0.051 / -0.025
(0.010 / +0.002 / -0.001)
0.889 ± 0.178
(0.035 ± 0.007)
45º
0.406 ± 0.076
(0.016 ± 0.003)
12.757 ± 0.254
(0.502 ± 0.010)
7.493 ± 0.127
(0.295 ± 0.005)
10.312 ± 0.381
(0.406 ± 0.015)
1.270 TYP
(0.050 TYP)
PIN 1
PIN 20
0.649 ± 0.102
(0.026 ± 0.004)
2.337 ± 0.051
(0.092 ± 0.002)
0.203 ± 0.102
(0.008 ± 0.004)
2.00
(0.079)
1.27
(0.050)
9.40
(0.370)
0.60
(0.024)
Recommended PCB Land Pattern
Dimensions
mm
(inches)
NOTE: Unless otherwise specified, all dimension tolerances per EIA-481
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
K0=3.20±0.15
(0.126±0.006)
K1=2.60±0.15
(0.10±0.006)
P=12.00
(0.47)
A0=10.75±0.15
(0.42±0.006)
B0=13.40±0.15
(0.53±0.006)
W=24.00±0.3
(0.94)
Specifications: DS-CPC7512-R01
© Copyright 2015, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
2/27/2015
For additional information please visit www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applica-
tions intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or
environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.