EPC 的 EPC2100 规格书

RoHS (A @ Halogen-Free
eGaN® FET DATASHEET EPC2100
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
VDS , 30 V
RDS(on) , 8.2 mΩ (Q1), 2.1 mΩ (Q2)
ID , 10 A (Q1), 40 A (Q2)
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
EPC2100 eGaN® ICs are supplied only in
passivated die form with solder bumps
Die Size: 6.05 mm x 2.3 mm
Applications
• High Frequency DC-DC
• Point-of-Load (POL) Converters
Benefits
• High Frequency Operation
• Ultra High Efficiency
• High Density Footprint
EFFICIENT POWER CONVERSION
HAL
Maximum Ratings
DEVICE PARAMETER VALUE UNIT
Q1
VDS
Drain-to-Source Voltage (Continuous) 30 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
36
ID
Continuous (TA = 25°C, RθJA = 92°C/W) 10 A
Pulsed (25°C, TPULSE = 300 µs) 100
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Q2
VDS
Drain-to-Source Voltage (Continuous) 30 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
36
ID
Continuous (TA = 25°C, RθJA = 22°C/W) 40 A
Pulsed (25°C, TPULSE = 300 µs) 400
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Thermal Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction-to-Case
0.4
°C/W RθJB
Thermal Resistance, Junction-to-Board
2.5
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
42
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
EPC2100 – Enhancement-Mode GaN Power
Transistor Half-Bridge
eGaN® FET DATASHEET EPC2100
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2
Dynamic Characteristics
DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Q1
CISS Input Capacitance
VDS = 15 V, VGS = 0 V
395 475
pF
CRSS Reverse Transfer Capacitance 15
COSS Output Capacitance 290 435
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 15 V, VGS = 0 V
371
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 404
QG Total Gate Charge VDS = 15 V, VGS = 5 V, ID = 25 A 3.6 4.9
nC
QGS Gate-to-Source Charge
VDS = 15 V, ID = 25 A
1.3
QGD Gate-to-Drain Charge 0.6
QG(TH) Gate Charge at Threshold 0.9
QOSS Output Charge VDS = 15 V, VGS = 0 V 6.1 9.2
QRR Source-Drain Recovery Charge 0
Q2
CISS Input Capacitance
VDS = 15 V, VGS = 0 V
1630 1960
pF
CRSS Reverse Transfer Capacitance 64
COSS Output Capacitance 1370 2060
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 15 V, VGS = 0 V
1740
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 1900
QG Total Gate Charge VDS = 15 V, VGS = 5 V, ID = 25 A 15 19
nC
QGS Gate-to-Source Charge
VDS = 15 V, ID = 25 A
4.8
QGD Gate-to-Drain Charge 2.7
QG(TH) Gate Charge at Threshold 3.4
QOSS Output Charge VDS = 15 V, VGS = 0 V 29 44
QRR Source-Drain Recovery Charge 0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
Static Characteristics (TJ = 25°C unless otherwise stated)
DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Q1
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.3 mA 30 V
IDSS Drain-Source Leakage VDS = 24 V, VGS = 0 V 0.004 0.2 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.007 3 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.004 0.2 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 4 mA 0.8 1.3 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 6 8.2 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V
Q2
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 1 mA 30 V
IDSS Drain-Source Leakage VDS = 24 V, VGS = 0 V 0.015 0.8 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.03 9 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.015 0.8 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 16 mA 0.8 1.3 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 25 A 1.5 2.1 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.7 V
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RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
3.0 2.5 3.5 4.0 4.5
5.0
Figure 3b (Q2): RDS(on) vs. VGS for Various Drain Currents
ID = 15 A
ID = 25 A
ID = 35 A
ID = 50 A
6
5
4
3
2
1
0
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
3.0 2.5 3.5 4.0 4.5 5.0
Figure 3a (Q1): RDS(on) vs. VGS for Various Drain Currents
ID = 15 A
ID = 25 A
ID = 35 A
ID = 50 A
20
15
10
5
0
ID
–
Drain Current (A)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
25˚C
125˚C
VDS = 3 V
VGS – Gate-to-Source Voltage (V)
Figure 2a (Q1): Transfer Characteristics
25˚C
125˚C
VDS = 3 V
100
80
60
40
20
0
ID
–
Drain Current (A)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
25˚C
125˚C
VDS = 3 V
VGS – Gate-to-Source Voltage (V)
Figure 2b (Q2): Transfer Characteristics
25˚C
125˚C
VDS = 3 V
400
300
200
100
0
100
80
60
40
20
00 0.5 1.0 1.5 2.0 2.5 3.0
ID
–
Drain Current (A)
VDS – Drain-to-Source Voltage (V)
Figure 1a (Q1): Typical Output Characteristics at 25°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
400
300
200
100
00 0.5 1.0 1.5 2.0 2.5 3.0
ID
–
Drain Current (A)
VDS – Drain-to-Source Voltage (V)
Figure 1b (Q2): Typical Output Characteristics at 25°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
K L
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Capacitance (pF)
1000
100
10 0 5 10 15 20 25
30
Figure 5d (Q2): Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capacitance (pF)
Figure 5c (Q2): Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
3000
2500
2000
1500
1000
500
00 5 10 15 3020 25
Capacitance (pF)
0 5 10 2015 25 30
Figure 5a (Q1): Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
800
600
400
200
0
Capacitance (pF)
1000
100
10
10 5 10 15 3020 25
Figure 5b (Q1): Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
20
15
10
5
03.02.5 3.5 4.0 4.5 5.0
Figure 4a (Q1): RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 25 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
6
5
4
3
2
1
03.02.5 3.5 4.0 4.5 5.0
Figure 4b (Q2): RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 25 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 63 (01): Output (“3'99 and C s Stored Energy Figure 6b (02): Output (harge and C 5 Stored Energy Figure 8a (01): Reverse Drain-Sourte (haraderistics Figure 8b (01): Reverse Drain-Sourte (haraderistics
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Figure 6a: Output Charge and COSS Stored Energy
Q
OSS –
Output Charge (nC)
E
OSS –
C
OSS
Stored Energy (μJ)
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0 5 10 252015 30
V
DS
– Drain-to-Source Voltage (V)
Figure 6b (Q2): Output Charge and COSS Stored Energy
Figure 6a: Output Charge and COSS Stored Energy
QOSS – Output Charge (nC)
EOSS – COSS Stored Energy (μJ)
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0 5 10 15 20 25 30
VDS – Drain-to-Source Voltage (V)
Figure 6a (Q1): Output Charge and C
OSS
Stored Energy
12
10
8
6
4
2
0
0 5 10 15
Figure 7b (Q2): Gate Charge
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
ID = 25 A
VDS = 15 V
5
4
3
2
1
0
0 1 2 3 4
Figure 7a (Q1): Gate Charge
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
ID = 25 A
VDS = 15 V
5
4
3
2
1
0
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8a (Q1): Reverse Drain-Source Characteristics
100
80
60
40
20
0
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VGS = 0 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8b (Q2): Reverse Drain-Source Characteristics
400
300
200
100
0
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VGS = 0 V
Normalized Threshold Voltage Figure 9a (01): Figure 9b (02): Figure 10a (01): Figure 1% (02): /l Mormalixed Ihreshold Voluge /U on
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Figure 10b (Q2):
Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 16 mA
Figure 10a (Q1):
Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 4 mA
Figure 9a (Q1):
Normalized On-State Resistance vs. Temperature
ID = 25 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
Figure 9b (Q2):
Normalized On-State Resistance vs. Temperature
ID = 25 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
1000
100
10
1
0.1
0.1 1 10
ID – Drain Current (A)
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Limited by RDS(on)
100 ms
10 ms
1 ms
Pulse Width
1 ms
250 µs
100 µs
Figure 11a (Q1): Safe Operating Area
1000
100
10
1
0.1
0.1 1 10
100
ID – Drain Current (A)
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Limited by RDS(on)
100 ms
10 ms
1 ms
100 µs
Pulse Width
100 µs
10 µs
1 ms
250 µs
Figure 11b (Q2): Safe Operating Area
Junttion-lo-Board Hr Juntlion-lo-(ase —u—§E 3: 1H E}? ——
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tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.05
0.02
Single Pulse
0.01
0.1
0.2
Duty Cycle:
Junction-to-Board
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 101
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
0.1
0.02
0.05
Single Pulse
0.01
0.2
Duty Cycle:
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
Figure 12a
Transient Thermal
Response Curves
Figure 12b
Transient Thermal
Response Curves
Figure 13
Typical Application Circuit Gate driver/
controller
eGaNIC
GND
Gate 1
GR1
VIN
VIN+
+
_
_
VOUT
RLoad
PGND
VSW
Q1
Q2
Gate 2
VB
HO
VS
VCC
LO
eGaN® FET DATASHEET EPC2100
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2100
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
EPC2100 2100 YYYY ZZZZ
Die orientation dot
Gate bumps are along this edge of the die
DIE MARKINGS
TAPE AND REEL CONFIGURATION
4mm pitch, 12mm wide tape on 7” reel
7” reel
a
d e f g
c
b
EPC2100 (note 1)
Dimension (mm)
a
b
c (see note)
d
e
f (see note)
g
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die is placed into pocket
solder ball side down
(face side down)
Loaded Tape Feed Direction
target min max
12.00 11.70 12.30
1.75 1.65 1.85
5.50 5.45 5.55
4.00 3.90 4.10
4.00 3.90 4.10
2.00 1.95 2.05
1.50 1.50 1.60
2100
YYYY
ZZZZ
Die
orientation
dot
Gate bumps are along this edge of the die
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(625)
(785)
160+/−16
A
B
c
e
e
d
f
Seating plane
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED LAND PATTERN
(measurements in µm)
Pad 2 is Gate1 (high side); Pad 4 is Gate2 (low side);
Pad 3 is HS Gate Return;
Pads 5, 12, 13, 14, 15, 22, 23, 24, 25, 32, 33, 34, 35,
42, 43, 44, 45, 52, 53, 54, 55, 62, 63, 64, 65, 72, 73,
74, 75 are Ground;
Pads 1, 11, 21, 31, 41, 51, 61, 71 are VIN ;
Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29,
30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58,
59, 60, 66, 67, 68, 69, 70 are Switch Node
The land pattern is solder mask defined.
Suggest SMD Pads at 200 +20/–10 µm.
190 µm minimum.
DIE OUTLINE
Solder Bump View
Side View
DIM MIN Nominal MAX
A6020 6050 6080
B2270 2300 2330
c400 400 400
d450 450 450
e210 225 240
f187 208 240
RECOMMENDED STENCIL DRAWING
(measurements in µm)
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
Additional assembly resources available at:
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
6050
2300
400
450
5
3
1
10
8
6
15
13
11
20
18
16
25
23
21
30
28
26
35
33
31
38 43 48 53 58 63 68
36 41 46 51 56 61 66 71
2 7 12 17 22 27 32 37 42 47 52 57 62 67 72
73
4 9 14 19 24 29 34 39 44 49 54 59 64 69 74
40 45 50 55 60 65 70 75
6050
2300
400
225
275
450
Information subject to
change without notice.
Revised August 2019