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ANALOG DEVICES LTC2645 Lil—IL"; Uf—LT

LTC2645

Rev. B

For more information www.analog.com

TYPICAL APPLICATION

FEATURES DESCRIPTION

Quad 12-/10-/8-Bit PWM to VOUT

DACs with 10ppm/°C Reference

The LTC

2645 is a family of quad 12-, 10-, and 8-bit

PWM-to-voltage output DACs with an integrated high

accuracy, low drift, 10ppm/°C reference in a 16-lead

MSOP package. It has rail-to-rail output buffers and is

guaranteed monotonic.

The LTC2645 measures the period and pulse width of the

PWM input signals and updates the voltage output DACs

after each corresponding PWM input rising edge. The DAC

outputs update and settle to 12-bit accuracy within 8µs

typically and are capable of sourcing and sinking up to

5mA (3V) or 10mA (5V), eliminating voltage ripple and

replacing slow analog filters and buffer amplifiers.

The LTC2645 has a full-scale output of 2.5V using the

10ppm/°C internal reference. It can operate with an exter

nal reference, which sets the full-scale output equal to the

external reference voltage. Each DAC enters a pin-select-

able idle state when the PWM input is held unchanged for

more than 60ms. The part operates from a single 2.7V

to 5.5V supply and supports PWM input voltages from

1.71V to 5.5V.

PWM Input to DAC Output

4-Channel PWM to Voltage Output DAC

APPLICATIONS

n Digital Calibration

n Trimming and Adjustment

n Level Setting

n Process Control and Industrial Automation

n Instrumentation

n Automotive

n No Latency PWM-to-Voltage Conversion

n Voltage Output Updates and Settles within 8µs

n 100kHz to 30Hz PWM Input Frequency

n ±2.5LSB Max INL; ±1LSB Max DNL (LTC2645-12)

n Guaranteed Monotonic

n Pin-Selectable Internal or External Reference

n 2.7V to 5.5V Supply Range

n 1.71V to 5.5V Input Voltage Range

n Low Power: 4mA at 3V, <1µA Power-Down

n Guaranteed Operation from –40°C to 125°C

n 16-Lead MSOP Package

20µs/DIV TA01b

VOUTA

500mV/DIV

INA

2V/DIV

LTC2645

PWM INPUTS

INA

INB

INC

IND

BUFFERED

VOLTAGE

OUTPUTS

GND

0.1µF

1.7V TO 5.5V

2.7V TO 5.5V

IOVCC

VOUTA

VOUTB

VOUTC

VOUTD

GND

IDLSEL

REFSEL

REF

VCC

2645 TA01a

0.1µF

INPUT: 1V TO 5.5V

OUTPUT: 1.25V

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 5396245, 5859606, 6891433, 6937178, 7414561.

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LTC2645

Rev. B

For more information www.analog.com

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

VCC

VOUTA

VOUTB

IDLSEL

INB

INA

IOVCC

GND

VOUTD

VOUTC

REFSEL

REF

INC

IND

TOP VIEW

MS PACKAGE

16-LEAD PLASTIC MSOP

(4mm × 4.9mm)

TJMAX = 150°C, θJA = 120°C/W

Supply Voltages (VCC, IOVCC) ...................... –0.3V to 6V

INA, INB, INC, IND ......................................... –0.3V to 6V

IDLSEL, PD, REFSEL .................................... –0.3V to 6V

VOUTA, VOUTB, VOUTC,

VOUTD ............................... –0.3V to Min (VCC + 0.3V, 6V)

REF ..................................–0.3V to Min (VCC + 0.3V, 6V)

Operating Temperature Range

LTC2645C ................................................ 0°C to 70°C

LTC2645I .............................................–40°C to 85°C

LTC2645H .......................................... –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

L E

LTC2645

Rev. B

For more information www.analog.com

ORDER INFORMATION

LTC2645 C MS –L 12 #TR PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

PACKAGE TYPE

MS = 16-Lead MSOP

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

PRODUCT SELECTION GUIDE

PART NUMBER PART MARKING* RESOLUTION CHANNELS

VFS WITH INTERNAL

REFERENCE MAXIMUM INL PACKAGE DESCRIPTION

LTC2645-L12

LTC2645-L10

LTC2645-L8

645L12

645L10

2645L8

12-Bit

10-Bit

8-Bit

2.5V

±2.5LSB

±1.0LSB

±0.5LSB

16-Lead Plastic MSOP

*Temperature grades are identified by a label on the shipping container.

LTC2645

Rev. B

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span External Reference

Internal Reference

0 to VREF

0 to 2.5

PSR Power Supply Rejection VCC = 3V ±10% or 5V ±10% –80 dB

ISC Short Circuit Output Current (Note 5)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero-Scale; VOUT Shorted to VCC

Full-Scale; VOUT Shorted to GND

–28

–48

Power Supply

VCC Positive Supply Voltage For Specified Performance l2.7 5.5 V

IOVCC Digital Input Supply Voltage For Specified Performance l1.71 5.5

ICC Supply Current (Note 6) VCC = 3V, Internal Reference

VCC = 5V, Internal Reference

6.4

ICC(IOVCC) Supply Current, IOVCC (Note 6) IOVCC = 5V l25 50 µA

ISD Supply Current in Power-Down Mode (Note 6) VCC = 5V, PD = 0V l0.5 5 µA

ISD(IOVCC) Supply Current in Power-Down Mode, IOVCC

(Note 6)

IOVCC = 5V, PD = 0V l0.5 5 µA

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

SYMBOL

PARAMETER CONDITIONS

LTC2645-L8 LTC2645-L10 LTC2645-L12

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

DC Performance

Resolution l8 10 12 Bits

Monotonicity VCC = 3V, Internal Ref. (Note 3) l8 10 12 Bits

DNL Differential

Nonlinearity

VCC = 3V, Internal Ref. (Note 3) l±0.5 ±0.5 ±1 LSB

INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 3) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB

ZSE Zero-Scale Error VCC = 3V, Internal Ref., Code = 0 l0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 3V, Internal Ref. (Note 4) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefficient

VCC = 3V, Internal Ref. (Note 9) ±10 ±10 ±10 µV/°C

GE Gain Error VCC = 3V, Internal Ref. l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

GETC Gain Temperature

Coefficient

VCC = 3V, Internal Ref. (Note 9)

C-grade

I-grade

H-grade

ppm/°C

Load Regulation Internal Ref., Mid-Scale,

VCC = 3V ±10%,

–5mA ≤ IOUT ≤ 5mA

l0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA

VCC = 5V ±10%,

–10mA ≤ IOUT ≤ 10mA

l0.009 0.016 0.035 0.064 0.14 0.256 LSB/mA

ROUT DC Output

Impedance

Internal Ref., Mid-Scale,

VCC = 3V ±10%,

–5mA ≤ IOUT ≤ 5mA

l0.09 0.156 0.09 0.156 0.09 0.156 Ω

VCC = 5V ±10%,

–10mA ≤ IOUT ≤ 10mA

l0.09 0.156 0.09 0.156 0.09 0.156 Ω

LTC2645-L12/-L10/-L8 (VFS = 2.5V)

LTC2645

Rev. B

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Input

VREF Input Voltage Range l1 VCC V

Resistance l120 160 200 kΩ

Capacitance 7.5 pF

IREF Reference Current, Power-Down Mode DAC Powered Down l0.005 1.5 µA

Reference Output

Output Voltage l1.24 1.25 1.26 V

Reference Temperature Coefficient (Note 9) ±10 ppm/°C

Output Impedance 0.5 kΩ

Capacitive Load Driving 10 µF

Short Circuit Current VCC = 5.5V, REF Shorted to GND 2.5 mA

Digital Inputs (INA, INB, INC, IND, PD)

VIH Digital Input High Voltage l0.8•IOVCC V

VIL Digital Input Low Voltage l0.5 V

ILK Digital Input Leakage INA/INB/INC/IND = GND to IOVCC l±1 µA

CIN Digital Input Capacitance (Note 7) l5 pF

AC Performance

tsSettling Time From INA/INB/INC/IND Rising Edge

(Note 8)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

7.0

7.4

7.8

µs

Voltage Output Slew Rate 1.0 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 2.1 nV • s

DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switched 0 to FS 0.9 nV • s

Multiplying Bandwidth External Reference 320 kHz

enOutput Voltage Noise Density At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

200

180

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

CREF = 0.1µF

680

730

µVP-P

LTC2645-L12/-L10/-L8 (VFS = 2.5V)

LTC2645

Rev. B

For more information www.analog.com

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages with respect to GND.

Note 3: Linearity and monotonicity are defined from code 16 to code 4095

(LTC2645-12), code 4 to code 1023 (LTC2645-10) or code 1 to code 255

(LTC2645-8).

Note 4: Inferred from measurement at code 16 (LTC2645-12), code 4

(LTC2645-10) or code 1 (LTC2645-8), and at full-scale.

Note 5: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the specified maximum operating junction temperature may impair

device reliability.

Note 6: INx at 0V or IOVCC.

Note 7: Guaranteed by design and not production tested.

Note 8: Internal Reference mode. DAC is stepped ¼ scale to ¾ scale and

¾ scale to ¼ scale. Load is 2kΩ in parallel with 100pF to GND.

Note 9: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tPWH INA/INB/INC/IND High Time l25 ns

tPWL INA/INB/INC/IND Low Time l25 ns

tPER INA/INB/INC/IND Rising Edge to Rising Edge

Period

LTC2645-L12 l0.160 33 ms

LTC2645-L10 l0.040 33 ms

LTC2645-L8 l0.010 33 ms

t3INA/INB/INC/IND Idle Mode Timeout l50 70 ms

t4INA/INB/INC/IND Rising Edge to DAC Update

Delay

3.2 µs

fMAX INA/INB/INC/IND Frequency LTC2645-L12 l0.03 6.25 kHz

LTC2645-L10 l0.03 25 kHz

LTC2645-L8 l0.03 100 kHz

LTC2645-L12/-L10/-L8 (VFS = 2.5V)

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2645 m:

LTC2645

Rev. B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

DNL vs Temperature

Reference Output Voltage

vs Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL vs Temperature

TEMPERATURE (°C)

–50

INL (LSB)

0.5

1.0

25 500 75 100

2645 G03

–25 125

–0.5

–1.0

VCC = 3V

INL = (POS)

INL = (NEG)

TEMPERATURE (°C)

–50

DNL (LSB)

0.5

1.0

25 500 75 100

2645 G04

–25 125

–0.5

–1.0

VCC = 3V

DNL = (POS)

DNL = (NEG)

(TA = 25°C, unless otherwise noted.)

LTC2645-12 (Internal Reference, VFS = 2.5V)

TEMPERATURE (°C)

–50

VREF (V)

1.255

1.260

25 500 75 100

2645 G05

1.250

–25 125

1.245

1.240

VCC = 3V

2µs/DIV 2645 G06

INX

5V/DIV

VOUTX

1LSB/DIV

1/4 SCALE TO

3/4 SCALE STEP

VCC = 5V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

7µs

2µs/DIV 2645 G07

VOUTX

1LSB/DIV

3/4 SCALE TO

1/4 SCALE STEP

VCC = 5V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256

EVENTS

7.8µs

INX

5V/DIV

DUTY CYCLE (%)

INL (LSB)

0.5

1.0

50 75

2645 G01

25 100

–0.5

–1.0

VCC = 3V

tPER = 200µs

INTERNAL REFERENCE

DUTY CYCLE (%)

DNL (LSB)

0.5

1.0

50 75

2645 G02

25 100

–0.5

–1.0

VCC = 3V

tPER = 200µs

INTERNAL REFERENCE

LTC2645

Rev. B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL)

LTC2645-10 (Internal Reference, VFS = 2.5V)

LTC2645-8 (Internal Reference, VFS = 2.5V)

LTC2645

Differential Nonlinearity (DNL)

Load Regulation Current Limiting Offset Error vs Temperature

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

25 50 75 100 1250–25–50

TEMPERATURE (°C)

2645 G14

–1

–2

–3

OFFSET ERROR (mV)

DUTY CYCLE (%)

INL (LSB)

0.5

1.0

50 75

2645 G08

25 100

–0.5

–1.0

VCC = 3V

tPER = 50µs

INTERNAL REFERENCE

DUTY CYCLE (%)

DNL (LSB)

0.5

1.0

50 75

2645 G09

25 100

–0.5

–1.0

VCC = 3V

tPER = 50µs

INTERNAL REFERENCE

DUTY CYCLE (%)

INL (LSB)

0.5

1.0

50 75

2645 G10

25 100

–0.5

–1.0

VCC = 3V

tPER = 10µs

INTERNAL REFERENCE

DUTY CYCLE (%)

DNL (LSB)

0.5

1.0

50 75

2645 G11

25 100

–0.5

–1.0

VCC = 3V

tPER = 10µs

INTERNAL REFERENCE

0 10 20 30–10–20–30

IOUT (mA)

2645 G12

–2

–4

–6

–8

–10

VCC = 5V

VCC = 3V

INTERNAL REF.

CODE = MID-SCALE

∆VOUT (mV)

0 10 20 30–10–20–30

IOUT (mA)

2645 G13

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

VCC = 5V

VCC = 3V

INTERNAL REF.

CODE = MID-SCALE

∆VOUT (mV)

(TA = 25°C, unless otherwise noted.)

LTC2645 wﬁffl _T_"_’Il __,_/:

LTC2645

Rev. B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

Entering Idle Mode Full-Scale

From Mid-Scale (IDLSEL = GND)

Exiting Idle Mode Zero-Scale

to Mid-Scale (IDLSEL = GND)

Exiting Idle Mode Full-Scale

to Mid-Scale (IDLSEL = GND)

Exiting Idle Mode Power-Down

(1 Channel) to Mid-Scale

(IDLSEL = VCC)

Power-On-Reset to Idle Mode

Full-Scale (IDLSEL = GND)

Large-Signal Response

INX to VOUTX Delay

Full-Scale Transition

Entering Idle Mode Zero-Scale

from Mid-Scale (IDLSEL = GND)

(TA = 25°C, unless otherwise noted.)

(Internal Reference, VFS = 2.5V)

2µs/DIV 2645 G15

VOUTX

0.5V/DIV

VFS = VREF = VCC = 5V

1/4 SCALE TO 3/4 SCALE

2µs/DIV 2645 G16

INA

2/DIV

VOUTA

500mV/DIV

10ms/DIV 2645 G17

INA

2V/DIV

VOUTA

500mV/DIV

1ms/DIV 2645 G19

INA

2V/DIV

VOUTA

500mV/DIV

500µs/DIV 2645 G21

INA

2V/DIV

VOUTA

500mV/DIV

VREF

1V/DIV

10ms/DIV 2645 G22

VCC

2V/DIV

INA

2V/DIV

VOUTA

2V/DIV

VREF

1V/DIV

10ms/DIV 2645 G18

INA

2V/DIV

VOUTA

500mV/DIV

1ms/DIV 2645 G20

INA

2V/DIV

VOUTA

500mV/DIV

LTC2645 ‘IO

LTC2645

Rev. B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

Multiplying Bandwidth Gain Error vs Reference Input Gain Error vs Temperature

Headroom at Rails vs

Output Current Noise Voltage vs Frequency DAC-to-DAC Crosstalk (Dynamic)

Supply Current vs Input Period

(tPER)

Supply Current vs Duty Cycle

(tPW/tPER) Mid-Scale Glitch Impulse

100 1k101 10k 100k

PERIOD (µs)

ICC (mA)

2645 G23

VCC = 3V

VCC = 5V

LTC2645-12

DUTY CYCLE = 50%

4-CHANNELS ACTIVE

50 75 100250

DUTY CYCLE (%)

2645 G24

4.50

4.25

4.00

3.75

3.50

LTC2645-12

VCC = 3V, IDLSEL = 0V

4-CHANNELS ACTIVE

ICC (mA)

tPER = 20ms

tPER = 200µs

1k 10k 100k 1M

FREQUENCY (Hz)

2645 G26

–2

–4

–6

–8

–10

–12

–14

–16

–18

VCC = 5V

VREF(DC) = 2V

VREF(AC) = 0.2VP-P

CODE = FULL SCALE

1 2.521.5 4 4.5 53 3.5 5.5

REFERENCE VOLTAGE (V)

GAIN ERROR (%FSR)

2645 G27

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

VCC = 5.5V

GAIN ERROR OF 4 CHANNELS

–50 0–25 75 10025 50 125

TEMPERATURE (°C)

GAIN ERROR (%FSR)

2645 G28

1.0

0.5

–0.5

–1.0

0 1 2 3 4 5 6 97 8 10

IOUT (mA)

VOUT (V)

2645 G29

5.0

4.5

4.0

3.5

3.0

2.0

1.5

1.0

2.5

0.5

3V SOURCING

5V SINKING

3V SINKING

5V SOURCING

100 1k 10k 100k 1M

FREQUENCY (Hz)

NOISE VOLTAGE (nV/√Hz)

2645 G30

500

400

300

200

100

VCC = 5V

CODE = MID-SCALE

INTERNAL REF

2µs/DIV 2645 G31

INA/INB/INC

5V/DIV

DACs A-C

SWITCH 0-FS

2V/DIV

VOUTD

1mV/DIV

LTC2645-12, VCC = 5V

VREF = 2.5V

0.9nV-s TYP

(TA = 25°C, unless otherwise noted.)

(Internal Reference, VFS = 2.5V)

2µs/DIV 2645 G25

VOUTX

5mV/DIV

INX

5V/DIV

LTC2645-12

VCC = 5V

2.1nV • s TYPICAL

LTC2645 ‘I‘I

LTC2645

Rev. B

For more information www.analog.com

PIN FUNCTIONS

VCC (Pin 1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

Bypass to GND with a 0.1µF capacitor.

, IN

(Pins 6, 5, 11, 10): PWM Inputs. Apply

a pulse-width modulated input frequency between 30Hz

and 6.25kHz (12-bit), 25kHz (10-bit) or 100kHz (8-bit).

After each INX rising edge, the part calculates the duty

cycle based upon the pulse width and period and updates

DAC channel V

OUTX

. Logic levels are referenced to IOV

IOVCC (Pin 7): I/O Supply Voltage Input. 1.71V ≤ IOVCC ≤

5.5V. Bypass to GND with a 0.1µF capacitor.

IDLSEL (Pin 4): Idle Mode Select Input. Connect IDLSEL

to GND or VCC to select the behavior of the DAC output

when there has been no rising edge on the PWM input for

more than the idle mode timeout delay t3 (nominal delay

is 60ms). Available idle mode states are power-down with

high impedance output, hold previous state, zero-scale or

full-scale. This pin also selects the initial state of the DAC

outputs following a power-on reset.

PD (Pin 9): Active-Low Power-Down Input. Connect PD to

GND to place the part in power-down with a typical supply

current of <1µA. Connect PD to IOVCC for normal operation.

REFSEL (Pin 13): Reference Select Input. Connect REFSEL

to GND to select internal reference mode. Connect REFSEL

to VCC to select external reference mode.

REF (Pin 12): Reference Voltage Input or Output. When

REFSEL is connected to VCC, REF is an input (1V ≤ VREF

≤ VCC) where the voltage supplied sets the full-scale DAC

output voltage. When REFSEL is connected to GND, the

10ppm/°C, 1.25V internal reference (half full-scale) is

available at the pin. This output may be bypassed to GND

with up to 10µF and must be buffered when driving exter-

nal DC load current.

VOUTA, VOUTB, VOUTC, VOUTD (Pins 2, 3, 14, 15): DAC

Analog Voltage Outputs. The DAC output voltage can be

calculated by the following equation:

VOUTX = VREF • tPWHX/tPERX

where VREF is 2.5V in internal reference mode or the REF

pin voltage in external reference mode, tPWHX is the pulse

width of the preceding INX period and tPERX is the time

between the two most recent INX rising edges.

GND (Pins 8, 16): Ground.

BLOCK DIAGRAM

2645 BD

PWM TO BINARY

CONVERSION

INTERNAL REFERENCE

PWM TO BINARY

CONVERSION

PWM TO BINARY

CONVERSION

PWM TO BINARY

CONVERSION

DAC A

VREF

DAC B

DAC C

DAC D VOUTD

VOUTC

VOUTB

INB

INA

IDLSEL

IOVCC

INC

IND

GND

VOUTA

VCC

REFSEL

REF

GND

SWITCH

LTC2645 12

LTC2645

Rev. B

For more information www.analog.com

TIMING DIAGRAMS

(a)

(b) Sample/Hold Operation (IDLSEL = VCC)

Figure1.

2645 TD01a

tPER t3

tPWL

VOUT = (tPWH/tPER) • VREF

tPWH

IDLE STATE

INX

VOUTX

2645 TD01b

tPER1

tPWL < t3

tHOLD1 > t3

tPWH2

tPER2

tPWH1

SAMPLE #1 HOLD #1

VOUT1 = (tPWH1/tPER1)*VREF

VOUT2 = (tPWH2/tPER2)*VREF

SAMPLE #2 HOLD #2

INX

VOUTX

2645 TD01c

tPER1 tIDLE(LOW) ≥ t3tPER2 tIDLE(HIGH) ≥ t3

tPWH1 tPWH2

SAMPLE #1

VOUT1 = (tPWH1/tPER1) • VREF VOUT2 = (tPWH2/tPER2) • VREF

VOUT = GND

IDLE STATE

TIMEOUT

LOW

IDLE STATE

TIMEOUT

HIGH

VOUT = VREF

SAMPLE #2

INX

VOUTX

t4t4

LTC2645 13

LTC2645

Rev. B

For more information www.analog.com

OPERATION

The LTC2645 is a family of quad PWM input, voltage

output DACs in a 16-lead MSOP package. The part mea-

sures the pulse width and period of the PWM inputs and

updates each DAC output after the corresponding PWM

input rising edge. Each DAC can operate rail-to-rail using

an external reference, or with a 2.5V full-scale voltage

using an integrated reference. Three resolutions (12-, 10-,

and 8-bit) are available.

PWM-to-Voltage Conversion

The LTC2645 converts a PWM input to an accurate, sta-

ble, buffered voltage without the latency, slow settling,

and high-value passive components required for discrete

solutions. The PWM input pins (INX) accept frequencies

from 30Hz up to 6.25kHz (12-bit), 25kHz (10-bit), or

100kHz (8-bit).

The duty cycle is calculated after each PWM input rising

edge based upon the previous high and low pulse width.

The resulting digital DAC code k is calculated as:

k = 2N • tPWHX / tPERX

where t

PWHX

is the pulse width of the preceding IN

period

and tPERX is the time between the two most recent INX

rising edges. The digital-to-analog transfer function is:

VOUT(IDEAL) =k

⎛

⎝

⎜⎞

⎠

⎟VREF, for k = 0 to 2N–

where N is the resolution, VREF is 2.5V for internal reference

mode or the REF pin voltage for external referencemode.

DAC Update Timing

The update for DAC output VOUTX occurs following each

rising edge input on INX (Figure1a). Delay tS is the delay

from an INX rising edge to the VOUTX settled output volt-

age corresponding to the previous period’s duty cycle.

Delay tS is composed of the computational cycle delay (t4)

and the actual settling of the output DAC. The PWM-to-

binary, internal computational cycle begins immediately

following the IN

rising edge. The computational cycle

is completed after delay t4 and the DAC output VOUTX is

updated. The DAC output typically settles to 12-bit accu-

racy within 8µs from the INX rising edge.

PWM Input Idle Mode Selection

When no PWM input rising edge is received for more than

the idle mode timeout delay t3 (nominal delay is 60ms),

the DAC output enters an idle mode state which can be

configured by connecting IDLSEL to GND or VCC accord-

ing to Table 1 below. Note that these pins also control the

initial state of the DACs after power-on reset.

Table1. Power-On Reset and Idle Mode States

IDLSEL POWER-ON RESET INX IDLE LOW INX IDLE HI

GND Zero-Scale Zero-Scale Full-Scale

VCC Power-Down Hi-Z Power-Down Hi-Z Hold

Transparent Operation

For applications in which the PWM input duty cycle may

be 0% or 100%, connect IDLSEL to GND to select trans-

parent operation, in which case an idle low input sets the

DAC to zero-scale or an idle high input sets the DAC to

full-scale. Figure1c illustrates the timing for transparent

operation. Any pair of PWM input rising edges separated

by less than the idle mode timeout delay t3 (50ms mini-

mum) will cause the DAC code to be updated following

the second rising edge. Note that an idle high input state

may be followed by an idle low input state.

Sample/Hold Operation

The LTC2645 has the capability to sample the pulse-

width/period and hold the corresponding voltage level

indefinitely. Unlike analog filter implementations which

require the PWM input to run continuously, the LTC2645

may operate with a discontinuous PWM input. Connect

IDLSEL to VCC to select sample/hold operation, in which

a single pair of rising edges is sufficient to update the

DAC, and the DAC code retains its previous value when

LTC2645 14

LTC2645

Rev. B

For more information www.analog.com

OPERATION

the PWM input idles high. Figure1b illustrates correct

timing for sample/hold operations. Any pair of rising

edgesseparated by less than the idle timeout delay t

(50ms minimum) will cause the DAC code to be updated.

Any pair of rising edges separated by more than t3 (70ms

maximum) will be ignored and the DAC code will retain

its previous value. Note that after power-on-reset or when

INX idles low, the DAC will power down with a high imped

ance output.

Short INX Period Operation

The accuracy of the PWM to voltage conversion is guar-

anteed for INX input frequencies up to 6.25 kHz (12-bit),

25kHz (10-bit) or 100kHz (8-bit). Faster INX input fre-

quencies will proportionally decrease the resolution and

accuracy of the analog output. For INX input periods of

less than the computational delay t4 (nominally 3.2µs), the

DAC update will be skipped and the DAC code will retain

its previous value.

Short INX Pulse-Width Operation

Provide INX input high and low pulse widths greater than

tPWH and tPWL to ensure that the DAC output is updated

after every INX rising edge. High going pulses narrower

than t

PWH

will cause the DAC code to be calculated as

zero-scale, and low going pulses narrower than tPWL will

cause the DAC code to be calculated as full-scale. For

much narrower pulse widths of only a few nanoseconds,

the input edge may not be recognized, in which case the

DAC update will be skipped entirely and the DAC code will

retain its previous value.

Power-On Reset

The LTC2645 resets the output to a known state when

power is first applied, making system initialization con-

sistent and repeatable. Connect the IDLSEL pin to GND or

VCC according to Table 1 to cause the DACs to initialize to

zero-scale or with the device powered down and the DAC

outputs high impedance.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2645 con-

tains circuitry to reduce the power-on glitch when zero-

scale reset is selected: the analog output typically rises

less than 5mV above zero-scale during power on if the

power supply is ramped to 5V in 1ms or more. In general,

the glitch amplitude decreases as the power supply ramp

time is increased.

Reference Modes

For applications where an accurate external reference

is not available, nor desirable due to limited space, the

LTC2645 has a user-selectable, integrated reference.

Internal Reference mode can be selected by connecting

the REFSEL pin to GND.

The 10ppm/°C, 1.25V internal reference is available at the

REF pin. This voltage is internally amplified by 2× to pro-

vide a 2.5V full-scale DAC output voltage range. Adding

bypass capacitance to the REF pin will improve noise per-

formance; 0.1µF is recommended, and up to 10µF can

be driven without oscillation. The REF output must be

buffered when driving an external DC load current.

Alternatively, the DAC can operate in External Reference

mode by connecting the REFSEL pin to VCC. In this mode,

an input voltage supplied externally to the REF pin pro-

vides the reference (1V ≤ VREF ≤ VCC) and the supply

current is reduced. In this mode the full-scale DAC output

voltage is equal to the voltage at the REF pin.

Power-Down Mode

For power constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four DAC outputs are needed. When in power-down

mode, the buffer amplifiers, bias circuits, and integrated

reference circuits are disabled, and draw essentially

zerocurrent.

LTC2645 15

LTC2645

Rev. B

For more information www.analog.com

OPERATION

If IDLSEL is connected to VCC, any channel or all chan-

nels can be powered down by keeping the PWM input(s)

(INA/INB/INC/IND) low for the idle mode timeout delay t3.

The integrated reference is automatically powered down

when external reference mode is selected or when all DAC

channels are powered down. In addition, all the DAC chan-

nels and the integrated reference can be powered down

by pulling the PD pin low. When the integrated reference

is powered down, the REF pin becomes high impedance

(typically > 1GΩ).

Normal operating current resumes when PD returns high

for transparent operation (IDLSEL = GND). For sample/

hold operation (IDLSEL = VCC), the LTC2645 remains

in full power-down until the first rising edge is received

on any PWM input. Any pair of PWM input rising edges

separated by less than the idle mode timeout delay t3

(50ms minimum) will cause the DAC code to be updated.

The DAC output(s) will remain in Hi-Z until the channel

is updated following the second rising PWM input edge.

Voltage Output

The LTC2645’s integrated rail-to-rail amplifier has guar-

anteed load regulation when sourcing or sinking up to

10mA at 5V, and 5mA at 3V.

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change

in units from LSB/mA to Ω. The amplifier’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage

is 50Ω • 1mA, or 50mV). See the graph Headroom at

Rails vs Output Current in the Typical Performance

Characteristicssection.

The amplifier is stable driving capacitive loads of up

to500pF.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is lim-

ited to voltages within the supply range.

Since the analog output of the DAC cannot go below

ground, it may limit the lowest codes reachable as shown

in Figure2b. Similarly, limiting can occur near full-scale

when the REF pin is tied to V

. If V

REF

= V

and the DAC

full-scale error (FSE) is positive, the output for the highest

codes limits at VCC, as shown in Figure2c. No full-scale

limiting will occur if VREF is less than VCC–FSE.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting

canoccur.

Board Layout

The PC board should have separate areas for the analog

and digital sections of the circuit. A single, solid ground

plane should be used, with analog and digital signals care-

fully routed over separate areas of the plane. This keeps

digital signals away from sensitive analog signals and

minimizes the interaction between digital ground currents

and the analog section of the ground plane. The resistance

from the LTC2645 GND pin to the ground plane should

be as low as possible. Resistance here will add directly to

the effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2645 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

LTC2645 16 Tn) mu nl u

LTC2645

Rev. B

For more information www.analog.com

OPERATION

Figure2. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12 Bits)

2645 F02

INPUT CODE

(b) Effect of Negative Offset for Codes Near Zero

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V 20480 4095

INPUT CODE

OUTPUT

VOLTAGE

(a) Overall Transfer Function

VREF = VCC

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2645 is sinking large currents, this current flows

out of the ground pin and directly into the power ground

trace without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to confine digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

LTC2645 17

LTC2645

Rev. B

For more information www.analog.com

TYPICAL APPLICATIONS

Figure3. Analog Control Voltage with PWM Transmission to DAC Control Voltage Output

2645 F03

PWM TO

BINARY

LTC2645 -12

ISOLATION BARRIER

PS9851-1

PWM TO

BINARY

PWM TO

BINARY

PWM TO

BINARY

DAC A

REFIOVCC VCC IDLSEL REFSEL

DAC B

DAC C

DAC D VOUTD

VOUTC

VOUTB VOUTB = Hi-Z

VOUTC = Hi-Z

VOUTD = Hi-Z

GND

VOUTA DAC CONTROL

VOLTAGE OUTPUT

(0V TO VREF)

IND

INC

INB

INA

2.7V TO 5.5V

EXT INPUT: 1V TO VCC

0.1µF

LTC6992

RSET

50k

2.25V TO 5.5V

MOD

ANALOG PWM

DUTY CYCLE

CONTROL

(0V TO 1V)

OUT

GND V+

SET DIV

0.1µF

LTC2645 mnnnnnnnﬂ (52m) 3207345 “26436) l LEIEIEIEIEIWT +7» EEEEEEW 4 W + if :Eﬁ if ,7Eguumuu ' (M rm; ”:1 ‘u I 7 18

LTC2645

Rev. B

For more information www.analog.com

PACKAGE DESCRIPTION

MSOP (MS16) 0213 REV A

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16151413121110

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ±0.038

(.0120 ±.0015)

TYP

0.50

(.0197)

BSC

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.1016 ±0.0508

(.004 ±.002)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.280 ±0.076

(.011 ±.003)

REF

4.90 ±0.152

(.193 ±.006)

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

LTC2645 19

LTC2645

Rev. B

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 02/17 Corrected VOUT(IDEAL) equation 13

B 11/18 Corrected Units of Output Voltage Noise 5

LTC2645 20 SEGLé’ES

LTC2645

Rev. B

For more information www.analog.com

 ANALOG DEVICES, INC. 2014-2018

11/18

www.analog.com

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

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10ppm°/C Reference

Zero Latency Bus Update, 100kHz to 30Hz Input Frequency, ±2.5LSB INL, 2.7V to

5.5V Supply Range, 12-Lead MSOP Package

1991 Precision, 100µA Gain Selectable Amplifier Gain Accuracy of 0.04%, Gains from –13 to 14, 100µA Precision Op Amp

LT1469-2 Dual 200MHz, 30V/µs 16-Bit Accurate Op Amp 200MHz Gain Bandwidth, 125µV Offset, 30V/µs Slew Rate Precision Op Amp

LTC2055 Dual Micropower Zero-Drift Op Amp 2.7V Minimum Supply Voltage, 150µA Supply Current per Amplifier, Zero-Drift

Op Amp

LTC6992 Timer Blox: Voltage-Controlled Pulse Width

Modulator (PWM)

3.8Hz to 1MHz Output Frequency Range, 0V to 1V Analog Input, < 1.7% Maximum

Frequency Error

LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C VOUT DACs with

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16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages

Figure4. Voltage Margining Application with LTC3850 (3.3V ±10%)

SW1

BG1

PGND

ITH1 SENSE1+

MODE/PLLIN RUN1

SENSE1–

VFB1

500kHz

TKSS1

ILM

VIN INTVCC

PGOOD

TG1

0.1µF

1nF

0.1µF

2.2k 100k

10k

SGND

10k

0.008k2.2µH

LTC3850EUF

2645 F04

FREQ

BOOST1

0.1µF

CMDSH-3

RJK0305DPB

RJK0301DPB

10nF

1nF 3.32k

10k

1nF

10k

100pF

4.7µF

VIN

6.5V

TO 14V

VOUT

3.3V ±10%

20k

15pF 63.4k

0.1µF

PWM TO

BINARY

LTC2645 -12

PWM TO

BINARY

PWM TO

BINARY

PWM TO

BINARY

DAC A

REFIOVCC VCC IDLSEL REFSEL

DAC B

DAC C

FOR NO MARGINING, KEEP INA LOW. (VOUTA = Hi-Z)

TO MARGIN 10% HIGH, SET INA DUTY CYCLE TO 1/4096. (VOUTA = 0V)

TO MARGIN 10% LOW, SET INA DUTY CYCLE TO 2621/4096. (VOUTA = 1.6V)

DAC D VOUTD

VOUTC

VOUTB VOUTB = Hi-Z

VOUTC = Hi-Z

VOUTD = Hi-Z

GND

VOUTA

IND

INC

INB

INA

0.1µF

10k 143k

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