Analog Devices Inc. 的 LTC4232IDHC-1 规格书

L7 LINE I “2 LTC4232-1 TECHNOLOGY mnk W VFW-HS L7 LJUW 1
LTC4232-1
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Typical applicaTion
FeaTures
applicaTions
DescripTion
5A Integrated Hot Swap
Controller
The LT C
®
4232-1 is an integrated solution for Hot Swap
applications that allows a board to be safely inserted and
removed from a live backplane. The part integrates a Hot
Swap controller, power MOSFET and current sense resis-
tor in a single package for small form factor applications.
The LTC4232-1 provides separate inrush current control
and a 10% accurate 5A current limit with foldback cur-
rent limiting. The current limit threshold can be adjusted
dynamically using an external pin. Additional features
include a current monitor output that amplifies the sense
resistor voltage for ground referenced current sensing
and a MOSFET temperature monitor output. Thermal limit,
overvoltage, undervoltage and power good monitoring
are also provided.
The PCI Express compliant LTC4232-1 allows faster turn-on
than the LTC4232 by providing a shorter (16ms) debounce
delay and external control of the GATE ramp rate.
12V, 5A Card Resident Application with Auto-Retry
n Reduced 16ms Turn-On Delay
n Small Footprint
n 33mΩ MOSFET with RSENSE
n Wide Operating Voltage Range: 2.9V to 15V
n Adjustable, 10% Accurate Current Limit
n Current and Temperature Monitor Outputs
n Overtemperature Protection
n Adjustable Current Limit Timer Before Fault
n Power Good and Fault Outputs
n Adjustable Inrush Current Control
n 2% Accurate Undervoltage and Overvoltage Protection
n Pin Compatible with LTC4217 (DFN Package Only)
n Available in 16-Lead 5mm × 3mm DFN Package
n RAID Systems, Solid State Drives
n Server I/O Cards
n PCI Express Systems
n Industrial
Power-Up Waveforms
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation and PowerPath is a trademark of Linear Technology Corporation. All
other trademarks are the property of their respective owners.
12V
VOUT
12V
5A
42321 TA01a
150µF
10k
VDD
ISET
TIMER
UV
INTVCC
OUT
FB
PG
GND
GATE
IMON
LTC4232DHC-1
OV
F LT
+
100k
20k
1µF
*TVS: DIODES INC. SMAJ17A
ADC
4.7nF
0.1µF
3.3nF
107k
*
10k
5.23k
150k
20k
VIN
10V/DIV
VOUT
10V/DIV
PG
10V/DIV
4ms/DIV 42321 TA01b
IIN
1A/DIV
CONTACT BOUNCE
LTC4232—1 1111111] ,:::::::,
LTC4232-1
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16
15
14
13
12
11
10
9
17
SENSE
1
2
3
4
5
6
7
8
TOP VIEW
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
VDD
ISET
IMON
FB
F LT
PG
GATE
OUT
VDD
UV
OV
TIMER
INTVCC
GND
OUT
OUT
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 17) IS SENSE,
θJA = 43°C/W SOLDERED, OTHERWISE θJA = 140°C/W
pin conFiguraTionabsoluTe MaxiMuM raTings
Supply Voltage (VDD) ................................. –0.3V to 28V
Input Voltages
FB, OV, UV ..............................................–0.3V to 12V
TIMER ................................................... –0.3V to 3.5V
SENSE .............................VDD – 10V or – 0.3V to VDD
Output Voltages
ISET, IMON ................................................. –0.3V to 3V
PG, FLT .................................................. –0.3V to 35V
OUT ............................................ –0.3V to VDD + 0.3V
INTVCC .................................................. –0.3V to 3.5V
GATE (Note 3) ........................................ –0.3V to 33V
Operating Ambient Temperature Range
LTC4232C-1 ............................................. 0°C to 70°C
LTC4232I-1 ..........................................–40°C to 85°C
Junction Temperature (Notes 4, 5) ........................ 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
elecTrical characTerisTics
The l denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Characteristics
VDD Input Supply Range l2.9 15 V
IDD Input Supply Current MOSFET On, No Load l1.6 3 mA
VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l2.63 2.73 2.85 V
IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 15V
VOUT = VGATE = 12V
l
l
1
0
2
±150
4
µA
µA
RON MOSFET + Sense Resistor On-Resistance l15 33 50 mΩ
ILIM(TH) Current Limit Threshold V = 1.23V, ISET Open l5.0 5.6 6.1 A
VFB = 0V, ISET Open l1.2 1.5 1.8 A
VFB = 1.23V, RSET = 20kΩ l2.6 2.9 3.3 A
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4232CDHC-1#PBF LTC4232CDHC-1#TRPBF 42321 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C
LTC4232IDHC-1#PBF LTC4232IDHC-1#TRPBF 42321 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
LTC4232—1
LTC4232-1
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Inputs
IIN OV, UV, FB Input Current V = 1.2V l0 ±1 µA
VTH OV, UV, FB Threshold Voltage VPIN Rising l1.21 1.235 1.26 V
ΔVOV(HYST) OV Hysteresis l10 20 30 mV
ΔVUV(HYST) UV Hysteresis l50 80 110 mV
VUV(RTH) UV Reset Threshold Voltage VUV Falling l0.55 0.62 0.7 V
ΔVFB(HYST) FB Power Good Hysteresis l10 20 30 mV
RISET ISET Internal Resistor l19 20 21 kΩ
Outputs
VINTVCC INTVCC Output Voltage VDD = 5V, 15V, ILOAD = 0mA, –10mA l2.8 3.1 3.3 V
VOL PG, F LT Output Low Voltage ISINK = 2mA l0.4 0.8 V
IOH PG, F LT Input Leakage Current V = 30V l0 ±10 µA
VTIMER(H) TIMER High Threshold VTIMER Rising l1.2 1.235 1.28 V
VTIMER(L) TIMER Low Threshold VTIMER Falling l0.1 0.21 0.3 V
ITIMER(UP) TIMER Pull-Up Current VTIMER = 0V l–80 –100 –120 µA
ITIMER(DN) TIMER Pull-Down Current VTIMER = 1.2V l1.4 2 2.6 µA
ITIMER(RATIO) TIMER Current Ratio ITIMER(DN)/ITIMER(UP) l1.6 2 2.7 %
BWIMON IMON Bandwidth 250 kHz
AIMON IMON Current Gain IOUT = 2.5A l18.5 20 21.5 µA/A
IOFF(IMON) IMON Offset Current IOUT = 150mA l0 ±4.5 µA
IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l–18 –24 –29 µA
IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V l180 250 400 µA
IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 mA
AC Characteristics
tPHL(GATE) Input High (OV), Input Low (UV) to Gate Low
Propagation Delay
VGATE < 16.5V Falling l8 10 µs
tPHL(ILIM) Short-Circuit to Gate Low VFB = 0, Step ISENSE to 6A,
VGATE < 15V Falling
l1 5 µs
tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l8 16 24 ms
tD(FAULT) UVLOW to Clear Fault Latch Delay 1 µs
tD(CB) Circuit Breaker Filter Delay Time (Internal) VFB = 0V, Step ISENSE to 3A l1.3 2 2.7 ms
tD(AUTO-RETRY) Auto-Retry Turn-On Delay (Internal) l8 16 24 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V
above OUT. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the formula:
TJ = TA + (PD • 43°C/W)
elecTrical characTerisTics
The l denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
LTC4232—1 5%: \\ 250 I 4m: 4 L7HCU§QB
LTC4232-1
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TEMPERATURE (°C)
–50
ISET RESISTOR (kΩ)
22
21
20
19
18
–25 0 25
42321 G09
50 75 100
FB VOLTAGE (V)
CURRENT LIMIT VALUE (A)
6
5
4
3
2
1
0
42321 G07
0 0.2 0.4 0.6 0.8 1.0 1.2
ISET OPEN
RSET (Ω)
1k
CURRENT LIMIT THRESHOLD VALUE (A)
6
5
4
3
2
1
0
10k 100k
42321 G08
1M 10M
TEMPERATURE (°C)
–50
UV HYSTERESIS (V)
0.10
0.08
0.06
0.04
–25 0 25
42321 G04
50 75 100
TEMPERATURE (°C)
–50
TIMER PULL-UP CURRENT (µA)
–110
–105
–100
–95
–90
–25 0 25
42321 G05
50 75 100
TEMPERATURE (°C)
–50
UV LOW-HIGH THRESHOLD (V)
1.234
1.232
1.230
1.228
1.226
–25 0 25
42321 G03
50 75 100
VDD (V)
0
1.0
IDD (mA)
1.2
1.4
1.6
1.8
2.0
5 10 15 20
42321 G01
25 30
–40°C
25°C
85°C
ILOAD (mA)
0
0
0.5
1.5
1.0
INTVCC (V)
3.5
2.0
2.5
3.0
42321 G02
–14–12–10–8–6–4–2
VDD = 5V
VDD = 3.3V
Typical perForMance characTerisTics
IDD vs VDD INTVCC Load Regulation
UV Low-High Threshold
vs Temperature
UV Hysteresis vs Temperature
Timer Pull-Up Current
vs Temperature
Current Limit Delay
(tPHL(ILIM) vs Overdrive)
Current Limit Threshold Foldback
Current Limit Adjustment
(IOUT vs RSET)
Internal ISET Resistor (RISET)
vs Temperature
TA = 25°C, VDD = 12V unless otherwise noted.
OUTPUT CURRENT (A)
0
CURRENT PROPAGATION DELAY (µs)
1000
100
10
1
0.1
10
42321 G06
20 30
LTC4232-1 L7 HEW 5
LTC4232-1
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TEMPERATURE (°C)
–50
0.9
0.8
0.7
0.6
0.5
0.4
0.3
–25 0 25
42321 G18
50 75 150125100
VISET (V)
TEMPERATURE (°C)
–50
–105
–100
–95
–90
–85
–80
–25 0 25
42321 G13
50 75 100
IMON (µA)
VDD = 3.3V, 12V
ILOAD = 5A
TEMPERATURE (°C)
–50
IGATE PULL-UP (µA)
–26.0
–25.5
–25.0
–24.5
–24.0
–25 0 25
42321 G14
50 75 100
IGATE (µA)
0
0
7
6
5
4
3
2
1
–5 –10 –15 –20
42321 G15
–25 –30
VDD = 12V
VDD = 3.3V
∆VGATE (VGATE – VOUT) (V)
VDD (V)
0
6.2
6.0
5.8
5.6
5.4
5.2
5 10 15
42321 G16
20 25 30
∆VGATE (VGATE – VOUT) (V)
TEMPERATURE (°C)
–50
6.15
6.14
6.13
6.12
6.11
6.10
–25 0 25
42321 G17
50 75 100
∆VGATE (VGATE – VOUT) (V)
CURRENT (mA)
0
0
PG, FLT VOL (V)
14
12
10
8
6
4
2
2468
42321 G12
10 12
FLT
PG
TEMPERATURE (°C)
–50
60
50
40
30
20
10
0
–25 0 25
42321 G10
50 75 100
RON (mΩ)
VDD = 3.3V, 12V
VDS (V)
0.1
0.01
ID (A)
0.1
1
10
1 10 100
42321 G11
TA = 25°C
MULTIPLE PULSE
DUTY CYCLE = 0.2
DC
10s
100ms
10ms
1ms
1s
Typical perForMance characTerisTics
RON vs VDD and Temperature MOSFET SOA Curve
IMON vs Temperature and VDD
Gate Drive
vs Gate Pull-Up Current
PG, F LT Output Low Voltage
vs Current
TA = 25°C, VDD = 12V unless otherwise noted.
GATE Pull-Up Current
vs Temperature
Gate Drive vs VDD Gate Drive vs Temperature VISET vs Temperature
LTC4232—1 6 L7LJ1‘JW
LTC4232-1
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pin FuncTions
FB: Foldback and Power Good Input. Connect this pin to
an external resistive divider from OUT. If the voltage falls
below 0.6V, the current limit is reduced using a foldback
profile (see the Typical Performance Characteristics sec-
tion). If the voltage falls below 1.21V, the PG pin will pull
low to indicate the power is bad.
F LT : Overcurrent Fault Indicator. Open-drain output pulls
low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
the Applications Information section for details).
GATE: Gate Drive for Internal N-channel MOSFET. An internal
24µA current source charges the gate of the N-channel
MOSFET. A resistor and capacitor network from this pin sets
the turn-on rate. During an undervoltage or overvoltage
condition a 250µA pull-down current turns the MOSFET
off. During a short-circuit or undervoltage lockout condi-
tion, a 140mA pull-down current source between GATE
and OUT is activated.
GND: Device Ground.
IMON: Current Monitor Output. The current in the internal
MOSFET switch is divided by 50,000 and sourced from this
pin. Placing a 20k resistor from this pin to GND creates a
0V to 2V voltage swing when current ranges from 0A to 5A.
INTVCC: Internal 3.1V Supply Decoupling Output. This pin
must have a 1µF or larger bypass capacitor. Overloading
this pin can disrupt internal operation.
ISET: Current Limit Adjustment Pin. For a 5.6A current limit
value open this pin. This pin is driven by a 20k resistor
in series with a voltage source. The pin voltage is used
to generate the current limit threshold. The internal 20k
resistor (RISET) and an external resistor (RSET) between
ISET and ground create an attenuator that lowers the current
limit value. Due to circuit tolerance, RSET should not be
less than 2k. In order to match the temperature variation
of the sense resistor, the voltage on this pin increases at
the same rate as the sense resistance increases. Therefore
the voltage at ISET pin is made proportional to temperature
of the MOSFET switch.
OUT: Output of Internal MOSFET Switch. Connect this pin
directly to the load.
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from VDD. If the voltage at this
pin rises above 1.235V, an overvoltage is detected and
the switch turns off. Tie to GND if unused.
PG: Power Good Indicator. Open-drain output pulls low
when the FB pin drops below 1.21V indicating the power is
bad. If the FB pin rises above 1.23V and the GATE to OUT
voltage exceeds 4.2V, the open-drain pull-down releases
the PG pin to go high.
SENSE: Current Sense Node and MOSFET Drain. The cur-
rent limit circuit controls the GATE pin to limit the sense
voltage between the VDD and SENSE pins to 42mV (5.6A)
or less depending on the voltage at the FB pin. The exposed
pad on DHC packages are connected to SENSE and must
be soldered to an electrically isolated printed circuit board
trace to properly transfer the heat out of the package.
TIMER: Timer Input. Connect a capacitor between this pin
and ground to set a 12ms/µF duration for current limit
before the switch is turned off. If the UV pin is toggled
low while the MOSFET switch is off, the switch will turn on
again following a cooldown time of 518ms/µF duration. Tie
this pin to INTVCC for a fixed 2ms overcurrent delay. Note
that the fixed 2ms overcurrent delay is not recommended
when auto-retry is enabled (see Applications Information).
UV: Undervoltage Comparator Input. Tie high if unused.
Connect this pin to an external resistive divider from VDD.
If the UV pin voltage falls below 1.15V, an undervoltage is
detected and the switch turns off. Pulling this pin below
0.62V resets the overcurrent fault and allows the switch
to turn back on (see the Applications Information section
for details). If overcurrent auto-retry is desired then tie
this pin to the F LT pin.
VDD: Supply Voltage and Current Sense Input. This pin
has an undervoltage lockout threshold of 2.73V.
LTC4232—1 L7 LJUW 7
LTC4232-1
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FuncTional DiagraM
42321 BD
RISET
20k
VDD
UV
OUT
FB
PG
GND
IMON
INTVCC
INTVCC
100µA
TIMER
F LT
+
–ISET
GATE
6.15V
SENSE
(EXPOSED PAD)
X1
CLAMP
0.6V POSITIVE
TEMPERATURE
COEFFICIENT
REFERENCE
INTERNAL 25mΩ
MOSFET
INTERNAL 7.5mΩ
SENSE RESISTOR
CHARGE
PUMP
AND GATE
DRIVER
f = 2MHz
OUT
3.1V
GEN
LOGIC
CS
CM
FOLDBACK
0.6V
2.65V
1.235V
+–
+
–
PG
1.235V
–
+
UV
0.21V
–
+
TM1
1.235V –
+
TM2
0.62V
–
+
RST
VDD
VDD
2.73V +
–
UVLO1
OV
1.235V –
+
OV
2µA
–
+
UVLO2
LTC4232—1 8 L7LJ1‘JW
LTC4232-1
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operaTion
The Functional Diagram displays the main circuits of
the device. The LTC4232-1 is designed to turn a board’s
supply voltage on and off in a controlled manner allowing
the board to be safely inserted and removed from a live
backplane. The LTC4232-1 includes a 25mΩ MOSFET and
a 7.5mΩ current sense resistor. During normal opera-
tion, the charge pump and gate driver turn on the pass
MOSFET’s gate to provide power to the load. The inrush
current control is accomplished by a resistor and capacitor
network connected to the GATE pin. This circuit limits the
GATE ramp rate and hence controls the voltage ramp rate
of the output capacitor.
The current sense (CS) amplifier monitors the load current
using the voltage sensed across the current sense resistor.
The CS amplifier limits the current in the load by reduc-
ing the GATE-to-OUT voltage in an active control loop. It
is simple to adjust the current limit threshold using the
current limit adjustment (ISET) pin. This allows a different
threshold during other times such as start-up.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current
limit value from 5.6A to 1.5A in a linear manner as the
FB pin drops below 0.6V (see the Typical Performance
Characteristics section).
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.235V (comparator TM2). This indicates to the
logic that it is time to turn off the pass MOSFET to prevent
overheating. At this point the TIMER pin ramps down us-
ing the 2µA current source until the voltage drops below
0.21V (Comparator TM1) which tells the logic to start
an internal 16ms timer. At this point, the pass transistor
has cooled and it is safe to turn it on again. Latchoff is
the normal operating condition following overcurrent
turn-off. Retry is initiated by pulling the UV pin low for
a minimum of 1µs then high. Auto-retry is implemented
by tying the FLT to the UV pin.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signaled by the PG
pin using an open-drain pull-down transistor.
The Functional Diagram also shows the monitoring blocks
of the LTC4232-1. The two comparators on the left side
include the UV and OV comparators. These comparators
determine if the external conditions are valid prior to turning
on the MOSFET. But first the undervoltage lockout circuits
UVLO1 and UVLO2 must validate the input supply and
the internally generated 3.1V supply (INTVCC) and gener-
ate the power up initialization to the logic circuits. If the
external conditions remain valid for 16ms the MOSFET is
allowed to turn on.
Other features include MOSFET current and temperature
monitoring. The current monitor (CM) outputs a current
proportional to the sense resistor current. This current can
drive an external resistor or other circuits for monitoring
purposes. A voltage proportional to the MOSFET tempera-
ture is output to the ISET pin. The MOSFET is protected by
a thermal shutdown circuit.
LTC4232—1 SLOPE = zduA/Cem 1 L7 LJUW 9
LTC4232-1
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applicaTions inForMaTion
The voltage at the GATE pin rises with a slope equal to
24µA/CGATE and the supply inrush current is set at:
IINRUSH=
C
L
C
GATE
•24µA
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT volt-
age follows the GATE voltage as it increases. Once OUT
reaches VDD, the GATE will ramp up until clamped by the
6.15V Zener between GATE and OUT.
Figure 2. Supply Turn-On
Figure 1. 2A, 12V Card Resident Application
The typical LTC4232-1 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. A complete application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
Turn-On Sequence
Several conditions must be present before the internal
pass MOSFET can be turned on. First the supply VDD must
exceed its undervoltage lockout level. Next the internally
generated supply INTVCC must cross its 2.65V undervolt-
age threshold. This generates a 25µs power-on-reset pulse
which clears the fault register and initializes internal latches.
After the power-on-reset pulse, the UV and OV pins must
indicate that the input voltage is within the acceptable
range. All of these conditions must be satisfied for the
duration of 16ms to ensure that any contact bounce dur-
ing the insertion has ended.
The MOSFET is turned on by charging up the GATE with a
24µA charge pump generated current source (Figure 2).
ADC
R1
226k
C1
1µF
R2
20k
12V
42321 F01
CT
0.1µF
*TVS Z1: DIODES INC. SMAJ17A
CL
150µF
VOUT
12V
2A
VDD
UV
Z1*
OUT
FB
PG
GND
IMON
RSET
20k
RMON
20k
ISET
CGATE
4.7nF
RGATE
100k
CCOMP
3.3nF
GATE
LTC4232-1
OV
INTVCC
TIMER
F LT
+
R3
140k
R4
20k
R7
10k
R6
20k
R5
150k
UV = 9.88V
OV = 15.2V
PG = 10.5V
t1 t2
SLOPE = 24µA/CGATE
GATE
OUT
VDD + 6.15V
VDD
42321 F02
LTC4232—1 ‘IO
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applicaTions inForMaTion
If VDD drops below 2.65V for greater than 5µs or INTVCC
drops below 2.5V for greater than 1µs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
140mA current to the OUT pin.
Overcurrent Fault
The LTC4232-1 features an adjustable current limit with
foldback that protects against short-circuits and excessive
load current. To prevent excessive power dissipation in the
switch during active current limit, the available current is
reduced as a function of the output voltage sensed by the
FB pin. A graph in the Typical Performance Characteristics
curves shows the Current Limit Threshold Foldback.
An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the timeout delay set
by the TIMER. Current limiting begins when the MOSFET
current reaches 1.5A to 5.6A (depending on the foldback).
The GATE pin is then brought down with a 140mA GATE-
to-OUT current. The voltage on the GATE is regulated in
order to limit the current to less than 5.6A. At this point,
a circuit breaker time delay starts by charging the external
timing capacitor with a 100µA pull-up current from the
TIMER pin. If the TIMER pin reaches its 1.235V threshold,
the internal switch turns off (with a 250µA current from
GATE to ground). Included in the Typical Performance
Characteristics curves is a graph of the Safe Operating
Area for the MOSFET. From this graph one can determine
the MOSFET’s maximum time in current limit for a given
output power.
Tying the TIMER pin to INTVCC will force the part to use
the internally generated (circuit breaker) delay of 2ms.
In either case the F LT pin is pulled low to indicate an
overcurrent fault has turned off the pass MOSFET. For a
given circuit breaker time delay, the equation for setting
the timing capacitor’s value is as follows:
CT = tCB • 0.083[µF/ms]
As the OUT voltage rises, so will the FB pin which is moni-
toring it. Once the FB pin crosses its 1.235V threshold
and the GATE to OUT voltage exceeds 4.2V, the PG pin
will cease to pull low and indicate that the power is good.
Parasitic MOSFET Oscillation
When the N-channel MOSFET ramps up the output dur-
ing power-up it operates as a source follower. The source
follower configuration may self-oscillate in the range of
25kHz to 300kHz when the load capacitance is less than
10µF, especially if the wiring inductance from the supply
to the VDD pin is greater than 3µH. The possibility of oscil-
lation will increase as the load current (during power-up)
increases. There are two ways to prevent this type of
oscillation. The simplest way is to avoid load capacitances
below 10µF. For wiring inductance larger than 20µH, the
minimum load capacitance may extend to 100µF. A second
choice is to connect an external gate capacitor CP >1.5nF
as shown in Figure 3.
42321 F03
LTC4232-1
GATE CP
2.2nF OPTIONAL
RC TO LOWER
INRUSH CURRENT
Figure 3. Compensation for Small CLOAD
Turn-Off Sequence
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its
1.235V threshold. Additionally, several fault conditions
will turn off the switch. These include an input overvolt-
age (OV pin), overcurrent circuit breaker (SENSE pin) or
overtemperature. Normally the switch is turned off with
a 250µA current pulling down the GATE pin to ground.
With the switch turned off, the OUT voltage drops which
pulls the FB pin below its threshold. PG then pulls low to
indicate output power is no longer good.
LTC4232—1 “HF” W. "—1—— L7 LJUW 1 1
LTC4232-1
11
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For more information www.linear.com/LTC4232-1
applicaTions inForMaTion
After the switch is turned off, the TIMER pin begins
discharging the timing capacitor with a 2µA pull-down
current. When the TIMER pin reaches its 0.21V threshold,
an internal 16ms timer is started. After the 16ms delay,
the switch is allowed to turn on again if the overcurrent
fault latch has been cleared. Bringing the UV pin below
0.6V for minimum of 1µs and then high will clear the fault
latch. If the TIMER pin is tied to INTVCC then the switch is
allowed to turn on again (after an internal 16ms delay), if
the overcurrent fault latch is cleared.
Tying the F LT pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin
has ramped below 0.21V. In this auto-retry mode the
LTC4232-1 repeatedly tries to turn on after an overcurrent
at a period determined by the capacitor on the TIMER pin.
When the TIMER pin is tied to INTVCC the internal 16ms
turn-on delay is not sufficient to prevent overheating during
auto-retry into a shorted load. Using an external timing
capacitor is recommended when using auto-retry mode.
The waveform in Figure 4 shows how the output latches
off following a short-circuit. The current in the MOSFET
is 1.4A as the timer ramps up.
∆VGATE
10V/DIV
IOUT
2A/DIV
VOUT
10V/DIV
TIMER
2V/DIV
1ms/DIV 42321 F04
Figure 4. Short-Circuit Waveform
The RGATE, CGATE and CCOMP network on the GATE pin
compensates the current limit regulation loop. It is pos-
sible to eliminate CCOMP and use only the RGATE and CGATE
network, which will require RGATE to reduce to 270Ω (see
Figure 5). This alternate compensation with one less
component allows the GATE pin to undershoot during a
short circuit on the output and chatter as it settles. This
chatter could last about 1µs to 2µs for every nF of CGATE
capacitance.
LTC4232-1
Typical Compensation
OUT
GATE
CCOMP
3.3nF
CGATE
4.7nF
RGATE
100k
LTC4232-1
Alternate Compensation
OUT
GATE
42321 F05
CGATE
4.7nF
RGATE
270Ω
Figure 5. Compensation Components on the GATE Pin
Current Limit Adjustment
The default value of the active current limit is 5.6A. The
current limit threshold can be adjusted lower by placing
a resistor between the ISET pin and ground. As shown in
the Functional Block Diagram the voltage at the ISET pin
(via the clamp circuit) sets the CS amplifier’s built-in offset
voltage. This offset voltage directly determines the active
current limit value. With the ISET pin open, the voltage at
the ISET pin is determined by a positive temperature co-
efficient reference. This voltage is set to 0.618V at room
temperature which corresponds to a 5.6A current limit at
room temperature.
An external resistor RSET placed between the ISET pin and
ground forms a resistive divider with the internal 20k RISET
sourcing resistor. The divider acts to lower the voltage at
the ISET pin and therefore lower the current limit threshold.
The overall current limit threshold precision is reduced to
±12% when using a 20k resistor to halve the threshold.
Using a switch (connected to ground) in series with RSET
allows the active current limit to change only when the
switch is closed. This feature can be used to program a
reduced running current while the maximum available
current limit is used at startup.
LTC4232—1 RSET (RSET ) VISET V‘SET 12 L7LJCUEN2
LTC4232-1
12
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For more information www.linear.com/LTC4232-1
applicaTions inForMaTion
Monitor MOSFET Temperature
The voltage at the ISET pin increases linearly with increas-
ing temperature. The temperature profile of the ISET pin is
shown in the Typical Performance Characteristics section.
Using a comparator or ADC to measure the ISET voltage
provides an indicator of the MOSFET temperature.
The ISET voltage follows the formula:
VISET =
R
SET
R
SET
+R
ISET
•T+273°C
( )
•2.093[mV/°C]
The MOSFET temperature is calculated using RISET of 20k.
T=
R
SET +
20k
( )
•V
ISET
RSET •2.093 [mV /°C] – 273°
C
When RSET is not present, T becomes:
T=
ISET
2.093 [mV /°C]– 273°C
There is an overtemperature circuit in the LTC4232-1 that
monitors an internal voltage similar to the ISET pin voltage.
When the die temperature exceeds 145°C the circuit turns
off the MOSFET until the temperature drops to 125°C.
Monitor MOSFET Current
The current in the MOSFET passes through an internal
7.5mΩ sense resistor. The voltage on the sense resistor is
converted to a current that is sourced out of the IMON pin.
The gain of ISENSE amplifier is 20µA/A referenced from the
MOSFET current. This output current can be converted to
a voltage using an external resistor to drive a comparator
or ADC. The voltage compliance for the IMON pin is from
0V to INTVCC – 0.7V.
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci-
tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
Monitor OV and UV Faults
Protecting the load from an overvoltage condition is the
main function of the OV pin. In Figure 1 an external resis-
tive divider (driving the OV pin) connects to a comparator
to turn off the MOSFET when the VDD voltage exceeds
15.2V. If the VDD pin subsequently falls back below 14.9V,
the switch will be allowed to turn on immediately. In the
LTC4232-1 the OV pin threshold is 1.235V when rising,
and 1.215V when falling out of overvoltage.
The UV pin functions as an undervoltage protection pin
or as an “ON” pin. In the Figure 1 application the MOSFET
turns off when VDD falls below 9.23V. If the VDD pin sub-
sequently rises above 9.88V for 100ms, the switch will
be allowed to turn on again. The LTC4232-1 UV turn-on/
off thresholds are 1.235V (rising) and 1.155V (falling).
In the cases of an undervoltage or overvoltage the MOS-
FET turns off and there is indication on the PG status pin.
When the overvoltage is removed the MOSFET’s gate
ramps up immediately.
Power Good Indication
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The Figure 1 application uses an external resistive divider
on the OUT pin to drive the FB pin. The PG comparator
indicates logic high when OUT pin rises above 10.5V. If the
OUT pin subsequently falls below 10.3V the comparator
toggles low. On the LTC4232-1 the PG comparator drives
high when the FB pin rises above 1.235V and low when
it falls below 1.215V.
LTC4232—1 1.2ms cL-vIN 150uF~12V “WW L7Hfl§0g 1 3
LTC4232-1
13
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For more information www.linear.com/LTC4232-1
Figure 6. 5A, 12V Card Resident Application
ADC
C1
1µF
R2
20k
12V
R3
140k
R4
20k
RMON
20k
UV = 9.88V
OV = 15.2V
PG = 10.5V
42321 F06
CT
0.1µF
CGATE
4.7nF
CCOMP
3.3nF
CL
150µF
VDD
UV
OUT
FB
GATE
PG
GND
IMON
ISET
LTC4232-1
OV
INTVCC
TIMER
F LT
+
VOUT
12V
5A
R7
10k
R6
20k
R5
150k
RGATE
100k
Z1*
*TVS Z1: DIODES INC. SMAJ17A
R1
226k
applicaTions inForMaTion
Once the PG comparator is high the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V the PG pin goes high.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes low when the GATE is commanded off (using
the UV, OV or SENSE pins) or when the PG comparator
drives low.
Design Example
Consider the following design example (Figure 6): VIN =
12V, IMAX = 5A. IINRUSH = 750mA, CL = 150µF, VUVON =
9.88V, VOVOFF = 15.2V, VPGTHRESHOLD = 10.5V. A current
limit fault triggers an automatic restart of the power-up
sequence.
The inrush current is set to 750mA using CGATE:
CGATE =CL
I
GATE(UP)
I
INRUSH
=150µF 24µA
750mA ≅4.7nF
Calculate the time it takes to charge CL:
tCHARGEUP =
C
L
•V
IN
IINRUSH
=
150µF •12V
750mA =2.4ms
The peak power dissipation of 12V at 750mA (or 9W) must
not exceed the SOA of the pass MOSFET for 2.4ms (see
MOSFET SOA graph in the Typical Performance Charac-
teristics section).
Next the power dissipated in the MOSFET during overcur-
rent must be limited. The active current limit uses a timer
to prevent excessive energy dissipation in the MOSFET
.
The worst-case power dissipation occurs when the voltage
versus current profile of the foldback current limit is at
the maximum. This occurs when the current is 6.1A and
the voltage is one half of the VIN or 6V. See the Current
Limit Threshold Foldback graph in the Typical Performance
Characteristics section to view this profile. In order to
survive 36W, the MOSFET SOA dictates a maximum time
of 10ms (see SOA graph). Therefore, it is acceptable to set
the current limit timeout using CT to be 1.2ms:
CT=
1.2ms
12[ms /µF]=0.1µF
After the 1.2ms timeout the F LT pin needs to pull-down
on the UV pin to restart the power-up sequence.
LTC4232—1 14
LTC4232-1
14
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For more information www.linear.com/LTC4232-1
applicaTions inForMaTion
The values for overvoltage, undervoltage and power good
thresholds using the resistive dividers on the UV, OV and
FB pins match the requirements of turn-on at 9.88V and
turn-off at 15.2V.
The final schematic in Figure 6 results in very few external
components. The pull-up resistor, R7, connects to the PG
pin while the 20k (RMON) converts the IMON current to a
voltage at a ratio:
VIMON = 20[µA/A] • 20k • IOUT = 0.4[V/A] • IOUT
In addition there is a 1µF bypass (C1) on the INTVCC pin.
Layout Considerations
In Hot Swap applications where load currents can be 5A,
narrow PCB tracks exhibit more resistance than wider tracks
and operate at elevated temperatures. The minimum trace
width for 1oz copper foil is 0.02" per amp to make sure
the trace stays at a reasonable temperature. Using 0.03"
per amp or wider is recommended. Note that 1oz copper
Figure 7. Recommended Layout
42321 F07
HEAT SINK
VIA TO
SINK
GND
C
OUTVDD
exhibits a sheet resistance of about 0.5mΩ/square. Small
resistances add up quickly in high current applications.
There are two VDD pins on opposite sides of the package
that connect to the sense resistor and MOSFET. The PCB
layout should be balanced and symmetrical to each VDD
pin to balance current in the MOSFET bond wires. Figure 7
shows a recommended layout for the LTC4232-1.
Although the MOSFET is self protected from overtem-
perature, it is recommended to solder the backside of the
package to a copper trace to provide a good heat sink.
Note that the backside is connected to the SENSE pin and
cannot be soldered to the ground plane. During normal loads
the power dissipated in the MOSFET is as high as 1.9W.
A 10mm × 10mm area of 1oz copper should be sufficient.
This area of copper can be divided in many layers.
It is also important to put C1, the bypass capacitor for
the INTVCC pin as close as possible between the INTVCC
and GND.
L7 LJUW LTC4232—1 9W F71 .H— § 15
LTC4232-1
15
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For more information www.linear.com/LTC4232-1
applicaTions inForMaTion
Additional Applications
The LTC4232-1 has a wide operating range from 2.9V to
15V. The UV, OV and PG thresholds are set with few resis-
tors. All other functions are independent of supply voltage.
In addition to Hot Swap applications, the LTC4232-1 also
functions as a backplane resident switch for removable
load cards (see Figure 8.)
The last page shows a 3.3V application with a UV threshold
of 2.87V, an OV threshold of 3.77V and a PG threshold
of 3.05V.
Figure 8. 12V, 5A Backplane Resident Application with Insertion Activated Turn-On
UV = 9.88V
OV = 15.2V
PG = 10.5V
R5
150k
R6
20k
RGATE
100k
ADC
C1
1µF RMON
20k
42321 F08
CGATE
4.7nF
CCOMP
3.3nF
CT
0.1µF
VDD
PG
OUT
FB
UV
GND
IMON
ISET
GATE
LTC4232DHC-1
OV
INTVCC
TIMER
F LT
VOUT
12V
5A
12V
R7
10k
R1
226k
R2
20k
12V
R4
20k R3
140k
LOAD
*TVS Z1: DIODES INC. SMAJ17A
Z1*
LTC4232—1 Wfififififififlfi% \ fiflflflpfilflflfl‘f ‘_ ‘ a ‘ T ¢ } xuuuupuwu,7 157T 77777 7 L %* 9% 16 L7LJCUEN2
LTC4232-1
16
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For more information www.linear.com/LTC4232-1
package DescripTion
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
Please refer to http://www.linear.com/product/LTC4232-1#packaging for the most recent package drawings.
3.00 0.10
(2 SIDES)
5.00 0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 0.10
(2 SIDES)
0.75 0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 0.05
PIN 1
NOTCH
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 0.05
(2 SIDES)2.20 0.05
0.50 BSC
0.65 0.05
3.50 0.05
PACKAGE
OUTLINE
0.25 0.05
LTC4232—1 L7 LJUW 17
LTC4232-1
17
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For more information www.linear.com/LTC4232-1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 08/15 Raised IGATE(DN) maximum from 340µA to 400µA 3
B 01/16 Changed TVS to SMAJ17A in application circuit.
Clarified that operating temperature range refers to ambient.
Added BWIMON and tD(FAULT) specifications.
Updated INTVCC and ISET pin functions.
Added equations to calculate MOSFET temperature from VISET.
1, 9, 13, 15, 18
2
3
6
12
LTc4232-1 .||— III'VW‘ I -I|—| I- "H F‘ "W." -I|-W«-‘ "H fillw
LTC4232-1
18
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For more information www.linear.com/LTC4232-1
LINEAR TECHNOLOGY CORPORATION 2014
LT 0116 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4232-1
relaTeD parTs
Typical applicaTion
3.3V, 5A Card Resident Application with Auto-Retry
PART NUMBER DESCRIPTION COMMENTS
LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
LTC4211 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
LTC4212 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10
LTC4214 Negative Voltage, Hot Swap Controller Operates from 0V to –16V, MSOP-10
LTC4215 Hot Swap Controller with I2C Compatible
Monitoring
Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage
LTC4217 2A Integrated Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable 5% Accurate Current Limit
LTC4218 Hot Swap Controller with 5% Accurate (15mV)
Current Limit
Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16, DFN-16
LTC4219 5A Integrated Hot Swap Controller 12V and 5V Preset Versions, 10% Accurate Current Limit
LT4220 Positive and Negative Voltage Dual Channels Hot
Swap Controller
Operates from ±2.7V to ±16.5V, SSOP-16
LTC4221 Dual Hot Swap Controller/Sequencer Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
LTC4230 Triple Channels Hot Swap Controller Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
LTC4227 Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V, PowerPath™ and Inrush Current Control for
Redundant Supplies
LTC4228 Dual Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V, PowerPath and Inrush Current Control for Two Rails,
MicroTCA, Redundant Power Supplies, and Supply Holdup Applications
LTC4233 10A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit
LTC4234 20A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Accurate Current Limit
14.7k
10k
17.4k
ADC
3.16k
1µF
10k
3.3V
20k
42321 TA02
100k
0.1µF 4.7nF
3.3nF
100µF
VDD
UV
OUT
FB
GATE
GND
IMON
LTC4232DHC-1
OV
INTVCC
TIMER
F LT
+
VOUT
3.3V
5A
10k
ISET
PG
* TVS: DIODES INC. SMAJ17A
*
UV = 2.87V
OV = 3.77V
PG = 3.05V