Microchip Technology 的 HV2761 规格书

VDD 5ND ECL Level NN VP 0 a 2 T26 LE) RGN
Supertex inc.
Supertex inc.
www.supertex.com
HV2761
Doc.# DSFP-HV2761
NR010913
Features
►24-channel high voltage analog switch
►Integrated bleed resistors on the outputs
►3.3 or 5.0V CMOS input logic level
►3:1 MUX-deMUX with 8 states
►20MHz data shift clock frequency
►HVCMOS technology for high performance
►Very low quiescent power dissipation,10µA
►Low parasitic capacitance
►DC to 50MHz analog signal frequency
►-60dB typical OFF-isolation at 5.0MHz
►CMOS logic circuitry for low power
►Excellent noise immunity
►Cascadable serial data register with latches
►Flexible operating supply voltages
Applications
►Medical ultrasound imaging
►Piezoelectric transducer drivers
►Inkjet printer heads
►Optical MEMS modules
General Description
The Supertex HV2761 is a low charge injection, 24-channel,
high voltage analog switch integrated circuit (IC) intended for
use in applications requiring high voltage switching controlled by
low voltage control signals, such as medical ultrasound imaging,
piezoelectric transducer drivers, and printers. The bleed resistors
eliminate voltage built up on capacitive loads such as piezoelectric
transducers.
Input data is shifted into a 24-bit shift register that can then be
retained in a 24-bit latch. To reduce any possible clock feed through
noise, the latch enable (LE) should be left high until all bits are
clocked in. Data are clocked in during the rising edge of the clock.
Using HVCMOS technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
The device is suitable for various combinations of high voltage
supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V.
Block Diagram
Low Charge Injection, 24-Channel,
High Voltage Analog Switch with Bleed Resistors
SW0
Level
Shifters
VPPVNN
Latches
CLRLE
D
LE
CLR
Output
Switches
SW1
Y0
SW2
SW21
SW22
Y7
SW23
SW3
SW4
Y1
SW5
RGND
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
D
LE
CLR
24-Bit
Shift
Register
GNDVDD
CLK
DIN
DOUT
Absolute Maximum Ratings Top Marklng GD Recommended Operating Conditions YY=Yea WW=W L=Lot C=Co A=As Typical Thermal Resistance ::
2
HV2761
Supertex inc.
www.supertex.com
Doc.# DSFP-HV2761
NR010913
Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Parameter Value
VDD logic supply -0.5V to +6.5V
VPP - VNN differential supply 220V
VPP positive supply -0.5V to VNN + 200V
VNN negative supply +0.5V to - 200V
Logic input voltage -0.5V to VDD + 0.3V
Analog signal range VNN to VPP
Peak analog signal current/channel 3.0A
Storage temperature -65°C to 150°C
Power dissipation 1.0W
Recommended Operating Conditions
Sym Parameter Value
VDD Logic power supply voltage 3.0V to 5.5V
VPP Positive high voltage supply +40V to VNN + 200V
VNN Negative high voltage supply -40V to - 160V
VIH High level input voltage 0.9VDD to VDD
VIL Low level input voltage 0V to 0.1VDD
VSIG Analog signal voltage peak-to-peak VNN +10V to VPP - 10V
TAOperating free air temperature 0OC to 70OC
Pin Configuration
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition.
3. Rise and fall times of power supplies VDD, VPP
, and VNN should not be less than 1.0msec.
1
48
Product Marking
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV2761FG
LLLLLLLLL
CCCCCCCC
AAA
48-Lead LQFP
48-Lead LQFP
(top view)
Package may or may not include the following marks: Si or
Typical Thermal Resistance
Package θja
48-Lead LQFP 52OC/W
-G indicates package is RoHS compliant (‘Green’)
Ordering Information
Part Number Package Packing
HV2761FG-G 48-Lead LQFP 250/Tray
HV2761FG-G M931 48-Lead LQFP 1000/Reel
DC Electrical Characteristics
3
HV2761
Supertex inc.
www.supertex.com
Doc.# DSFP-HV2761
NR010913
DC Electrical Characteristics (Over recommended operating conditions unless otherwise specified )
Sym Parameter 0OC +25OC +70OCUnit Conditions
Min Max Min Typ Max Min Max
RONS
Small signal switch
ON-resistance
- - - 26 - - -
Ω
ISIG = 5.0mA VPP = +40V,
VNN = -160V
- - - 22 - - - ISIG = 200mA
- - - 22 - - - ISIG = 5.0mA VPP = +100V,
VNN = -100V
- - - 18 - - - ISIG = 200mA
- - - 20 - - - ISIG = 5.0mA VPP = +160V,
VNN = -40V
- - - 16 - - - ISIG = 200mA
ΔRONS
Small signal switch
ON-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA,
VPP = +100V, VNN = -100V
RONL
Large signal switch
ON-resistance - - - 30 - - - ΩVSIG = VPP - 10V, ISIG = 1.0A
RINT
Output switch shunt resis-
tance - - 20 35 50 - - KΩ Output switch to RGND
IRINT = 0.5mA
ISOL Switch OFF-leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP - 10V, VNN +10V
VOS
DC offset switch OFF - 300 - 100 300 - 300 mV No load
DC offset switch ON - 500 - 100 500 - 500
IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches OFF
INNQ Quiescent VNN supply current - - - -10 -50 - -
IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches ON,
ISW = 5.0mA
INNQ Quiescent VNN supply current - - - -10 -50 - -
ISW Switch output peak current - - - 2.0 1.3 - - A VSIG duty cycle < 0.1%
fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50%
IPP Average VPP supply current
- 4.0 - - 4.5 - 5.0
mA
VPP= +40V,
VNN = -160V All output
switches are
turning ON
and OFF at
50kHz with
no load
- 4.0 - - 4.5 - 5.0 VPP= +100V,
VNN = -100V
- 4.0 - - 4.5 - 5.0 VPP= +160V,
VNN = -40V
INN Average VNN supply current
- 4.0 - - 4.5 - 5.0
mA
VPP = +40V,
VNN = -160V All output
switches are
turning ON
and OFF at
50kHz with
no load
- 4.0 - - 4.5 - 5.0 VPP= +100V,
VNN = -100V
- 4.0 - - 4.5 - 5.0 VPP= +160V,
VNN = -40V
IDD Average VDD supply current - 8.0 - - 8.0 - 8.0 mA fCLK = 5.0MHz, VDD = 5.0V
IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static
ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 mA VOUT = VDD - 0.7V
ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 mA VOUT = 0.7V
CIN Logic input capacitance - 10 - - 10 - 10 pF ---
* See Test Circuits on page 5
AC Electrical Characteristics
4
HV2761
Supertex inc.
www.supertex.com
Doc.# DSFP-HV2761
NR010913
AC Electrical Characteristics (Over recommended operating conditions unless otherwise specified)
Sym Parameter 0OC +25OC +70OCUnit Conditions
Min Max Min Typ Max Min Max
tSD Set up time before LE rises 25 - 25 - - 25 - ns ---
tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V
12 - - 12 - 12 - VDD = 5.0V
tDO Clock delay time to data out 25 100 25 78 100 25 100 ns VDD = 3.0V
15 40 15 30 40 15 40 VDD = 5.0V
tWCLR Time width of CLR 55 - 55 - - 55 - ns ---
tSU Set up time data to clock 21 - 21 - - 21 - ns VDD = 3.0V
7.0 - 7.0 - - 7.0 - VDD = 5.0V
tHHold time data from clock 5.0 - 5.0 - - 5.0 - ns VDD = 3.0V
7.0 - 7.0 - - 7.0 - VDD = 5.0V
fCLK Clock frequency -8--8-8MHz VDD = 3.0V
- 20 - - 20 - 20 VDD = 5.0V
tR, tFClock rise and fall times - 50 - - 50 - 50 ns ---
tON Turn ON time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP - 10V,
RLOAD = 10kΩ
tOFF Turn OFF time - 5.0 - - 5.0 - 5.0
dv/dt Maximum VSIG slew rate
- 20 - - 20 - 20
V/ns
VPP = +40V, VNN = -160V
- 20 - - 20 - 20 VPP = +100V, VNN = -100V
- 20 - - 20 - 20 VPP = +160V, VNN = -40V
KOOFF isolation -30 - -30 -33 - -30 - dB
f = 5.0MHz,
1.0kΩ//15pF load
-58 - -58 -60 - -58 - f = 5.0MHz, 50Ω load
KCR Switch crosstalk -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load
IID
Output switch isolation diode
current - 300 - - 300 - 300 mA 300ns pulse width,
2.0% duty cycle
CSG(OFF)
OFF capacitance SW to GND - 14 - 9.0 14 - 14 pF VSIG = 0V, f = 1.0MHz
all SW OFF
OFF capacitance Y to GND - 35 - 27 35 - 35
CSG(ON)
ON capacitance SW to GND - 39 - 30 39 - 39 pF VSIG = 0V, f = 1.0MHz
one SW ON, two SW OFF
ON capacitance Y to GND - 39 - 30 39 - 39
+VSPK
Output voltage spike
(per switch)
- - - - 150 - -
mV
VPP = +40V, VNN = -160V
RLOAD = 50Ω
-VSPK - - - - 150 - -
+VSPK - - - - 150 - - VPP = +100V, VNN = -100V
RLOAD = 50Ω
-VSPK - - - - 150 - -
+VSPK - - - - 150 - - VPP = +160V, VNN = -40V
RLOAD = 50Ω
-VSPK - - - - 150 - -
* See Test Circuits on page 5
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5
HV2761
Supertex inc.
www.supertex.com
Doc.# DSFP-HV2761
NR010913
Test Circuits
SW1
SW0
Y0
SW1
SW0
Y0
SW1
SW0
Y0
SW1
SW0
Y0
SW1
SW0
Y0
SW1
SW0
Y0
SW1
SW0
Y0
SW1
SW0
Y0
V
PP
-10V
Switch OFF Leakage DC Offset ON/OFF TON/TOFF Test Circuit
OFF Isolation Isolation Diode Current
Charge Injection Output Voltage Spike SW
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
VPP VPP VDD 5.0V
VNN VNN GND
Output Voltage Spike Y
KO = 20Log
VOUT
VIN
V
IN
= 10V
P-P
@5.0MHz
R
LOAD
10kΩ
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
ΔV
OUT
NC
NC
NC
NC
NC
NC
V
PP
-10V I
SOL
V
SIG
I
ID
V
NN
NC
NC
NC
Q = 1000pF • ∆VOUT
50Ω
50Ω
R
L
1kΩ
NC
1000pF +V
SPK
-VSPK
+V
SPK
-VSPK
R
L
1kΩ
50Ω
50Ω
V
IN
= 10V
P-P
@5.0MHz
Crosstalk
KCR = 20Log
VOUT
VIN
50Ω
NC
NC
Y1
NC SW1
SW4SW3
SW0
VPP VPP VDD 5.0V
VNN VNN GND
V
OUT
SW2
NC
SW2
NC
SW2
NC
SW2
NC
SW2
NC
SW2
NC
SW5
NC
NC
SW2
NC
SW2
NC
Y0
RGND RGND
RGND
RGND
RGND RGND
RGND
NC
SW2
RGND RGND
Sym Parameter 0OC +25OC +70OCUnit Conditions
Min Max Min Typ Max Min Max
QC Charge injection
(per switch)
- - - 820 - - -
pC
VPP = +40V, VNN = -160V
- - - 600 - - - VPP = +100V, VNN = -100V
- - - 350 - - - VPP = +160V, VNN = -40V
AC Electrical Characteristics (cont.) (Over recommended operating conditions unless otherwise specified)
Truth Table
6
HV2761
Supertex inc.
www.supertex.com
Doc.# DSFP-HV2761
NR010913
Logic Timing Waveforms
Truth Table
DATA IN
DIN
LE
CLOCK
DATA OUT
DOUT
OFF
VOUT
(typ)
ON
CLR
50% 50%
50% 50%
tWLE
tSD
50% 50%
tSU th
tOFF
50%
tDO
tON
tWCL
DN + 1 DN DN - 1
50% 50%
90%
10%
D0 D1 ... D15 D16 ... D23 LE CLR SW0 SW1 ... SW15 SW16 ... SW23
L -
...
- -
...
- L L OFF -
...
- -
...
-
H - - - - L L ON - - - -
- L - - - L L - OFF - - -
- H - - - L L - ON - - -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - L - - L L - - OFF - -
- - H - - L L - - ON - -
- - - L - L L - - - OFF -
- - - H - L L - - - ON -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - - - - L L - - - - -
- - - - L L L - - - - OFF
- - - - H L L - - - - ON
X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X H ALL SWITCHES OFF
Notes:
1. The 24 switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch.
4. DOUT is high when data in the register 23 is high.
5. Shift registers clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
7
HV2761
Supertex inc.
www.supertex.com
Doc.# DSFP-HV2761
NR010913
Pin Function
1 VPP
2 NC
3 GND
4 CLR
5 LE
6 CLK
7 VDD
8 GND
9 DIN
10 DOUT
11 NC
12 VNN
Pin Function
13 SW0
14 Y0
15 SW1
16 SW2
17 SW3
18 Y1
19 SW4
20 SW5
21 SW6
22 Y2
23 SW7
24 SW8
Pin Function
25 VPP
26 RGND
27 SW9
28 Y3
29 SW10
30 SW11
31 SW12
32 SW13
33 Y4
34 SW14
35 RGND
36 VNN
Pin Function
37 SW15
38 SW16
39 Y5
40 SW17
41 SW18
42 SW19
43 Y6
44 SW20
45 SW21
46 SW22
47 Y7
48 SW23
Pin Function
Side View LL17 View B
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8
HV2761
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV2761
NR010913
48-Lead LQFP Package Outline (FG)
7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
Dimension
(mm)
MIN 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80*
0.50
BSC
0.45
1.00
REF
0.25
BSC
0O
NOM - - 1.40 0.22 9.00 7.00 9.00 7.00 0.60 3.5O
MAX 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* 0.75 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-48LQFPFG Version, D041309.
1
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
Side View
Note 1
(Index Area
D1/4 x E1/4)
48
A2A
A1
b
D
D1
E
E1
e
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.