Analog Devices Inc. 的 LTC2668 规格书

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LTLII‘IM TECHNOLOGY L7 LJUW 1

LTC2668

2668fa

For more information www.linear.com/LTC2668

Block Diagram

Features Description

16-Channel 16-/12-Bit ±10V

VOUT SoftSpan DACs with

10ppm/°C Max Reference

The LTC

2668 is a family of 16-channel, 16-/12-bit ±10V

digital-to-analog converters with integrated precision

references. They are guaranteed monotonic and have

built-in rail-to-rail output buffers. These SoftSpan™ DACs

offer five output ranges up to ±10V. The range of each

channel is independently programmable, or the part can

be hardware-configured for operation in a fixed range.

The integrated 2.5V reference is buffered separately to each

channel; an external reference can be used for additional

range options. The LTC2668 also includes A/B toggle

capability via a dedicated pin or software toggle command.

The SPI/Microwire-compatible 3-wire serial interface

operates on logic levels as low as 1.71V at clock rates

up to 50MHz.

Integral Nonlinearity (LTC2668-16)

applications

n Precision Reference 10ppm/°C Max

n Independently Programmable Output Ranges:

0V to 5V, 0V to 10V, ±2.5V, ±5V, ±10V

n Full 16-Bit/12-Bit Resolution at All Ranges

n Maximum INL Error: ±4LSB at 16 Bits

n A/B Toggle via Software or Dedicated Pin

n 16:1 Analog Multiplexer

n Guaranteed Monotonic Over Temperature

n Internal or External Reference

n Outputs Drive ±10mA Guaranteed

n 1.8V to 5V SPI Serial interface

n 6mm × 6mm 40-Lead QFN Package

n Optical Networking

n Instrumentation

n Data Acquisition

n Automatic Test Equipment

n Process Control and Industrial Automation

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

RGSTR A

INTERNAL REFERENCE

RGSTR B

CONTROL LOGIC DECODE

TOGGLE SELECT REGISTERMONITOR MUX

POWER-ON RESET

RGSTR A

REFCOMP

OVRTMP

2668 TA01a

GND

14, 37

REFLO

13, 35 MUX

REGISTERSPAN

SPAN

DAC 0

VREF

MUX

REGISTERSPAN

SPAN

DAC 15

VREF

RGSTR ARGSTR B

RGSTR B RGSTR A

MUX

REGISTERSPAN

SPAN

DAC 7

•••

MUX

REGISTERSPAN

SPAN

DAC 8

VREF

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

CS/LD

SCK

SDI

SDO

MUX 12

REF

AVP

V+

10, 31

V–

11, 32

VOUT13

VOUT12

VOUT11

VOUT10

VOUT15

VOUT14

VOUT9

VOUT8

CLR

LDAC

TGP

MSP0

MSP1

MSP2

OVP

32-BIT SHIFT REGISTER

CODE

±10V RANGE

–4

INL (LSB)

–1

–2

–3

16384 32768 49152

2668 TA01b

65535

LTC2668 ‘10) ‘39) ‘23) ‘37) ‘26) E51 ‘34) ‘33) ‘32) EU 2 L7Hﬂ§ﬁg

LTC2668

2668fa

For more information www.linear.com/LTC2668

pin conFigurationaBsolute maximum ratings

Analog Supply Voltage (AVP) ....................... –0.3V to 6V

Digital I/O Voltage (OVP) .............................. –0.3V to 6V

REFLO ....................................................... –0.3V to 0.3V

V+............................................................ –0.3V to 16.5V

V–.. ..........................................................–16.5V to 0.3V

CS/LD, SCK, SDI, LDAC, CLR, TGP .............. –0.3V to 6V

MSP0, MSP1, MSP2 ....... –0.3V to Min (AVP + 0.3V, 6V)

VOUT0 to VOUT15, MUX ...V–– 0.3V to V++ 0.3V (Max ±16.5V)

REF, REFCOMP ...............–0.3V to Min (AVP + 0.3V, 6V)

SDO ................................–0.3V to Min (OVP + 0.3V, 6V)

OVRTMP ....................................................... –0.3V to 6V

Operating Temperature Range

LTC2668C ................................................ 0°C to 70°C

LTC2668I .............................................–40°C to 85°C

LTC2668H .......................................... –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOUT10

VOUT9

VOUT8

OVP

CLR

V–

MUX

REFLO

GND

LDAC

CS/LD

SCK

SDO

SDI

TGP

3940 38 37 36 35 34 33 32 31

11 20

12 13 14 15

TOP VIEW

V–

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

16 17 18 19

MSP2

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

V+

MSP1

MSP0

OVRTMP

GND

AVP

REFLO

REFCOMP

REF

V–

V+

TJMAX = 150°C, θJA = 33°C/W, θJC = 2°C/W

EXPOSED PAD IS V–, MUST BE SOLDERED TO PCB

LTC2668 L7 LJUW 3

LTC2668

2668fa

For more information www.linear.com/LTC2668

proDuct selection guiDe

orDer inFormation

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2668CUJ-16#PBF LTC2668CUJ-16#TRPBF LTC2668UJ-16 40-Lead (6mm × 6mm) QFN 0°C to 70°C

LTC2668IUJ-16#PBF LTC2668IUJ-16#TRPBF LTC2668UJ-16 40-Lead (6mm × 6mm) QFN –40°C to 85°C

LTC2668HUJ-16#PBF LTC2668HUJ-16#TRPBF LTC2668UJ-16 40-Lead (6mm × 6mm) QFN –40°C to 125°C

LTC2668CUJ-12#PBF LTC2668CUJ-12#TRPBF LTC2668UJ-12 40-Lead (6mm × 6mm) QFN 0°C to 70°C

LTC2668IUJ-12#PBF LTC2668IUJ-12#TRPBF LTC2668UJ-12 40-Lead (6mm × 6mm) QFN –40°C to 85°C

LTC2668HUJ-12#PBF LTC2668HUJ-12#TRPBF LTC2668UJ-12 40-Lead (6mm × 6mm) QFN –40°C to 125°C

LTC2668 C UJ 16 #TR PBF

LEAD FREE DESIGNATOR

PBF = Lead Free

TAPE AND REEL

TR = 2000-Piece Tape and Reel

RESOLUTION

16 = 16-Bit

12 = 12-Bit

PACKAGE TYPE

UJ = 40-Lead QFN

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2668 4 L7LJ1W

LTC2668

2668fa

For more information www.linear.com/LTC2668

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. AVP = 5V, OVP = 5V, V+ = 15V, V– = –15V, VREF = 2.5V, VOUT unloaded

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT Output Voltage Swing To V– (Unloaded, V– = GND)

To V+ (Unloaded, V+ = 5V)

To V– (–10mA ≤ IOUT ≤ 10mA)

To V+ (–10mA ≤ IOUT ≤ 10mA)

V+ – 1.4

V– + 0.004

V+ – 0.004

V– + 1.4

Load Regulation –10mA ≤ IOUT ≤ 10mA

(Note 4)

l78 150 µV/mA

ROUT DC Output Impedance –10mA ≤ IOUT ≤ 10mA

(Note 4)

l0.078 0.15 Ω

DC Crosstalk (Note 5)

0V to 5V Range

Due to Full-Scale Output Change

Due to Load Current Change

Due to Powering Down (per Channel)

±1

±2

±4

µV

µV/mA

µV

ISC V+/V– Short-Circuit Output Current

(Note 6)

AVP = 5.5V, V+/V– = ±15.75V, VREF = 2.5V,

±10V Output Range

Code: Zero-Scale; Forcing Output to GND

Code: Full-Scale; Forcing Output to GND

–40

–14.5

Reference

Reference Output Voltage 2.495 2.5 2.505 V

Reference Temperature Coefficient (Note 7) ±2 ±10 ppm/°C

Reference Line Regulation AVP ±10% 50 µV/V

Reference Short-Circuit Current AVP = 5.5V, Forcing Output to GND l5 mA

LTC2668-16/LTC2668-12

SYMBOL PARAMETER CONDITIONS

LTC2668-12 LTC2668-16

UNITSMIN TYP MAX MIN TYP MAX

DC Performance

Resolution l12 16 Bits

Monotonicity All Ranges (Note 3) l12 16 Bits

DNL Differential Nonlinearity All Ranges (Note 3) l±0.05 ±0.5 ±0.2 ±1 LSB

INL Integral Nonlinearity

All Ranges (Note 3)

V+/V– = ±15V

V– = GND (Note 3)

C-Grade, I-Grade

H-Grade

±0.2

±1

±2.2

±4

±5

LSB

VOS Unipolar Offset Error 0V to 5V Range

0V to 10V Range

±1

±2

±4

±1

±2

±4

VOS Temperature Coefficient All Unipolar Ranges 1 1 ppm/°C

ZSE Single-Supply Zero-Scale Error All Unipolar Ranges,

V– = GND

l2 4 2 4 mV

BZE Bipolar Zero Error All Bipolar Ranges l±0.02 ±0.08 ±0.02 ±0.08 %FSR

BZE Temperature Coefficient All Bipolar Ranges 1 1 ppm/°C

GE Gain Error All Ranges, External Reference l±0.02 ±0.08 ±0.02 ±0.08 %FSR

Gain Temperature Coefficient 2 2 ppm/°C

PSR Power Supply Rejection

All Ranges

AVP = 5V, ±10%

V+/V– = ±15V, ±5%

0.1

0.001

0.01

LSB/V

LTC2668 L7 LJUW 5

LTC2668

2668fa

For more information www.linear.com/LTC2668

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. AVP = 5V, OVP = 5V, V+ = 15V, V– = –15V, VREF = 2.5V, VOUT unloaded

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

REFCOMP Pin Short-Circuit Current AVP = 5.5V, Forcing Output to GND l200 µA

Reference Load Regulation AVP = 5V ± 10%, IOUT = 100µA Sourcing 140 mV/mA

Reference Output Voltage Noise

Density

CREFCOMP = CREF = 0.1µF, at f = 10kHz 32 nV/√Hz

Reference Input Range External Reference Mode (Note 8) l0.5 AVP – 1.75 V

Reference Input Current External Reference l0.001 1 µA

Reference Input Capacitance (Note 9) l40 pF

Power Supply

AVP Analog Supply Voltage l4.5 5.5 V

V+Analog Positive Supply l4.5 15.75 V

V–Analog Negative Supply V– Not Tied to GND

V– Tied to GND

l–15.75

–4.5 V

OVP Digital I/O Supply Voltage l1.71 AVP + 0.3 V

IAVP Supply Current AVP AVP = 5V, Unipolar Ranges (Note 10)

AVP = 5V, Bipolar Ranges (Note 10)

5.4

9.4

6.5

ISSupply Current V+/V–Unipolar Ranges (Code = 0)

Bipolar Ranges (Note 11)

4.6

6.5

9.5

IOVP Supply Current OVP (Note 12) OVP = 5V l0.02 1 µA

AVP Shutdown Supply Current OVP = AVP = 5V, V+/V– = ±15V l1 3 µA

V+ Shutdown Supply Current OVP = AVP = 5V, V+/V– = ±15V l35 70 µA

V– Shutdown Supply Current OVP = AVP = 5V, V+/V– = ±15V l–60 –27 µA

Monitor Mux

Monitor Mux DC Output Impedance 2.2 kΩ

Monitor Mux Leakage Current Monitor Mux Disabled (High Impedance) l0.02 1 µA

Monitor Mux Output Voltage Range Monitor Mux Selected to DAC Channel lV–V+ – 1.4 V

Monitor Mux Continuous Current

(Note 9)

l±1 mA

AC Performance

tSET Settling Time (Notes 9, 13)

0V to 5V or ±2.5V Span, ±5V Step

±0.024% (±1LSB at 12 Bits)

±0.0015% (±1LSB at 16 Bits)

4.5

µs

Settling Time (Notes 9, 13)

0V to 10V or ±5V Span, ±10V Step

±0.024% (±1LSB at 12 Bits)

±0.0015% (±1LSB at 16 Bits)

µs

Settling Time (Notes 9, 13)

±10V Span, ±20V Step

±0.024% (±1LSB at 12 Bits)

±0.0015% (±1LSB at 16 Bits)

15.5

20.5

µs

SR Voltage Output Slew Rate 5 V/µs

Capacitive Load Driving 1000 pF

Glitch Impulse (Note 14) At Mid-Scale Transition, 0V to 5V Range 8 nV • s

DAC-to-DAC Crosstalk (Note 15) Due to Full-Scale Output Change 6 nV • s

enOutput Voltage Noise

0V to 5V Output Span,

Internal Reference

Density at f = 1kHz

Density at f = 10kHz

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, Internal Reference

1.7

nV/√Hz

µVRMS

LTC2668

2668fa

For more information www.linear.com/LTC2668

electrical characteristics

timing characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. AVP = 5V, OVP = 5V, V+ = 15V, V– = –15V, VREF = 2.5V, VOUT unloaded

unless otherwise specified.

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Digital input low and high voltages are 0V and OVP, respectively.

LTC2668-16/LTC2668-12

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AVP = 4.5V to 5.5V, OVP = 2.7V to AVP

t1 SDI Valid to SCK Setup l6 ns

t2 SDI Valid to SCK Hold l6 ns

t3 SCK HIGH Time l9 ns

t4 SCK LOW Time l9 ns

t5 CS/LD Pulse Width l10 ns

t6 LSB SCK High to CS/LD High l7 ns

t7 CS/LD Low to SCK High l7 ns

t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF

OVP = 4.5V to AVP

OVP = 2.7V to 4.5V

t9 CLR Pulse Width l20 ns

t10 CS/LD High to SCK Positive Edge l7 ns

t12 LDAC Pulse Width l15 ns

t13 CS/LD High to LDAC High or Low Transition l15 ns

SCK Frequency 50% Duty Cycle l50 MHz

t14 TGP High Time (Note 9) l1 µs

t15 TGP Low Time (Note 9) l1 µs

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital I/O

VOH Digital Output High Voltage SDO Pin. Load Current = –100µA lOVP – 0.2 V

VOL Digital Output Low Voltage SDO Pin. Load Current = 100µA

OVRTMP Pin. Load Current = 100µA

0.2

IOZ Digital Hi-Z Output Leakage SDO Pin Leakage Current (CS/LD High)

OVRTMP Pin Leakage Current (Not Asserted)

±1

µA

ILK Digital Input Leakage VIN = GND to OVP l±1 µA

CIN Digital Input Capacitance

(Note 9)

l8 pF

OVP = 2.7V to AVP

VIH Digital Input High Voltage l0.8 • OVP V

VIL Digital Input Low Voltage l0.5 V

OVP = 1.71V to 2.7V

VIH Digital Input High Voltage l0.8 • OVP V

VIL Digital Input Low Voltage l0.3 V

LTC2668 L7 LJUW 7

LTC2668

2668fa

For more information www.linear.com/LTC2668

LTC2668-16/LTC2668-12

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AVP = 4.5V to 5.5V, OVP = 1.71V to 2.7V

t1 SDI Valid to SCK Setup l7 ns

t2 SDI Valid to SCK Hold l7 ns

t3 SCK HIGH Time l30 ns

t4 SCK LOW Time l30 ns

t5 CS/LD Pulse Width l15 ns

t6 LSB SCK High to CS/LD High l7 ns

t7 CS/LD Low to SCK High l7 ns

t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF l60 ns

t9 CLR Pulse Width l30 ns

t10 CS/LD High to SCK Positive Edge l7 ns

t12 LDAC Pulse Width l15 ns

t13 CS/LD High to LDAC High or Low Transition l15 ns

SCK Frequency 50% Duty Cycle l15 MHz

t14 TGP High Time (Note 9) l1 µs

t15 TGP Low Time (Note 9) l1 µs

timing characteristics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Digital input low and high voltages are 0V and OVP, respectively.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to GND

Note 3: For V– = GND, linearity is defined from code kL to code 2N – 1,

where N is the resolution and kL is the lower end code for which no output

limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is

defined from code 128 to code 65,535. For VREF = 2.5V and N = 12, kL = 8

and linearity is defined from code 8 to code 4095.

Note 4: 4.5V ≤ V+ ≤ 16.5V; –16.5V ≤ V– ≤ –4.5V or

V– = GND. VOUT is at least 1.4V below V+ and 1.4V above V–.

Note 5: DC crosstalk is measured with AVP = 5V, using the internal

reference. The conditions of one DAC channel are changed as specified,

and the output of an adjacent channel (at mid-scale) is measured before

and after the change.

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the specified maximum operating junction temperature may impair

device reliability.

Note 7: Temperature coefficient is calculated by first computing the ratio

of the maximum change in output voltage to the nominal output voltage.

The ratio is then divided by the specified temperature range.

Note 8: Gain-error and bipolar zero error specifications may be degraded

for reference input voltages less than 1.25V. See the Gain Error vs

Reference Input and Bipolar Zero vs Reference Input curves in the Typical

Performance Characteristics section.

Note 9: Guaranteed by design and not production tested.

Note 10: Internal reference on.

Note 11: I(V+) measured in ±10V span; outputs unloaded; all channels at

full scale. I(V–) measured in ±10V span; outputs unloaded; all channels

at negative full scale. Each DAC amplifier is internally loaded by a 40kΩ

feedback network, so supply currents increase as output voltages diverge

from 0V.

Note 12: Digital inputs at 0V or OVP.

Note 13: Internal reference mode. Load is 2k in parallel with 100pF

to GND.

Note 14: AVP = 5V, 0V to 5V range, internal reference mode. DAC is

stepped ±1LSB between half-scale and half-scale – 1LSB. Load is 2k in

parallel with 200pF to GND.

Note 15: DAC-to-DAC crosstalk is the glitch that appears at the output of

one DAC due to full-scale change at the output of another DAC. 0V to 10V

range with internal reference. The measured DAC is at mid-scale.

LTC2668

2668fa

For more information www.linear.com/LTC2668

typical perFormance characteristics

DNL vs Temperature Gain Error vs Temperature Bipolar Zero Error vs Temperature

Settling 5V Step Settling 10V Step

TA = 25°C, unless otherwise noted.

LTC2668-16

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

CODE

±10V RANGE

–4

INL (LSB)

–1

–2

–3

16384 32768 49152

2668 G01

65535

INL vs Output Range

CODE

–1

DNL (LSB)

–0.4

–0.2

–0.6

–0.8

0.4

0.2

0.6

0.8

16384 32768 49152

2668 G02

65535

±10V RANGE

TEMPERATURE (°C)

–40

–4

INL (LSB)

–1

–2

–3

–20 0 100

2668 G03

12060 8020 40

INL (NEG)

INL (POS)

±10V RANGE

TEMPERATURE (°C)

–40

–0.08

BZE (%FS)

–0.04

–0.02

0.02

–0.06

0.06

0.04

0.08

–20 0 100

2668 G06

12060 8020 40

±5V RANGE

±10V RANGE

±2.5V RANGE

5µs/DIV

VOLTAGE

2668 G09

0V to 10V RANGE; INTERNAL REFERENCE

RISING 10V STEP; AVERAGE OF 64 EVENTS.

FALLING SETTLING IS SIMILAR OR BETTER.

SUBTRACT 100ns FIXTURE DELAY FROM

SETTLING WAVEFORM

VOUT RESIDUAL

500µV/DIV

tSETTLE = 8.9µs

VOUT = 2V/DIV

CS/LD

TEMPERATURE (°C)

–40

–1.0

DNL (LSB)

–0.4

–0.2

0.2

–0.6

–0.8

0.6

0.4

0.8

1.0

–20 0 100

2668 G04

12060 8020 40

DNL (NEG)

DNL (POS)

±10V RANGE

TEMPERATURE (°C)

–40

–0.08

GE (%FS)

–0.04

–0.02

0.02

–0.06

0.06

0.04

0.08

–20 0 100

2668 G05

12060 8020 40

0V TO 5V RANGE

0V TO 10V RANGE

±5V RANGE

±10V RANGE

±2.5V RANGE

OUTPUT RANGE (V)

–4

INL (LSB)

–1

–2

–3

2668 G07

±2.5V

±5V

±10V

0V TO 5V

0V TO 10V

2µs/DIV

VOLTAGE

2668 G08

CS/LD

VOUT RESIDUAL

500µV/DIV

tSETTLE = 9µs

VOUT = 1V/DIV

0V to 5V RANGE; INTERNAL REFERENCE

RISING 5V STEP; AVERAGE OF 64 EVENTS.

FALLING SETTLING IS SIMILAR OR BETTER.

SUBTRACT 100ns FIXTURE DELAY FROM

SETTLING WAVEFORM

LTC2668 \\ /\ L7 HEW 9

LTC2668

2668fa

For more information www.linear.com/LTC2668

typical perFormance characteristics

Integral Nonlinearity (INL)

(LTC2668-12)

Differential Nonlinearity (DNL)

(LTC2668-12)

Single-Supply Zero-Scale Error

vs Temperature

Gain Error vs Reference Input

Bipolar Zero Error

vs Reference Input

Settling 20V Step

LTC2668-16/LTC2668-12

TA = 25°C, unless otherwise noted.

Reference Output vs Temperature Unipolar Offset vs Temperature

Headroom to V– Rail

vs Output Current

10µs/DIV

VOLTAGE

2668 G10

±10V RANGE; INTERNAL REFERENCE

RISING 20V STEP; AVERAGE OF 64 EVENTS.

FALLING SETTLING IS SIMILAR OR BETTER.

SUBTRACT 100ns FIXTURE DELAY FROM

SETTLING WAVEFORM.

tSETTLE = 20.2µs

VOUT RESIDUAL

500µV/DIV

VOUT = 5V/DIV

CS/LD

CODE

±10V RANGE

–1.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

0.4

0.2

0.6

0.8

1.0

1024 2048 3072

2668 G11

4095

CODE

–0.5

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

0.2

0.1

0.3

0.4

0.5

1024 2048 3072

2668 G12

4095

±10V RANGE

VREF (V)

0.5

–0.1

GE (%FS)

0.05

–0.05

0.10

0.15

11.5

2668 G13

3.532 2.5

±10V RANGE

16 CHANNELS

VREF (V)

0.5

–0.15

BZE (%FS)

–0.05

–0.10

0.10

11.5

2668 G14

3.532 2.5

±10V RANGE

16 CHANNELS

TEMPERATURE (°C)

–40

ZSE (mV)

–20 0 100

2668 G15

12060 8020 40

0V TO 5V RANGE

VAVP = 5V

V(V+) = 5V

V(V–) = 0V

TEMPERATURE (°C)

–40

2.494

VREF (V)

2.496

2.504

2.502

2.500

2.498

2.506

–20 0 100

2668 G16

12060 8020 40

TEMPERATURE (°C)

–40

–4

VOS (mV)

–3

–1

–2

–20 0 100

2668 G17

12060 8020 40

0V TO 10V RANGE

0V TO 5V RANGE

OUTPUT CURRENT SINKING (mA)

VOUT DELTA ABOVE V– (V)

0.2

0.8

0.6

0.4

1.0

2668 G18

106 8

0V TO 5V RANGE; V+ = 4.5V, V– = GND

±5V RANGE; V+/V– = ±4.5V

CODE: ZERO-SCALE

LTC2668 ,// I/ “IO L7HCU§QB

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typical perFormance characteristics

V+/V– Shutdown Current

vs Symmetric Supplies

IOVP Supply Current

vs Logic Voltage Hardware CLR to Mid-Scale Hardware CLR to Zero-Scale

Headroom to V+ Rail

vs Output Current

Unipolar Offset

vs Reference Input

TA = 25°C, unless otherwise noted.

LTC2668-16/LTC2668-12

Unipolar Offset

vs Reference Input

AVP Supply Current

vs Bipolar Output Voltage AVP Shutdown Current vs AVP

OUTPUT CURRENT SOURCING (mA)

3.5

VOUT (V)

3.7

4.3

4.5

3.9

4.1

4.7

–2 –4

2668 G19

–10–6 –8

0V TO 5V RANGE; V+ = 4.5V, V– = GND

±5V RANGE; V+/V– = ±4.5V

CODE: FULL-SCALE

VREF (V)

0.5

–2.0

VOS (mV)

–1.0

1.0

–1.5

1.5

0.5

2.0

11.5

2668 G20

3.532 2.5

0V TO 5V RANGE

16 CHANNELS

VREF (V)

0.5

–4

–3

VOS (mV)

–1

–2

11.5

2668 G20

3.532 2.5

0V TO 10V RANGE

16 CHANNELS

VOUT (V)

–10

IAVP (mA)

–7.5 –5 2.5

2668 G22

105–2.5 0 7.5

±10 RANGE

±5V RANGE

±2.5V RANGE

ALL CHANNELS AT SAME CODE

OUTPUTS UNLOADED

VAVP (V)

4.4

IAVP (µA)

0.2

0.8

0.4

0.6

1.0

4.6 4.8

2668 G23

5.45 5.2

V+/V– (V)

–40

V+/V– SHUTDOWN CURRENT (µA)

–30

–20

–10

2668 G24

16126 8 14

I(V+)SHUTDOWN

I(V–)SHUTDOWN

INPUT LOGIC VOLTAGE (V)

AVP = 5V

SCK, SDI, CS/LD, CLR, LDAC,

TGP TIED TOGETHER

–0.1

IOVP (mA)

0.3

0.4

0.5

0.1

0.2

0.6

2668 G25

541 2

OVP = 1.8V

OVP = 3.3V

OVP = 5V

2µs/DIV

VOUT

5V/DIV

CLR

2668 G26

FROM FULL-SCALE

FROM ZERO-SCALE

±10V RANGE

2µs/DIV

VOUT

1V/DIV

CLR

2668 G27

0V TO 5V RANGE

LTC2668 CS/LD ovp AVP 5v VW’ mv nv m 5v RANGE EnVrsTVP |N1ERNAL REFERENCE I CREE CREFwMP ”WP Vam mmwnw Ins/UN FALLWG MAJOR CARRY TRANsmoN R‘S‘MG TRANsnmN IS S‘M‘LAR 0R BETEER ALL CHANNELS ARE S‘M‘LAR 0R aEnER L7 HEW 1 1

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typical perFormance characteristics

Noise Density vs Frequency

Output 0.1Hz to 10Hz Voltage

Noise

Reference 0.1Hz to 10Hz

Voltage Noise Load Regulation

Mid-Scale Glitch Impulse DAC-to-DAC Crosstalk

Large Signal Response

TA = 25°C, unless otherwise noted.

LTC2668-16/LTC2668-12

1µs/DIV

OUT

10mV/DIV

/LD

2668 G28

FALLING MAJOR CARRY TRANSITION

RISING TRANSITION IS SIMILAR OR BETTER

ALL CHANNELS ARE SIMILAR OR BETTER

OVP, AVP: 5V

–

: ±15V

0V TO 5V RANGE

INTERNAL REFERENCE

REF

, C

REFCOMP

: 0.1µF

8nV–s TYP

1µs/DIV

OVP, AVP: 5V

V+, V–: ±15V

0V TO 10V RANGE

INTERNAL REFERENCE

CREF, CREFCOMP: 0.1µF

CS/LD

VOUT

10mV/DIV

2668 G29

SUBJECT CHANNEL: VOUT0

AGGRESSOR CHANNEL:

VOUT1 10V TO 0V STEP

VOUT1 RISING IS SIMILAR OR BETTER

ALL CHANNELS ARE SIMILAR OR BETTER

6nV-s TYP

10µs/DIV

–15

VOUT (V)

–10

–5

2668 G30

0V TO 10V RANGE

±10V RANGE

0V TO 5V RANGE

FREQUENCY (Hz)

NOISE DENSITY (nV/√Hz)

400

300

200

100

500

100 1k 10k 100k

2668 G31

1s/DIV

AVP = 5V, V+, V– = ±15V

0V TO 5V RANGE

CODE = MID-SCALE

INTERNAL REFERENCE

CREF = CREFCOMP = 0.1µF

VOUT

10µV/DIV

2668 G32

1s/DIV

AVP = 5V, V+, V– = ±15V

VREF = 2.5V

CREF = CREFCOMP = 0.1µF

VREF

10µV/DIV

2668 G33

VOUT LOAD CURRENT (mA)

–30

–10

∆VOUT (mV)

–8

–2

–6

–4

–20 –10 10

2668 G34

40200 30

0V TO 5V RANGE,

AVP, V+ = 5V, V– = GND

±10V RANGE,

AVP = 5V, V+/V– = ±15V

78µV/mA TYP

CODE: MID-SCALE

INTERNAL REF

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pin Functions

MSP2 (Pin 1): MSPAN Bit 2. Tie this pin to AVP or GND

to select the power-on span and power-on-reset code for

all 16 channels (see Table 4).

VOUT0 to VOUT15 (Pins 2-9, 23-30): DAC Analog Voltage

Outputs.

V+ (Pins 10, 31): Analog Positive Supply. Typically 15V;

4.5V to 15.75V range. Bypass to GND with a 1µF capacitor.

V– (Pins 11, 32, 41): Analog Negative Supply. Typically

–15V; –4.5V to –15.75V range, or can be tied to GND.

Bypass to GND with a 1µF capacitor unless V– is con-

nected to GND.

MUX (Pin 12): Analog Multiplexer Output. Any of the 16

DAC outputs can be internally routed to the MUX pin. When

the mux is disabled, this pin becomes high impedance.

REFLO (Pins 13, 35): Reference Low Pins. Signal ground

for all DAC channels and internal reference. These pins

should be tied to GND.

GND (Pins 14, 37): Analog Ground. Tie to a clean analog

ground plane.

LDAC (Pin 15): Active-low Asynchronous DAC Update

Pin. If CS/LD is high, a falling edge on LDAC immediately

updates all DAC registers with the contents of the input

registers (similar to a software update). If CS/LD is low

when LDAC goes low, the DAC registers are updated after

CS/LD returns high. A low on the LDAC pin powers up

the DACs. A software power-down command is ignored if

LDAC is low. Logic levels are determined by OVP.

Tie LDAC high (to OVP) if not used. Updates can then be

performed through SPI commands (see Table 1).

CS/LD (Pin 16): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

SDI into the register. When CS/LD is taken high, SCK

is disabled and the specified command (see Table 1) is

executed. Logic levels are determined by OVP.

SCK (Pin 17): Serial Interface Clock Input. Logic levels

are determined by OVP.

SDO (Pin 18): Serial Interface Data Output. The serial

output of the 32-bit shift register appears at the SDO

pin. The data transferred to the device via the SDI pin is

delayed 32 SCK rising edges before being output at the

next falling edge. Can be used for data echo readback or

daisy-chain operation (pull-up/down resistor required).

The SDO pin becomes high impedance when CS/LD is

high. Logic levels are determined by OVP.

SDI (Pin 19): Serial Interface Data Input. Data on SDI

is clocked into the DAC on the rising edge of SCK.

The LTC2668 accepts input word lengths of either 24 or

32 bits. Logic levels are determined by OVP.

TGP (Pin 20): Asynchronous Toggle Pin. A falling edge

updates the DAC register with data from input registerA.

A rising edge updates the DAC register with data from

input register B. Toggle operations only affect those DAC

channels with their toggle select bit (Tx) set to 1. Tie the

TGP pin to OVP if toggle operations are to be done through

software. Tie the TGP pin to GND if not using toggle opera-

tions. Logic levels are determined by OVP.

CLR (Pin 21): Active-low Asynchronous Clear Input. A

logic low at this level-triggered input clears the part to the

reset code and range determined by the hardwired option

chosen using the MSPAN pins and specified in Table 4.

The control registers are cleared to zero. Logic levels are

determined by OVP.

OVP (Pin 22): Digital Input/Output Supply Voltage. 1.71V ≤

OVP ≤ AVP + 0.3V. Bypass to GND with a 0.1µF capacitor.

REF (Pin 33): Reference In/Out. The voltage at the REF

pin sets the full-scale range of all channels. By default, the

internal reference is routed to this pin. Must be buffered

when driving external DC load currents. If the reference

is disabled (see Reference Modes in the Operation

section), its output is disconnected and the REF pin

becomes a high impedance input to which you may

apply a precision external reference. For low noise and

reference stability, tie a capacitor from this pin to GND.

The value must be ≤ CREFCOMP, where CREFCOMP is

the capacitance tied to the REFCOMP pin. The allow-

able external reference input voltage range is 0.5V to

VAVP – 1.75V.

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pin Functions

REFCOMP (Pin 34): Internal Reference Compensation Pin.

For low noise and reference stability, tie a 0.1µF capacitor

to GND. Tying REFCOMP to GND causes the part to power

up with the internal reference disabled, allowing the use

of an external reference at start-up.

AVP (Pin 36): Analog Supply Voltage Input. 4.5V ≤ AVP ≤

5.5V. Bypass to GND with a 1µF capacitor.

OVRTMP (Pin 38): Thermal Protection Interrupt Pin. This

open-drain N-channel output pulls low when chip tem-

perature exceeds 160°C. This pin is released on the next

CS/LD rising edge. A pull-up resistor is required.

MSP0 (Pin 39): MSPAN Bit 0. Tie this pin to AVP or GND

to select the power-on span and power-on-reset code for

all 16 channels (see Table 4).

MSP1 (Pin 40): MSPAN Bit 1. Tie this pin to AVP or GND

to select the power-on span and power-on-reset code for

all 16 channels (see Table 4).

Exposed Pad (Pin 41): Analog Negative Supply (V–). Must

be soldered to PCB.

LTC2668 L7LJCUEN2 14

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Block Diagram

RGSTR A

INTERNAL REFERENCE

RGSTR B

CONTROL LOGIC DECODE

TOGGLE SELECT REGISTERMONITOR MUX

POWER-ON RESET

RGSTR A

REFCOMP

OVRTMP

2668 BD

GND

14, 37

REFLO

13, 35 MUX

REGISTERSPAN

SPAN

DAC 0

VREF

MUX

REGISTERSPAN

SPAN

DAC 15

VREF

RGSTR ARGSTR B

RGSTR B RGSTR A

MUX

REGISTERSPAN

SPAN

DAC 7

•••

MUX

REGISTERSPAN

SPAN

DAC 8

VREF

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

CS/LD

SCK

SDI

SDO

MUX 12

REF

AVP

V+

10, 31

V–

11, 32

VOUT13

VOUT12

VOUT11

VOUT10

VOUT15

VOUT14

VOUT9

VOUT8

CLR

LDAC

TGP

MSP0

MSP1

MSP2

OVP

32-BIT SHIFT REGISTER

LTC2668 [RX VT? \ / \ YR / «J XXXX:XXXX L7HEJWEGR 1 5

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The LTC2668 is a family of 16-channel, ±10V digital-to-

analog converters with selectable output ranges and an

integrated precision reference. The DACs operate on posi-

tive 5V and bipolar ±15V supplies. The bipolar supplies can

operate as low as ±4.5V, and need not be symmetrical. In

addition, the negative V– supply can be operated at ground,

making the parts compatible with single-supply systems.

The outputs are driven by the bipolar supply rails.

The output amplifiers offer true rail-to-rail operation. When

drawing a load current from the V+ or V– rail, the output

voltage headroom with respect to that rail is limited by

the 60Ω typical channel resistance of the output devices.

See the graph, Headroom at Rails vs Output Current, in

the Typical Performance Characteristics section.

The LTC2668 is controlled using a cascadable 3-wire SPI/

Microwire-compatible interface with echo readback.

Power-On Reset

The outputs reset when power is first applied, making

system initialization consistent and repeatable. By tying

the MSPAN pins (MSP2, MSP1, MSP0) to GND and/or

AVP, you can select the initial output range and reset

code (zero- or mid-scale), as well as selecting between a

manual (fixed) range and SoftSpan operation. See Table4

for pin configurations and available options.

timing Diagram

operation

Power Supply Sequencing and Start-Up

The supplies (AVP, OVP, V+ and V–) may be powered up

in any convenient order.

If an external reference is used, the voltage at REF should

be kept within the range –0.3V ≤ VREF ≤ AVP + 0.3V (see

the Absolute Maximum Ratings section). Particular care

should be taken to observe these limits during power

supply turn-on and turn-off sequences when the voltage

at AVP is in transition.

Supply bypassing is critical to achieving the best possible

performance. We recommend at least 1μF to ground on

AVP, V+ and V– supplies, and at least 0.1μF of low ESR

capacitance for each supply, as close to the device as

possible. The larger capacitor may be omitted for OVP.

Hot-plugging or hard switching of supplies is not recom-

mended, as power supply cable or trace inductances

combined with bypass capacitances can cause supply

voltage transients beyond absolute maximum ratings,

even if the bench supply has been carefully current-/

voltage-limited. During start-up, limit the supply inrush

currents to no more than 5A and supply slew rates to no

more than 5V/µs. Internal protection circuitry can be dam-

aged and long-term reliability adversely affected if these

requirements are not met.

Figure 1. Serial Interface Timing

SDI

CS/LD

SCK

2668 F01

t10

t5t7

t3t4

1 2 3 23 24

LTC2668 2 5v WTERNAL REFERENCE 2 5v WTERNAL REFERENCE - 15v RANGE :wv RANGE :2 5V RANGE ‘I 6 L7LII‘1ENQ v tCHKCJJm

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operation

Serial Interface

When the CS/LD pin is taken low, the data on the SDI

pin is loaded into the shift register on the rising edge

of the clock (SCK pin). The 4-bit command, C3-C0, is

loaded first, followed by the 4-bit DAC address, A3-A0,

and finally the 16-bit data word in straight binary format.

For the LTC2668-16, the data word comprises the 16-bit

input code, ordered MSB-to-LSB. For the LTC2668-12,

the data word comprises the 12-bit input code, ordered

MSB-to-LSB, followed by four don’t-care bits. Data can

only be transferred to the LTC2668 when the CS/LD signal

is low. The rising edge of CS/LD ends the data transfer

and causes the device to carry out the action specified in

the 24-bit input word. The complete sequence is shown

in Figure 3a.

Table 1. Command Codes

COMMAND

C3 C2 C1 C0

0 0 0 0 Write Code to

1 0 0 0 Write Code to

All

0 1 1 0 Write Span to

1 1 1 0 Write Span to

All

0 0 0 1 Update

(Power Up)

1 0 0 1 Update

All

(Power Up)

0 0 1 1 Write Code to

, Update

(Power Up)

0 0 1 0 Write Code to

, Update

All

(Power Up)

1 0 1 0 Write Code to

All

, Update

All

(Power Up)

0 1 0 0 Power Down

0 1 0 1 Power Down Chip (All DACs, Mux and Reference)

1 0 1 1 Monitor Mux

1 1 0 0 Toggle Select

1 1 0 1 Global Toggle

0 1 1 1 Config

1 1 1 1 No Operation

Table 2. DAC Addresses,

ADDRESS

A3 A2 A1 A0

0 0 0 0 DAC 0

0 0 0 1 DAC 1

0 0 1 0 DAC 2

0 0 1 1 DAC 3

0 1 0 0 DAC 4

0 1 0 1 DAC 5

0 1 1 0 DAC 6

0 1 1 1 DAC 7

1 0 0 0 DAC 8

1 0 0 1 DAC 9

1 0 1 0 DAC 10

1 0 1 1 DAC 11

1 1 0 0 DAC 12

1 1 0 1 DAC 13

1 1 1 0 DAC 14

1 1 1 1 DAC 15

Data Transfer Functions

The DAC input-to-output transfer functions for all output

ranges and resolutions are shown in Figures 2a and 2b.

The input code is in straight binary format for all ranges.

STRAIGHT BINARY CODE (DECIMAL EQUIVALENT)

2.5V INTERNAL REFERENCE

–10

VOUT (V)

–2.5

–5

–7.5

2.5

7.5

16384 32768 49152

2668 F01a

65535

0V TO 5V RANGE

0V TO 10V RANGE

±5V RANGE

±10V RANGE

±2.5V RANGE

STRAIGHT BINARY CODE (DECIMAL EQUIVALENT)

2.5V INTERNAL REFERENCE

–10

VOUT (V)

–2.5

–5

–7.5

2.5

7.5

1024 2048 3072

2668 F02b

4095

0V TO 5V RANGE

0V TO 10V RANGE

±5V RANGE

±10V RANGE

±2.5V RANGE

Figure 2a. LTC2668-16 Transfer Function

Figure 2b. LTC2668-12 Transfer Function

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12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX

CS/LD

SCK

SDI

COMMAND WORD ADDRESS WORD DATA WORD

DON’T CARE

32-BIT INPUT WORD

C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX

SDO

CURRENT

32-BIT

INPUT WORD

(HI-Z)(HI-Z)

2668 F03b

PREVIOUS 32-BIT INPUT WORD

t3t4

D15

SCK

SDI

SDO PREVIOUS D14PREVIOUS D15

D14

3a. LTC2668-16 24-Bit Load Sequence (Minimum Input Word).

LTC2668-12 SDI Data Word Is 12-Bit Input Code + 4 Don’t-Care Bits

3b. LTC2668-16 32-Bit Load Sequence.

LTC2668-12 SDI/SDO Data Word Is 12-Bit Input Code + 4 Don’t-Care Bits

Figure 3. LTC2668 Load Sequences

operation

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3

CS/LD

SCK

SDI

COMMAND WORD ADDRESS WORD DATA WORD

24-BIT INPUT WORD

2668 F03a

LTc2668 W

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Figure 4. Write Span Syntax

operation

While the minimum input word is 24 bits, it may option-

ally be extended to 32 bits. To use the 32-bit word width,

8 don’t-care bits must be transferred to the device first,

followed by the 24-bit word, as just described. Figure 3b

shows the 32-bit sequence. The 32-bit word is required

for echo readback and daisy-chain operation, and is also

available to accommodate processors that have a minimum

word width of 16 or more bits.

Input and DAC Registers

The LTC2668 has five internal registers for each DAC, in

addition to the main shift register (see the Block Diagram).

Each DAC channel has two sets of double-buffered reg-

isters: one set for the code data, and one set for the span

(output range) of the DAC. Double buffering provides the

capability to simultaneously update the span and code,

which allows smooth voltage transitions when changing

output ranges. It also permits the simultaneous updating

of multiple DACs.

Each set of double-buffered registers comprises an input

• Input Register: The write operation shifts data from the

SDI pin into a chosen input register. The input registers

are holding buffers; write operations do not affect the

DAC outputs.

In the code data path, there are two input registers, A

and B, for each DAC register. Register B is an alternate

input register used only in the toggle operation, while

Diagram).

• DAC Register: The update operation copies the contents

of an input register to its associated DAC register. The

content of a DAC register directly controls the DAC

output voltage or range. The update operation also

powers up the selected DAC if it had been in power-

down mode. The data path and registers are shown in

the Block Diagram.

Note that updates always refresh both code and span

data, but the values held in the DAC registers remain

unchanged unless the associated input register values

have been changed via a write operation. For example, if

you write a new code and update the channel, the code

is updated, while the span is refreshed unchanged. A

channel update can come from a serial update com-

mand, an LDAC negative pulse, or a toggle operation.

Table 3. Write Span Code

S2 S1 S0

OUTPUT RANGE

INTERNAL REFERENCE EXTERNAL REFERENCE

0 0 0 0V TO 5V 0V to 2VREF

0 0 1 0V to 10V 0V to 4VREF

0 1 0 ±5V ±2VREF

0 1 1 ±10V ±4VREF

1 0 0 ±2.5V ±VREF

Output Ranges

The LTC2668 is a 16-channel DAC with selectable output

ranges. Ranges can either be programmed in software or

hardwired through pin strapping.

SoftSpan Operation

SoftSpan operation (ranges controlled through the serial

interface) is invoked by tying all three MSPAN pins (MSP2,

MSP1 and MSP0) to AVP (see Table 4). In SoftSpan con-

figuration, all channels initialize to zero-scale in 0V to 5V

range at power-on. The range and code of each channel

are then fully programmable.

Each channel has a set of double-buffered registers for

range information (see the Block Diagram). Program the

span input register using the

Write Span n

Write Span All

commands (0110b and 1110b, respectively). Figure 4 shows

the syntax, and Table 3 shows the span codes and ranges.

As with the double-buffered code registers, update opera-

tions copy the span input registers to the associated span

DAC registers.

2668 F04

0 1 1 0 A3 A2 A1 A0 X X X X X X X X X X X X X S2 S1 S0

DON’T CAREADDRESS SPAN CODEWRITE SPAN COMMAND

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Manual Span Operation

Multiple output ranges are not needed in all applications.

By tying the MSPAN pins (MSP2, MSP1 and MSP0) to GND

and/or AVP, any output range can be hardware-configured

without additional operational overhead. Zero-scale and

mid-scale reset options are also available for the unipolar

modes (see Table 4).

Table 4. MSPAN Pin Configurations

MSP2 MSP1 MSP0

OUTPUT

RANGE

RESET

CODE

MANUAL

SPAN

SOFT-

SPAN

0 0 0 ±10V Mid-Scale X

0 0 AVP ±5V Mid-Scale X

0AVP 0 ±2.5V Mid-Scale X

0AVP AVP 0V to 10V Zero-Scale X

AVP 0 0 0V to 10V Mid-Scale X

AVP 0AVP 0V to 5V Zero-Scale X

AVP AVP 0 0V to 5V Mid-Scale X

AVP AVP AVP 0V to 5V Zero-Scale X

Monitor Mux

The LTC2668 includes a high voltage multiplexer (mux)

for surveying the channel outputs.

The MUX pin is intended for use with high impedance

inputs only; the output impedance of the multiplexer is

2.2kΩ. Continuous DC output current at the MUX pin must

be limited to ±1mA to avoid damaging internal circuits.

The output voltage range of the multiplexer is from V– to

V+ – 1.4V. The output is disabled (high impedance) at

power-up.

The syntax and codes for the

Mux

command are shown

in Figure 5 and Table 5.

Table 5. Monitor Mux Control Codes

M4 M3 M2 M1 M0 MUX PIN OUTPUT

0 0 0 0 0 Disabled (Hi-Z)

1 0 0 0 0 VOUT0

1 0 0 0 1 VOUT1

1 0 0 1 0 VOUT2

1 0 0 1 1 VOUT3

1 0 1 0 0 VOUT4

1 0 1 0 1 VOUT5

1 0 1 1 0 VOUT6

1 0 1 1 1 VOUT7

1 1 0 0 0 VOUT8

1 1 0 0 1 VOUT9

1 1 0 1 0 VOUT10

1 1 0 1 1 VOUT11

1 1 1 0 0 VOUT12

1 1 1 0 1 VOUT13

1 1 1 1 0 VOUT14

1 1 1 1 1 VOUT15

Toggle Operations

Some systems require that DAC outputs switch repetitively

between two voltage levels. Examples include introducing

a small AC bias, or independently switching between ‘on’

and ‘off’ states. The LTC2668 toggle function facilitates

these kinds of operations by providing two input registers

(A and B) per DAC channel.

Toggling between A and B is controlled by three signals.

The first of these is the toggle select command, which acts

on a data field of 16 bits, each of which controls a single

channel (see Figure 6). The second is the global toggle

command, which controls all selected channels using the

global toggle bit TGB (see Figure 7). Finally, the TGP pin

operation

Figure 5. Mux Command

2668 F05

1 0 1 1 X X X X X X X X X X X X X X X M4 M3 M2 M1 M0

DON’T CARE MUX CONTROL CODEMUX COMMAND

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operation

Figure 6. Toggle Select Syntax

Figure 7. Global Toggle Syntax

allows the use of an external clock or logic signal to toggle

the DAC outputs between A and B. The signals from these

controls are combined as shown in Figure 8.

If the toggle function is not needed, tie TGP (Pin 20) to

ground and leave the toggle select register in its power-on

reset state (cleared to zero). Input registers A then function

as the sole input registers, and registers B are not used.

Toggle Select Register (TSR)

The Toggle Select command (1100b) syntax is shown in

Figure 6. Each bit in the 16-bit TSR data field controls the

DAC channel of the same name: T0 controls channel 0,

T1 channel 1,…, and Tx controls channel x.

The toggle select bits (T0, T1,..., T15) have a dual function.

First, each toggle select bit controls which input register

(A or B) receives data from a write-code operation. When

the toggle select bit of a given channel is high, write-code

operations are directed to input register B of the addressed

channel. When the bit is low, write-code operations are

directed to input register A.

Secondly, each toggle select bit enables the corresponding

channel for a toggle operation.

Writing to Input Registers A and B

Having chosen channels to toggle, write the desired codes

to Input registers A for the chosen channels; then set

the channels’ toggle select bits using the toggle select

command; and finally, write the desired codes to input

registers B. Once these steps are completed, the channels

are ready to toggle. For example, to set up channel 3 to

toggle between codes 4096 and 4200:

1) Write code channel 3 (code = 4096) to register A

00000011 00010000 00000000

2) Toggle Select (set bit T3)

11000000 00000000 00001000

3) Write code channel 3 (code = 4200) to register B

00000011 00010000 01101000

The Write code of step (3) is directed to register B because

in step (2), bit T3 was set to 1. Channel 3 now has Input

registers A and B holding the two desired codes, and is

prepared for the toggle operation.

Toggling Between Registers A and B

Once Input registers A and B have been written to for all

desired channels and the corresponding toggle select bits

are set high, as in the previous example, the channels are

ready for toggling.

2668 F06

LSBMSB

1 1 0 0 X X X X T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

TOGGLE SELECT BITS (16 BITS, ONE FOR EACH CHANNEL)DON’T CARETOGGLE SELECT

2668 F07

1101XXXXXXXXXXXXXXXXXXXTGB

GLOBAL

TOGGLE

BITDON’T CARE

GLOBAL

TOGGLE COMMAND

LTC2668 3‘“ w J'L N w A w > 3‘“ ﬂ :1 IL L 3 un— Elllﬁl=lﬁlﬁlaltlEIEIEIEIEISIE II]- 0 i) i i u L7 LJUW 2 1

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For more information www.linear.com/LTC2668

operation

The LTC2668 supports three types of toggle operations:

a first in which all selected channels are toggled together

using the SPI port; a second in which all selected channels

are toggled together using an external clock or logic signal;

and a third in which any combination of channels can be

instructed to update from either input register A or B.

The internal toggle-update circuit is edge triggered, so

only transitions (of TGB or TGP) trigger an update from

the respective input register.

To toggle all selected channels together using the SPI port,

ensure the TGP pin is high and that the bits in the toggle

select register corresponding to the desired channels are

also high. Use the global toggle command (1101b) to

alternate codes, sequentially changing the global toggle

bit TGB (see Figure 7). Changing TGB from 1 to 0 updates

the DAC registers from their respective input registers

A. Changing TGB from 0 to 1 updates the DAC registers

from their respective input registers B. Note that in this

way up to 16 channels may be toggled with just one se-

rial command.

To toggle all selected channels using an external logic

signal, ensure that the TGB bit in the global toggle register

is high and that in the toggle select register, the bits cor-

responding to the desired channels are also high. Apply

a clock or logic signal to the TGP pin to alternate codes.

TGP falling edges update the DAC registers from their

associated input registers A. TGP rising edges update

the DAC registers from their associated input registers B.

Note that once the input registers are set up, all toggling

is triggered by the signal applied to the TGP pin, with no

further SPI instructions needed.

To cause any combination of channels to update from

either input register A or B, ensure the TGP pin is high

and that the TGB bit in the global toggle register is also

high. Using the toggle select command, set the toggle

select bits as needed to select the input register (A or B)

with which each channel is to be updated. Then update all

channels, either by using the serial command (1001b) or

by applying a negative pulse to the LDAC pin. Any channels

whose toggle select bits are 0 update from input register

Figure 8. Simplified Toggle Block Diagram. Conceptual Only, Actual Circuit May Differ

2668 F08

TOGGLE SELECT BIT T15

16 16

UPD

CS/LDSCK

SDI

LDAC 15

TGP

TGB

32-BIT SHIFT REGISTER

LOGIC

16-BIT TOGGLE SELECT REGISTER

ONE Tx BIT PER CHANNEL

T10

T11

T12

T13

T14

T15

GLOBAL TOGGLE

BIT (TGB)

INPUT REGISTER B

(16 BIT)

INPUT REGISTER A

(16 BIT)

A/B

MUX DAC REGISTER 16-BIT

SOFTSPAN DAC

1617

LTC2668

CHANNEL 15

LTC2668 22 L7ELUEN2

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For more information www.linear.com/LTC2668

operation

A, while channels whose toggle select bits are 1 update

from input register B (see Figure 8). By alternating toggle-

select and update operations, up to 16 channels can be

simultaneously switched to A or B as needed.

Daisy-Chain Operation

The serial output of the shift register appears at the SDO

pin. Data transferred to the device from the SDI input is

delayed 32 SCK rising edges before being output at the

next SCK falling edge, suitable for clocking into the mi-

croprocessor on the next 32 SCK rising edges.

The SDO output can be used to facilitate control of multiple

serial devices from a single 3-wire serial port (i.e., SCK,

SDI and CS/LD). Such a daisy-chain series is configured

by connecting the SDO of each upstream device to the SDI

of the next device in the chain. The shift registers of the

devices are thus connected in series, effectively forming a

single input shift register which extends through the entire

chain. Because of this, the devices can be addressed and

controlled individually by simply concatenating their input

words; the first instruction addresses the last device in

the chain and so forth. The SCK and CS/LD signals are

common to all devices in the series.

In use, CS/LD is first taken low. Then, the concatenated

input data is transferred to the chain, using the SDI of the

first device as the data input. When the data transfer is

complete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the

No-Operation

command

(1111) for all other devices in the chain.

When CS/LD is taken high, the SDO pin presents a high

impedance output, so a pull-up resistor is required at

the SDO of each device (except the last) for daisy-chain

operation.

Echo Readback

The SDO pin can be used to verify data transfer to the

device. During each 32-bit instruction cycle, SDO outputs

the previous 32-bit instruction for verification.

When CS/LD is high, SDO presents a high impedance

output, releasing the bus for use by other SPI devices.

Power-Down Mode

For power-constrained applications, power-down mode can

be used to reduce the supply current whenever less than

sixteen DAC outputs are needed. When in power-down,

the output amplifiers and reference buffers are disabled.

The DAC outputs are put into a high impedance state, and

the output pins are passively pulled to ground through

individual 42k (minimum) resistors. Register contents

are not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combina-

tion with the appropriate DAC address. In addition, all the

DAC channels and the integrated reference together can be

put into power-down mode using the

Power-Down Chip

command, 0101b. The 16-bit data word is ignored for all

power-down commands.

Normal operation resumes by executing any command

which includes a DAC update—either in software, as

shown in Table 1, by taking the asynchronous LDAC pin

low, or by toggling (see the Types of Toggle Operations

section). The selected DAC is powered up as its voltage

output is updated. When updating a powered-down DAC,

add wait time to accommodate the extra power-up delay. If

the channels have been powered down (command 0100b)

prior to the update command, the power-up delay time is

30μs. If, on the other hand, the chip has been powered

down (command 0101b), the power-up delay time is 35μs.

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 1, the

asynchronous, active-low LDAC pin updates all 16 DAC

registers with the contents of the input registers.

If CS/LD is high, a low on the LDAC pin causes all DAC

registers to be updated with the contents of the input

registers.

If CS/LD is low, a low-going pulse on the LDAC pin be-

fore the rising edge of CS/LD powers up all DAC outputs,

but does not cause the outputs to be updated. If LDAC

remains low after the rising edge of CS/LD, then LDAC is

recognized, the command specified in the 24-bit word is

executed and the DAC outputs are updated.

LTC2668 W L7HEJWEGR 23

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For more information www.linear.com/LTC2668

operation

The DAC outputs are powered up when LDAC is taken low,

independent of the state of CS/LD.

If LDAC is low at the time CS/LD goes high, any software

power-down command (power down

, power-down chip,

config/select external reference) that was specified in the

input word is inhibited.

Reference Modes

The LTC2668 has two reference modes (internal and ex-

ternal) with which the reference source can be selected.

In either mode, the voltage at the REF pin and the output

range settings determine the full-scale voltage of each of

the channels.

The device has a precision 2.5V integrated reference with

a typical temperature drift of 2ppm/°C. To use the internal

reference, the REFCOMP pin should be left floating (no

DC path to ground). In addition, the RD bit in the config

power-up, or it can be reset using the

Config

command,

0111b. Figure 9 shows the command syntax.

A buffer is needed if the internal reference is to drive exter-

nal circuitry. For reference stability and low noise, a 0.1μF

capacitor should be tied between REFCOMP and GND. In

this configuration, the internal reference can drive up to

0.1μF with excellent stability. In order to ensure stable

operation, the capacitive load on the REF pin should not

exceed that on the REFCOMP pin.

To use an external reference, tie the REFCOMP pin to

ground. This disables the output of the internal reference

at start-up, so that the REF pin becomes a high impedance

input. Apply the desired reference voltage at the REF pin

after powering up, and set the RD bit to 1 using the

Config

command (0111b). This reduces AVP supply current by

approximately 200µA.

The acceptable external reference voltage range is:

0.5V ≤ VREF ≤ AVP – 1.75V.

Integrated Reference Buffers

Each channel has its own integrated high performance

reference buffer. The buffers have very high input imped-

ance and do not load the reference voltage source. These

buffers shield the reference voltage from glitches caused by

DAC switching and, thus, minimize DAC-to-DAC dynamic

crosstalk. Typically DAC-to-DAC crosstalk is less than

6nV•s (0V to 10V range). See the DAC-to-DAC Crosstalk

graph in the Typical Performance Characteristics section.

Voltage Outputs

An amplifier’s ability to maintain its rated voltage accuracy

over a wide range of load conditions is characterized in its

load regulation specification. The change in output voltage

is measured per milliampere of forced load current change.

Each of the LTC2668's high voltage, rail-to-rail output

amplifiers has guaranteed load regulation when sourcing

or sinking up to 10mA with supply headroom as low as

1.4V. Additionally, the amplifiers can drive up to ±14mA

if available headroom is increased to 2.2V or more.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from µV/mA to ohms. The amplifier’s DC output

impedance is typically 0.08Ω when driving a load well

away from the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by the

60Ω typical channel resistance of the output devices—

e.g., when sinking 1mA, the minimum output voltage

(above V–) is 60Ω • 1mA = 60mV. See the Headroom at

Rails vs Output Current graphs in the Typical Performance

Characteristics section.

Figure 9. Config Command Syntax—Thermal Shutdown (TS) and Reference Disable (RD)

2668 F09

0111XXXXXXXXXXXXXXXXXXTSRD

CONFIG

BITS

DON’T CARECONFIG COMMAND

LTc2668

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For more information www.linear.com/LTC2668

operation

The amplifiers are stable driving capacitive loads of up

to 1000pF.

Thermal Overload Protection

The LTC2668 protects itself if the die temperature exceeds

160°C. All channels power down, and the open-drain

OVRTMP interrupt pin pulls low. The reference and bias

circuits stay powered on. Once triggered, the device stays

in shutdown even after the die cools.

The temperature of the die must fall to approximately 150°C

before the channels can be returned to normal operation.

Once the part has cooled sufficiently, the shutdown can be

cleared with any valid update operation, including LDAC

or a toggle operation. A CS/LD rising edge releases the

OVRTMP pin regardless of the die temperature.

Since the total load current of the device can easily exceed

100mA, die heating potential of the system design should

be evaluated carefully. Grounded loads as low as 1k may

be used and will not result in excessive heat.

Thermal protection can be disabled by using the

Config

command to set the TS bit (see Figure 9).

Board Layout

The excellent load regulation and DC crosstalk perfor-

mance of these devices is achieved in part by minimizing

common-mode resistance of signal and power grounds.

As with any high resolution converter, clean board ground-

ing is important. A low impedance analog ground plane

is necessary, as are star-grounding techniques. Keep the

board layer used for star ground continuous to minimize

ground resistances; that is, use the star-ground concept

without using separate star traces. Resistance from the

REFLO pin to the star point should be as low as possible.

For best performance, stitch the ground plane with arrays

of vias on 150 to 200 mil centers connecting it with the

ground pours from the other board layers. This reduces

overall ground resistance and minimizes ground loop area.

Using LTC2668 in 5V Single-Supply Systems

LTC2668 can be used in single-supply systems simply by

connecting the V– pins to ground along with REFLO and

GND, while V+ and AVP are connected to a 5V supply. OVP

can be connected to the 5V supply or to the logic supply

voltage if lower than 5V.

With the internal reference, use the 0V to 5V output

range. As with any rail-to-rail device, the output is

limited to voltages within the supply range. Since the

outputs of the device cannot go below ground, they may

limit at the lowest codes, as shown in Figure 10b. Simi-

larly, limiting can occur near full-scale if full-scale error

(FSE = VOS + GE) is positive, or if V+ < 2 • VREF. See

Figure 10c.

The multiplexer can be used and is fully functional. It can

pull all the way to ground, but the upper headroom limita-

tion means that it is useful for output voltages of 3.6V or

below only (V+ = 5V).

More flexibility can be afforded by using an external refer-

ence. For example, by using a 1.25V reference such as the

LTC6655, we can now select between 0x to 2x and 0x to

4x ranges, which give full-scale voltages of 2.5V and 5V,

respectively. Furthermore, the part can be configured for

reset to zero- or mid-scale codes (see the Output Ranges

section).

L7 LJUW 25

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For more information www.linear.com/LTC2668

operation

Figure 10. Effects of 0V to 5V Output Range for Single-Supply Operation. (10a) Overall Transfer Function

(10b) Effect of Negative Offset for Codes Near Zero-Scale (10c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

2668 F10

INPUT CODE

(10b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

32,7680 65,535

INPUT CODE

OUTPUT

VOLTAGE

(10a)

V+ = 2VREF = 5V

(10c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

V– = VREFLO = 0V

LTC2668 1 rﬁﬁﬁﬁﬁmﬁﬁﬁf’ a; +1 3 E 1 E”: a: 1 =9 ********** * E: 1 a =11 33 EL Liﬂﬂﬂiﬂﬂﬂﬂﬁlﬂiik ' , 1 1 11 1—1 1 1 is O 1 UUUWUUUUEj 1 3 C 1 g E 7 777777777 T 7777777777 '5 777777777 E 7 1 3 C 1 3 E 1 1 C 1 mmnmmmm ‘ t1: ﬁt 26 L7ELUEN2

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package Description

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

6.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1 NOTCH

R = 0.45 OR

0.35 × 45°

CHAMFER

0.40 ±0.10

4039

BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES)

4.42 ±0.10

4.42 ±0.05

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UJ40) QFN REV Ø 0406

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

4.50 ±0.05

(4 SIDES)

5.10 ±0.05

6.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

R = 0.10

TYP

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

LTC2668 L7HEJWEGR 27

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For more information www.linear.com/LTC2668

revision history

REV DATE DESCRIPTION PAGE NUMBER

A 7/15 Updated V– and glitch impulse in the Electrical Characteristics section.

Replaced Mid-Scale Glitch Impulse graph.

Edited the Power Supply Sequencing and Start-Up section.

Updated VOUT output voltage swing conditions.

Fixed AVP pin on schematic (pin 36).

LTC2668 28 L7ELUEN2

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For more information www.linear.com/LTC2668

 LINEAR TECHNOLOGY CORPORATION 2014

LT 0715 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2668

relateD parts

typical application

PART NUMBER DESCRIPTION COMMENTS

LTC2704 Quad Serial 16-/14-/12-Bit VOUT SoftSpan DACs with ±2LSB

INL, ±1LSB DNL

Software Programmable Output Ranges Up to ±10V, SPI Interface,

No External Amps Needed

LTC2754 Quad Serial 16-/12-Bit IOUT SoftSpan DACs with ±1LSB INL,

±1LSB DNL

Software Programmable Output Ranges Up to ±10V, SPI Interface,

7mm × 8mm QFN Package

LTC2656 Octal Serial 16-/12- Bit VOUT DACs with Internal Reference ±10ppm/°C Internal Reference, 4mm × 5mm QFN Package

LTC2636 Octal 12-/10-/8-Bit SPI VOUT DACs with Internal Reference ±10ppm/°C Internal Reference, 4mm × 3mm DFN and 16-Lead MSOP

Packages

References

LTC6655A Low Drift Precision Buffered Reference 0.025% Max Tolerance, 2ppm/°C Max, 0.25ppmP-P 0.1Hz to 10Hz Noise

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

MUX

OVRTMP

MSP0

MSP1

MSP2

LDAC

TGP

CLR

SDI

CS/LD

SDO

SCK

–

0.1µF

DAC

OUTPUTS

0.1µF

6 4

2 15 1

7 8 3, 16

15V

–15V

IN+

IN–

0.1µF0.1µF

2668 TA02

47µF

VDD

OVDD VDDLBYP

REFBUF

LTC2328-18

LT1468

LTC2668-16

REFIN GND

0.1µF 10µF

2×

10µF

2×

0.1µF

SDO

SCK

RDL/SDI

BUSY

CNV

CHAIN

OVP

AVP

REFLO

GND

REFCOMP

REF

V–

PAD

V+

0.1µF

344132,

14,

1335

0.1µF

–15V

1µF

0.1µF

1µF 0.1µF

15V

1µF

22 36 31, 10

SDI

CS1

CS2

SCK

SDO

MICROCONTROLLER

Using the Analog Multiplexer to Measure DAC Output Voltages Up to ±10.24V.

Independent ADC Reference Cross-Checks LTC2668 Internal Reference

Analog Devices Inc. 的 LTC2668 规格书

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