Microchip Technology 的 ATF1502AS,ASL 规格书

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Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Features
High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
̶32 Macrocells
̶5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
̶44 Pins
̶7.5ns Maximum Pin-to-pin Delay
̶Registered Operation up to 125MHz
̶Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
̶D/T Latch Configurable Flip-flops
̶Global and Individual Register Control Signals
̶Global and Individual Output Enable
̶Programmable Output Slew Rate
̶Programmable Output Open Collector Option
̶Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
̶Automatic 10μA Standby for “L” Version
̶Pin-controlled 1mA Standby Mode
̶Programmable Pin-keeper Inputs and I/Os
̶Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and 44-lead TQFP
Advanced EEPROM Technology
̶100% Tested
̶Completely Reprogrammable
̶10,000 Program/Erase Cycles
̶20 Year Data Retention
̶2000V ESD Protection
̶200mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993
Supported
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-fee/RoHS Compliant) Package Options
ATF1502AS and ATF1502ASL
High-performance EEPROM
Complex Programmable Logic Device
DATASHEET
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ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
2
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (“L” Versions)
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
VCC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
̶Input Transition Detection
̶Power-down (“L” Versions)
̶Individual Macrocell Power Option
̶Disable ITD on Global Clocks, Inputs, and I/O
Description
The Atmel® ATF1502AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD)
which utilizes the Atmel proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it
easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1502AS(L)’s enhanced
routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1502AS(L) has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of
device package selected. Each dedicated pin can serve as a global control signal, register clock, register reset,
or output enable. Each of these control signals can be selected for use individually within each macrocell.
Each of the 32 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin
also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the
global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic
between macrocells in the ATF1502AS(L) allows fast, efficient generation of complex logic functions. The
ATF1502AS(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to
40 product terms.
The ATF1502AS(L) macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions
operating at high speed. The macrocell consists of five sections:
Product Terms and Product Term Select Multiplexer
OR/XOR/CASCADE Logic
Flip-flop
Output Select and Enable
Logic Array Inputs
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ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Figure 1. ATF1502AS(L) Macrocell
SWITCH
MATRIX
OUTPUTS
REGIONAL
FOLDBACK
BUS
LOGIC
FOLDBACK CASIN
GLOBAL BUS
CASOUT MACROCELL REDUCED POWER BIT
OPEN COLLECTOR
OPTION
SLEW
RATE
MOE
GOE[0:5]
PTMUX
GCLEAR-
GCK[0:2]
I/O Pin I/O Pin
SWITCH
MATRIX
33333333333 33333333333
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
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1. Pin Configurations and Pinouts
Figure 1-1. Pinouts
44-lead TQFP
Top View
44-lead PLCC
Top View
44-lead TQFP
(Top View) 44-lead PLCC
(Top View)
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
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ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
2. Block Diagram
Figure 2-1. Block Diagram
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security
fuse, when programmed, protects the contents of the ATF1502AS(L). Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision, or date. The User
Signature is accessible regardless of the state of the security fuse.
The ATF1502AS(L) device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin
JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Description Language
(BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition
to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
Logic Block B
Macrocells
1 to 16
Global
Clock
Mux
Global
Clear
Mux
INPUT/GCLR
INPUT/OE2/GCLK2
INPUT/GCLK1
I/O (MC32)/GCLK3
GCK[0:2]
GCLEAR
GOE[0:5]
Logic Block A
I/O Pins
OE1/INPUT
GLOBAL
BUS
(INPUTS and FEEDBACKS BUS)
Switch
Matrix
Regional
Foldbacks
Output
Enable
Switch
Matrix
GOE[0:5]
GCK[0:2]
GCLEAR
GCK[0:2]
GOE[0:5]
GCLEAR
I/O Pins
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ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
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3. Macrocell Sections
Table 3-1. Macrocell Sections
Section Description
Product Terms and
Select Mux
Each ATF1502AS(L) macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The Product Term Select Multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX programming is determined by the design
compiler, which selects the optimum macrocell configuration.
OR/XOR/CASCADE
Logic
The ATF1502AS(L) logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity
selection. For registered functions, the fixed levels allow DeMorgan minimization of product
terms. The XOR gate is also used to emulate T-type and JK-type flip-flops.
Flip-flop
The ATF1502AS(L) flip-flop has very flexible data and control functions. The data input can come
from either the XOR gate, from a separate product term, or directly from the I/O pin. Selecting the
separate product term allows creation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically implemented by the fitter software). In addition to
D, T, JK, and SR operation, the flip-flop can be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched when the clock is low.
The clock itself can be either one of the Global CLK signals (GCK[0:2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s Asynchronous Reset (AR) signal can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
Asynchronous Preset (AP) can be a product term or always off.
Extra Feedback
The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The extra
buried feedback signal can be either combinatorial or a registered signal regardless of whether
the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the
creation of a second latch within a macrocell.
I/O Control: The Output Enable Multiplexer (MOE) controls the output enable signal.
Each I/O can be individually configured as an input, output, or for bi-directional
operation. The output enable for each macrocell can be selected from the true or
compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O
macrocells. This selection is automatically done by the fitter software when the I/O is
configured as an input, all macrocell resources are still available, including the buried
feedback, expander, and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from all
32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the
global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The four foldback terms in each region allow generation of high fan-in sum terms
(up to nine product terms) with little additional delay.
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ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
4. Programmable Pin-keeper Option for Inputs and I/Os
The ATF1502AS(L) offers the option of programming all input and I/O pins so the pin-keeper circuits can be
utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or
low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which
causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external
pull-up resistors and eliminate their DC power consumption.
Figure 4-1. Input Diagram
Figure 4-2. I/O Diagram
Input
ESD
Protection
Circuit
VCC
Programmable
Option
100K
VCC
OE
Data
Programmable
Option
I/O
VCC
100K
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ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
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5. Speed/Power Management
The ATF1502AS(L) has several built-in speed and power management features. The ATF1502AS(L) contains
circuitry which automatically puts the device into a low-power standby mode when no logic transitions are occurring.
This not only reduces power consumption during inactive periods, but also provides proportional power savings for
most applications running at system speeds below 50MHz. This feature may be selected as a design option.
To further reduce power, each ATF1502AS(L) macrocell has a reduced-power bit feature. This feature allows
individual macrocells to be configured for maximum power savings. This feature may be selected as a design
option.
The ATF1502AS(L) also has an optional power-down mode. In this mode, current drops to below 10mA. When
the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The
power-down option is selected in the design source file. When enabled, the device goes into power-down when
either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1
or PD2 pin cannot be used as a logic input or output; however, the pin’s macrocell may still be used to generate
buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder,
tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH, and tSEXP.
The ATF1502AS(L) macrocell also has an option whereby the power can be reduced on a per-macrocell basis.
By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby
reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by slowing down
outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified
as fast switching in the design file.
6. Design Software Support
ATF1502AS(L) designs are supported by several third-party tools. Automated fitters allow logic synthesis using
a variety of high-level description languages and formats.
7. Power-up Reset
The ATF1502AS(L) is designed with a power-up reset, a feature critical for state machine initialization. At a
point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will
depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how
VCC actually rises in the system, the following conditions are required:
The VCC rise must be monotonic,
After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and,
The clock must remain stable during TD.
The ATF1502AS(L) has two options for the hysteresis about the reset level, VRST, Small and Large. During the
fitting process, users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel
POF2JED users may select the Large option by including the flag “-power_reset” on the command line after
“filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the
following condition is added:
If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced by several hundred micro amps as well.
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Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
8. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1502AS(L) fuse patterns. Once
programmed, fuse verify is inhibited; however, the 16-bit User Signature remains accessible.
9. Programming
ATF1502AS(L) devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This
capability eliminates package handling normally required for programming and facilitates rapid design iterations
and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1502AS(L) via the PC. ISP is
performed by using either a download cable, a comparable board tester, or a simple microprocessor interface.
When using the ISP hardware or software to program the ATF1502AS(L) devices, four I/O pins must be
reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O
pins are still available to the design for burned logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF)
files can be created by Atmel-provided software utilities.
ATF1502AS(L) devices can also be programmed using standard third-party programmers. With a third-party
programmer, the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
10. ISP Programming Protection
The ATF1502AS(L) has a special feature which locks the device and prevents the inputs and I/O from driving if
the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a
condition. In addition, the pin-keeper option preserves the previous state of the input and I/O PMS during
programming.
All ATF1502AS(L) devices are initially shipped in the erased state, thereby making them ready to use for ISP.
Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
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ATF1502AS(L) [DATASHEET]
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11. Electrical Characteristics
11.1 Absolute Maximum Ratings*
Note: 1. Minimum voltage is -0.6VDC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin
voltage is VCC + 0.75VDC, which may overshoot to 7.0V for pulses of less than 20ns.
11.2 Pin Capacitance
Table 11-1. Pin Capacitance(1)
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12pF.
11.3 DC and AC Operating Conditions
Table 11-2. DC and AC Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Any Pin with
Respect to Ground . . . . . . . . . . . . . . . . . . . . . -2.0V to +7.0V(1)
Voltage on Input Pins with Respect
to Ground During Programming . . . . . . . . . . -2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground . . . . . . . . . . . . . . . . . . . . -2.0V to +14.0V(1)
*Notice: Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is a
stress rating only and functional operation of
the device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Typ Max Units Conditions
CIN 8 10 pF VIN = 0V; f = 1MHz
CI/O 8 10 pF VOUT = 0V; f = 1MHz
Commercial Industrial
Operating Temperature (Ambient) 0C to 70C -40C to 85C
VCC (5.0V) Power Supply 5V± 5% 5V± 10%
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11.4 DC Characteristics
Table 11-3. DC Characteristics
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30s.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on.
Symbol Parameter Condition Min Typ Max Units
IIL
Input or I/O Low
Leakage Current VIN = VCC -2 -10 μA
IIH
Input or I/O High
Leakage Current 2 10
IOZ
Tri-state Output
Off-state Current VO = VCC or GND -40 40 μA
ICC1
Power Supply Current,
Standby
VCC = Max
VIN = 0, VCC
Std Mode
Com. 60 mA
Ind. 75 mA
“L” Mode
Com. 10 μA
Ind. 10 μA
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode 1 5 mA
ICC3(2) Reduced-power Mode
Supply Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode
Com. 35 mA
Ind. 40 mA
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 2.0 VCCIO + 0.3 V
VOL
Output Low Voltage (TTL) VIN = VIH or VIL
VCC = Min, IOL = 12mA
Com. 3.0 0.45 V
Ind. 0.45
Output Low Voltage (CMOS) VIN = VIH or VIL
VCC = Min, IOL = 0.1mA
Com. 0.2 V
Ind. 0.2 V
VOH Output High Voltage (TTL) VIN = VIH or VIL
VCC = Min, IOH = -4.0mA 2.4 V
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11.5 AC Characteristics
Table 11-4. AC Characteristics(11.9)
Symbol Parameter
-7 -10 -25
UnitsMin Max Min Max Min Max
tPD1 Input or Feedback to Non-registered Output 7.5 10 25 ns
tPD2 I/O Input or Feedback to Non-registered Feedback 7 9 25 ns
tSU Global Clock Setup Time 6 7 20 ns
tHGlobal Clock Hold Time 0 0 0 ns
tFSU Global Clock Setup Time of Fast Input 3 3 5 ns
tFH Global Clock Hold Time of Fast Input 0.5 0.5 2 MHz
tCOP Global Clock to Output Delay 4.5 5 13 ns
tCH Global Clock High Time 3 4 7 ns
tCL Global Clock Low Time 3 4 7 ns
tASU Array Clock Setup Time 3 3 5 ns
tAH Array Clock Hold Time 2 3 6 ns
tACOP Array Clock Output Delay 7.5 10 25 ns
tACH Array Clock High Time 3 4 10 ns
tACL Array Clock Low Time 3 4 10 ns
tCNT Minimum Clock Global Period 8 10 22 ns
fCNT Maximum Internal Global Clock Frequency 125 100 50 MHz
tACNT Minimum Array Clock Period 8 10 22 ns
fACNT Maximum Internal Array Clock Frequency 125 100 50 MHz
fMAX Maximum Clock Frequency 166.7 125 60 MHz
tIN Input Pad and Buffer Delay 0.5 0.5 2 ns
tIO I/O Input Pad and Buffer Delay 0.5 0.5 2 ns
tFIN Fast Input Delay 1 1 2 ns
tSEXP Foldback Term Delay 4 5 12 ns
tPEXP Cascade Logic Delay 0.8 0.8 2 ns
tLAD Logic Array Delay 3 5 8 ns
tLAC Logic Control Delay 3 5 8 ns
tIOE Internal Output Enable Delay 2 2 4 ns
tOD1
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCC = 5.0V; CL = 35pF) 2 1.5 6 ns
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in
the reduced-power mode.
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tZX1
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 5.0V; CL = 35pF) 4.0 5.0 10 ns
tZX2
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35pF) 4.5 5.5 10 ns
tZX3
Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35pF) 9 9 12 ns
tXZ Output Buffer Disable Delay (CL = 5pF) 4 5 8 ns
tSU Register Setup Time 3 3 6 ns
tHRegister Hold Time 2 3 6 ns
tFSU Register Setup Time of Fast Input 3 3 3 ns
tFH Register Hold Time of Fast Input 0.5 0.5 5 ns
tRD Register Delay 1 2 2 ns
tCOMB Combinatorial Delay 1 2 2 ns
tIC Array Clock Delay 3 5 8 ns
tEN Register Enable Time 3 5 8 ns
tGLOB Global Control Delay 1 1 1 ns
tPRE Register Preset Time 2 3 6 ns
tCLR Register Clear Time 2 3 6 ns
tUIM Switch Matrix Delay 1 1 2 ns
tRPA Reduced-power Adder(2) 10 11 15 ns
Table 11-4. AC Characteristics(11.9) (Continued)
Symbol Parameter
-7 -10 -25
UnitsMin Max Min Max Min Max
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in
the reduced-power mode.
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ATF1502AS(L) [DATASHEET]
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14
11.6 Timing Model
Figure 11-1. Timing Model
11.7 Input Test Waveforms and Measurement Levels
Figure 11-2. Input Test Waveforms and Measurement Levels
Note: tR, tF = 1.5ns typical
11.8 Output AC Test Loads
Figure 11-3. Output AC Test Loads
Input
Delay
tIN
Switch
Matrix
tUIM
Internal Output
Enable Delay
tIOE
Global Control
Delay
tGLOB
Logic Array
Delay
tLAD
Register Control
Delay
tLAC
tIC
tEN
Foldback Term
Delay
tSEXP
Cascade Logic
Delay
tPEXP
Fast
Input Delay
tFIN
Register
Delay
tSU
tH
tPRE
tCLR
tRD
tCOMB
tFSU
tFH
Output
Delay
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
I/O
Delay
tIO
AC
Driving
Levels
AC
Measurement
Level
3.0V
0.0V
1.5V
5.0V
Output
CL = 35pF
R1 = 464Ω
R2 = 250Ω
Pin
AtmeL
15
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
11.9 Power-down Mode
The ATF1502AS(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the
PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than
5mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered
and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at
high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches
remain active to ensure the pins do not float to indeterminate levels, further reducing system power. The
power-down pin feature is enabled in the logic design file. Designs using the power-down pin may not use the
PD pin logic array input; however, all other PD pin macrocell resources may still be used, including the buried
feedback and foldback product term array inputs.
11.9.1 Power-down AC Characteristics
Table 11-5. Power-down AC Characteristics(1)(2)
Notes: 1. For slow slew outputs, add tSSO.
2. Pin or product term.
Symbol Parameter
-7 -10 -25
UnitsMin Max Min Max Min Max
tIVDH Valid I, I/O before PD High 7 10 25 ns
tGVDH Valid OE(2) before PD High 7 10 25 ns
tCVDH Valid Clock(2) before PD High 7 10 25 ns
tDHIX I, I/O Don’t Care after PD High 12 15 35 ns
tDHGX OE(2) Don’t Care after PD High 12 15 35 ns
tDHCX Clock(2) Don’t Care after PD High 12 15 35 ns
tDLIV PD Low to Valid I, I/O 1 1 1 μs
tDLGV PD Low to Valid OE (Pin or Term) 1 1 1 μs
tDLCV PD Low to Valid Clock (Pin or Term) 1 1 1 μs
tDLOV PD Low to Valid Output 1 1 1 μs
x? AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
16
12. JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS(L).
The boundary-scan technique involves the inclusion of a shift-register stage (contained in a Boundary-Scan
Cell) adjacent to each component so signals at component boundaries can be controlled and observed using
scan testing methods. Each input pin and I/O pin has its own Boundary-Scan Cell (BSC) to support
Boundary-Scan Testing (BST). The ATF1502AS(L) does not include a Test Reset (TRST) input pin because the
TAP controller is automatically reset at power-up. The five JTAG modes supported include:
SAMPLE/PRELOAD
EXTEST
BYPASS
IDCODE
HIGHZ
The ATF1502AS(L) ISP can fully be described using JTAG’s BSDL as described in IEEE Standard 1149.1b.
This allows ATF1502AS(L) programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502AS(L) has the option of using four JTAG-standard I/O pins for BST and ISP purposes. The
ATF1502AS(L) is programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface
for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed,
then the four JTAG control pins are available as I/O pins.
13. JTAG Boundary-scan Cell (BSC) Testing
The ATF1502AS(L) contains up to 32 I/O pins and four input pins, depending on the device type and package
type selected. Each input pin and I/O pin has its own BSC in order to support BST as described in detail by IEEE
Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update
registers. There are two types of BSCs, one for input or I/O pin and one for the macrocells. The BSCs in the
device are chained together through the capture registers. Input to the capture register chain is fed in from the
TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data
signals, to shift data in and out of the device, and to load data into the update registers. Control signals are
generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and
macrocells is shown below.
Figure 13-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note: 1. The ATF1502AS(L) has a pull-up option on TMS and TDI pins. This feature is selected as a design option.
Dedicated
Input
To Internal Logic
Capture
Registers
Clock
Shift
TDI
(From Next Register)
0
1DQ
TDO
AtmeL k1 % @ k1
17
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Figure 13-2. BSC Configuration for Macrocell
0
1
0
1
DQ DQ
Capture
DR
Update
DR
0
1
0
1
DQ DQ
TDI
OUTJ
OEJ
Shift Clock
Mode
TDO
BSC for I/O Pins and Macrocells
0
1
D
Q
TDI
CLOCK
TDO
Pin
AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
18
14. PCI Compliance
The ATF1502AS(L) supports the growing need in the industry to support the new Peripheral Component
Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high
current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel
outputs to support the high current load required by the PCI interface. The ATF1502AS(L) allows this without
contributing to system noise while delivering low output to output skew. Having a programmable high drive
option is also possible without increasing output delay or pin capacitance.
Table 14-1. PCI DC Characteristics
Note: 1. Leakage current is with pin-keeper off.
Figure 14-1. PCI Voltage-to-current Curves for
+5.0V Signaling in Pull-up Mode
Figure 14-2. PCI Voltage-to-current Curves for
+5.0V Signaling in Pull-down Mode
Symbol Parameter Conditions Min Max Units
VCC Supply Voltage 4.75 5.25 V
VIH Input High Voltage 2.0 VCC + 0.5 V
VIL Input Low Voltage -0.5 0.8 V
IIH Input High Leakage Current(1) VIN = 2.7V 70 μA
IIL Input Low Leakage Current(1) VIN = 0.5V -70 μA
VOH Output High Voltage IOUT = -2mA 2.4 V
VOL Output Low Voltage IOUT = 3mA, 6mA 0.55 V
CIN Input Pin Capacitance 10 pF
CCLK CLK Pin Capacitance 12 pF
CIDSEL IDSEL Pin Capacitance 8 pF
LPIN Pin Inductance 20 nH
2.4
VCC
1.4
-2 -44 -178
Current (mA)
AC drive
point
DC
drive point
Voltage
Pull Up
Test Point
2.2
V
CC
0.55
3,6 95 380
Current (mA)
AC drive
point
DC
drive point
Voltage
Pull Down
Test Point
AtmeL
19
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
Table 14-2. PCI AC Characteristics
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
Symbol Parameter Conditions Min Max Units
IOH(AC)
Switching
Current High
(Test High)
0 < VOUT 1.4 -44 mA
1.4 < VOUT < 2.4 -44 + (VOUT - 1.4)/0.024 mA
3.1 < VOUT < VCC Equation A mA
VOUT = 3.1V -142 μA
IOL(AC)
Switching
Current Low
(Test Point)
VOUT >2.2V 95 mA
2.2 > VOUT > 0 VOUT/0.023 mA
0.1 > VOUT > 0 Equation B mA
VOUT = 0.71 206 mA
ICL Low Clamp Current -5 < VIN -1 -25 + (VIN + 1)/0.015 mA
SLEWROutput Rise Slew Rate 0.4V to 2.4V Load 1 5 V/ns
SLEWFOutput Fall Slew Rate 2.4V to 0.4V Load 1 5 V/ns
AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
20
15. Pinouts
15.1 ATF1502AS(L) Dedicated Pinouts
Note: OE (1, 2) . . . . . . . . . . . . . Global OE pins
GCLR . . . . . . . . . . . . . . . Global Clear pin
GCLK (1, 2, 3) . . . . . . . . . Global Clock pins
PD (1, 2) . . . . . . . . . . . . . Power-down pins
TDI, TMS, TCK, TDO . . . JTAG pins used for boundary-scan testing or in-system programming
GND . . . . . . . . . . . . . . . . Ground pins
VCC . . . . . . . . . . . . . . . . . VCC pins for the device (+5V)
Dedicated Pin
44-lead
TQFP
44-lead
J-lead
INPUT/OE2/GCLK2 40 2
INPUT/GCLR 39 1
INPUT/OE1 38 44
INPUT/GCLK1 37 43
I/O / GCLK3 35 41
I/O / PD (1,2) 5, 19 11, 25
I/O / TDI (JTAG) 1 7
I/O / TMS (JTAG) 7 13
I/O / TCK (JTAG) 26 32
I/O / TDO (JTAG) 32 38
GND 4, 16, 24, 36 10, 22, 30, 42
VCC 9, 17, 29, 41 3, 15, 23, 35
# of Signal Pins 36 36
# User I/O Pins 32 32
AtmeL
21
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
15.2 ATF1502AS(L) I/O Pinouts
MC PLC 44-lead PLCC 44-lead TQFP
1 A 4 42
2 A 5 43
3 A/PD1 6 44
4/TDI A 7 1
5 A 8 2
6 A 9 3
7 A 11 5
8 A 12 6
9/TMS A 13 7
10 A 14 8
11 A 16 10
12 A 17 11
13 A 18 12
14 A 19 13
15 A 20 14
16 A 21 15
17 B 41 35
18 B 40 34
19 B 39 33
20/TDO B 38 32
21 B 37 31
22 B 36 30
23 B 34 28
24 B 33 27
25/TCK B 32 26
26 B 31 25
27 B 29 23
28 B 28 22
29 B 27 21
30 B 26 20
31 B 25 19
32 B 24 18
SUPPLY CURRENT VS SUPPLY VOLTAGE AS VERSION m = 25°c. F n) REDUCED A5 :75 5 525 5 5 mm supva cumENr Vs.suPDLv vomCE PlN-CONYROLLEJ PWER—DOWN MODE (T. = 25°C. F = o) gt YBD o5 415 5 525 5 5 Vacm SUPPLV CURRENT vs. FnEquNCV As VERSION (TA : 25%)) me 500 we k Sm) 200 mum mm .55 0.0 m awn wow w.» saw whoa mum mm OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE we" = 2.4V. TA = 25-.» on ma 200 L $60 0 Mm .500 m 450 A 75 5 m 5 25 5 so suPRvaarmE (VD 5|»:va CVRRENT VS. SUPPLY VOLTAGE (T = 25%, NDN-luRBCI, me E a, BIT an : n) n 0 van: N) supva CURRENT vs. FREauEch ASL (LOW-POWER) VERSION (r. : 25=C) STANDARD a: 0 gm 2a a nsnucm we on Dan law 2mm 5m «:00 mo mousm mm INPUT CLAMP CURRENT VS. INPUT VOLTAGE (v0c = 5v, T. = 25am 4 m use 4) an em ozu n m mnuwoLmE on ouTPuT SOURCE cuRRENT VS. ouTPuT VOLTAGE (Voc = 5V, T. = 5‘5) 570» mu m um am Can we ‘50 200 2m 3m 3543 mo m 509 Mpuwmrmtm AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
22
OUTPUT SINK CURRENT Vs. SUPPLY VOLTAGE [VOL = .EVJ',k = 25-c) ‘50 V vs 5 m 5 25 5 50 supmvwmim IMPUI cunnsmvs. mum VOLTAEE (v:c = w. : 25-0) m'fiks .2n .30 no as w T5 2» 15 :0 as u A; 5» wurvumcsm HORMAUIED TPD VSJEMPERATURE (vac: 5.nv) ‘2 1 T «a m2 «a o o 25 a 75 n rmmnumc» NomAqunTsu vs.suPPLv VOLTAGE (1. = we) ‘2 4.: surmvmmz m AtmeL NomALIzEu m: NORMALIZED TFD Vs. SUPPLY VOLTAGE (TA . 5°cp 120 Ho ‘00 090 can As Is so 5.: ss suPPvaoLTAuEm OUTPUT SINK CURRENT Vs. OUTPUT VOLTAGE (Vcc- \LTA- 5‘0 «an mu man km Em m 200 on we use 100 T50 200 250 300 am me 450 500 ouTrLrTvuLTmEM NORMALIZEDTCU Vs. supva VOLTAGE (TA: 25-12) \z n mam-mam | a a 9 a a surerVoLTmEM NonMALIzED Tco VSJEMPERATURE (VDc = 5.nV) D9 u a .mo 0 a 2; o 751) murmnuna It)
23
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
V2 NORMALIIED Tsu vs. TEMPERATURE (m,c . 5m) m m Hm vsu as u n- malnunE m) m m AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
24
AtmeL
25
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
16. Ordering Information
16.1 Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
7.5 4.5 166.7
ATF1502AS-7AX44 44A Commercial
(0Cto70C)
ATF1502AS-7JX44 44J
10 5 125
ATF1502AS-10AU44 44A Industrial
(-40C to +85C)
ATF1502AS-10JU44 44J
25 13 60
ATF1502ASL-25AU44 44A Industrial
(-40C to +85C)
ATF1502ASL-25JU44 44J
Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack Package (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
L o B M v s AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
26
17. Packaging Information
17.1 44A — 44-lead TQFP
DRAWING NO. REV. TITLE GPC
44A D
AIX
Package Drawing Contact:
packagedrawings@atmel.com
1/10/13
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
0°~7°
L
C
A1 A2 A
D
E
b
BOTTOM VIEW
SIDE VIEW
TOP VIEW
E1
D1
e
44A, 44-lead 10.0 x 10.0x1.0 mm Body, 0.80 mm
Lead Pitch, Thin Profile Plastic Quad Flat
Package (TQFP)
AtmeL
27
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
17.2 44J — 44-lead PLCC
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45° PIN NO. 1
IDENTIFIER
1.14(0.045) X 45°
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45° MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B
44J
10/04/01
TITLE DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com
AtmeL
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
28
18. Revision History
Revision Date Comments
0995L 03/2014 Remove lead based package offering and 15ns speed grade.
Update template, logos, and disclaimer page.
0995K 06/2005 Green package options added.
Atmet ‘ Enablmg Unlimited Possibilities" ”amfiw
X
XXX
XX
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© 2014 Atmel Corporation. / Rev.: Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014.
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