onsemi 的 MM82C19 规格书

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© 2004 Fairchild Semiconductor Corporation DS005891 www.fairchildsemi.com
October 1987
Revised January 2004
MM82C19 16-Line to 1-Line Multiplexer
MM82C19
16-Line to 1-Line Multiplexer
General Description
The MM82C19 multiplex 16 digital lines to 1 output. A 4-bit
address code determines the particular 1-of-16 inputs
which is routed to the output. The data is inverted from
input to output.
A strobe override places the output of MM82C19 in the
high-impedance state.
All inputs are protected from damage due to static dis-
charge by diode clamps to VCC and GND.
Features
■Wide supply voltage range: 3.0V to 15V
■Guaranteed noise margin: 1.0V
■High noise immunity: 0.45 VCC (typ.)
■TTL compatibility: Drive 1 TTL Load
Ordering Code:
Connection Diagram
Order Number Package Number Package Description
MM82C19N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
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MM82C19
Truth Table
MM82C19
Inputs Output
D C B A STROBE E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 W
XXXX 1 XXXXXXXXXXXXXXXX High-Z
0000 0 0XXXXXXXXXX XXXXX 1
0000 0 1XXXXXXXXXX XXXXX 0
0001 0 X0XXXXXXXXXXXXXX 1
0001 0 X1XXXXXXXXXXXXXX 0
0010 0 XX0XXXXXXXXXXXXX 1
0010 0 XX1XXXXXXXXXXXXX 0
0011 0 XXX0XXXXXXXXXXXX 1
0011 0 XXX1XXXXXXXXXXXX 0
0100 0 XXXX0XXXXXXXXXXX 1
0100 0 XXXX1XXXXXXXXXXX 0
0101 0 XXXXX0XXXXXXXXXX 1
0101 0 XXXXX1XXXXXXXXXX 0
0110 0 XXXXXX0XXXXXXXXX 1
0110 0 XXXXXX1XXXXXXXXX 0
0111 0 XXXXXXX0XXXXXXXX 1
0111 0 XXXXXXX1XXXXXXXX 0
1000 0 XXXXXXXX0XX XXXXX 1
1000 0 XXXXXXXX1XX XXXXX 0
1001 0 XXXXXXXXX0XXXXXX 1
1001 0 XXXXXXXXX1XXXXXX 0
1010 0 XXXXXXXXXX0 XXXXX 1
1010 0 XXXXXXXXXX1 XXXXX 0
1011 0 XXXXXXXXXXX 0 X XX X 1
1011 0 XXXXXXXXXXX 1 X XX X 0
1100 0 XXXXXXXXXXX X 0 XXX 1
1100 0 XXXXXXXXXXX X 1 XXX 0
1101 0 XXXXXXXXXXXXX 0 XX 1
1101 0 XXXXXXXXXXXXX 1 XX 0
1110 0 XXXXXXXXXXX XX X 0 X 1
1110 0 XXXXXXXXXXX XX X 1 X 0
1111 0 XXXXXXXXXXX XX XX 0 1
1111 0 XXXXXXXXXXX XX XX 1 0
0 mm
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MM82C19
Logic Diagram
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MM82C19
Absolute Maximum Ratings(Note 1)
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The Electrical Characteristic table provides conditions
for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted.
Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating VCC Range 3.0V to 15V
VCC 18V
Lead Temperature
(soldering, 10 seconds) 260°C
Symbol Parameter Conditions Min Typ Max Units
CMOS to CMOS
VIN(1) Logical “1” Input Voltage VCC = 5.0V 3.5 V
VCC = 10V 8.0
VIN(0) Logical “0” Input Voltage VCC = 5.0V 1.5 V
VCC = 10V 2.0
VOUT(1) Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V
VCC = 10V, IO = −10 µA9.0
VOUT(0) Logical “0” Output Voltage VCC = 5.0V, IO = +10 µA0.5
V
VCC = 10V, IO = +10 µA1.0
IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 V
IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA
IOZ Output Current in High
Impedance State
MM82C19 VCC = 15V, VO = 15V 0.005 1.0 µA
VCC = 15V, VO = 0V −1.0 −0.005
ICC Supply Current VCC = 15V 0.05 300 µA
CMOS/LPTTL Interface
VIN(1) Logical “1” Input Voltage 74C, 82C, VCC = 4.75V VCC−1.5 V
VIN(0) Logical “0” Input Voltage 74C, 82C, VCC = 4.75V 0.8 V
VOUT(1) Logical “1” Output Voltage 74C, 82C, VCC = 4.75V, IO = −1.6 mA 2.4 V
VOUT(0) Logical “0” Output Voltage 74C, 82C, VCC = 4.75V, IO = 1.6 mA 0.4 V
Output Drive (Short Circuit Current)
ISOURCE Output Source Current VCC = 5.0V, VOUT = 0V, TA = 25°C−4.35 −8mA
(P-Channel)
ISOURCE Output Source Current VCC = 10V, VOUT = 0V, TA = 25°C−20 −40 mA
(P-Channel)
ISINK Output Sink Current VCC = 5.0V, VOUT = VCC, TA = 25°C4.35 8 mA
(N-Channel)
ISINK Output Sink Current VCC = 10V, VOUT = VCC, TA = 25°C2040 mA
(N-Channel)
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MM82C19
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise noted
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics, application note
AN-90.
Symbol Parameter Conditions Min Typ Max Units
tpd0, tpd1 Propagation Delay Time to a VCC = 5.0V 250 600
ns
Logical “0” or Logical “1”VCC = 10V 110 300
from Data Inputs to Output VCC = 5.0V, CL = 150 pF 290 650
VCC = 10V, CL = 150 pF 120 330
tpd0, tpd1 Propagation Delay Time to a VCC = 5.0V 290 650 ns
Logical “0” or Logical “1”VCC = 10V 120 330
from Data Select Inputs to Output
tpd0, tpd1 Propagation Delay Time to a VCC = 5.0V 120 300 ns
Logical “0” or Logical “1”VCC = 10V 55 150
from Strobe to Output MM74C150
t1H, t0H Delay from Strobe to High VCC = 5.0V, RL = 10k, CL = 5 pF 80 200 ns
Impedance State MM82C19 VCC = 10V, RL = 10k, CL = 5 pF 60 150
tH1, tH0 Delay from Strobe to Logical VCC = 5.0V, RL = 10k, CL = 5 pF 80 250 ns
“1” Level or to Logical “0”VCC = 10V, RL = 10k, CL = 5 pF 30 120
Level (from High Impedance State)
MM82C19
CIN Input Capacitance Any Input (Note 3) 5.0 pF
COUT Output Capacitance (Note 3) 11.0 pF
MM82C19
CPD Power Dissipation Capacitance (Note 4) 100 pF
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MM82C19
Switching Time Waveforms
CMOS to CMOS
t1H and tH1 t1H
tH1 t0H and tH0
t0H
Note: Delays measured with input tr, tf ≤ 20 ns.
tH0
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MM82C19 16-Line to 1-Line Multiplexer
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide
Package Number N24A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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