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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

UCC28180 Programmable Frequency, Continuous Conduction Mode (CCM), Boost Power

Factor Correction (PFC) Controller

1 Features

1• 8-Pin Solution (No AC Line Sensing Needed)

• Wide Range Programmable Switching Frequency

(18 kHz to 250 kHz for MOSFET and IGBT-based

PFC Converters)

• Trimmed Current Loop Circuits for Low iTHD

• Reduced Current Sense Threshold (Minimizes

Power Dissipation in Shunt)

• Average Current-Mode Control

• Soft Over Current and Cycle-by-Cycle Peak

Current Limit Protection

• Output Overvoltage Protection With Hysteresis

Recovery

• Audible Noise Minimization Circuitry

• Open Loop Detection

• Enhance Dynamic Response During Output

Overvoltage and Undervoltage Conditions

• Maximum Duty Cycle of 96% (Typical)

• Burst Mode for No Load Regulation

• VCC UVLO, Low ICC Start-Up (< 75 µA)

2 Applications

• Universal AC Input, CCM Boost PFC Converters

in 100-W to Few-kW Range

• Server and Desktop Power Supplies

• White Good Appliances (Air Conditioners,

Refrigerators)

• Industrial Power Supplies (DIN Rail)

• Flat Panel (PDP, LCD, and LED) TVs

3 Description

The UCC28180 is a flexible and easy-to-use, 8-pin,

active Power-Factor Correction (PFC) controller that

operates under Continuous Conduction Mode (CCM)

to achieve high Power Factor, low current distortion

and excellent voltage regulation of boost pre-

regulators in AC - DC front-ends. The controller is

suitable for universal AC input systems operating in

100-W to few-kW range with the switching frequency

programmable between 18 kHz to 250 kHz, to

conveniently support both power MOSFET and IGBT

switches. An integrated 1.5-A and 2-A (SRC-SNK)

peak gate drive output, clamped internally at 15.2 V

(typical), enables fast turn-on, turn-off, and easy

management of the external power switch without the

need for buffer circuits.

Low-distortion wave shaping of the input current

using average current mode control is achieved

without input line sensing, reducing the external

component count. In addition, the controller features

reduced current sense thresholds to facilitate the use

of small-value shunt resistors for reduced power

dissipation, especially important in high-power

systems. To enable low current distortion, the

controller also features trimmed internal current loop

regulation circuits for eliminating associated

inaccuracies.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

UCC28180 SOIC (8) 4.90 mm × 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

space

Typical Application Schematic

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (Continued)........................................ 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 8

8 Detailed Description............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram....................................... 13

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 20

9 Application and Implementation ........................ 21

9.1 Application Information............................................ 21

9.2 Typical Application .................................................. 22

10 Power Supply Recommendations ..................... 36

10.1 Bias Supply ........................................................... 36

11 Layout................................................................... 36

11.1 Layout Guidelines ................................................. 36

11.2 Layout Example .................................................... 38

12 Device and Documentation Support . .............. 39

12.1 Documentation Support ....................................... 39

12.2 Receiving Notification of Documentation Updates 39

12.3 Community Resources.......................................... 39

12.4 Trademarks........................................................... 39

12.5 Electrostatic Discharge Caution............................ 39

12.6 Glossary................................................................ 39

13 Mechanical, Packaging, and Orderable

Information ........................................................... 39

4 Revision History

Changes from Revision C (April 2016) to Revision D Page

• Changed the correct page number in the C Revision History of the diode addition to the Functional Block Diagram.......... 2

• Changed text value of 0.538 to 0.366 to align with Equation 85. Updated change was implemented in the C revision

and recorded in the D revision. ............................................................................................................................................ 31

• Added D4 to Table 2. Updated change was implemented in the C revision and recorded in the D revision. ..................... 37

• Added Receiving Notification of Documentation Updates.................................................................................................... 39

• Added Community Resources.............................................................................................................................................. 39

Changes from Revision B (December 2014) to Revision C Page

• Added a diode to the Typical Application Schematic image. ................................................................................................. 1

• Changed ICC Standby current MAX rate from 2.95 mA to 3.47 mA...................................................................................... 6

• Changed ISENSE threshold, soft over current (SOC) TYP value from –0.295 V to –0.285 V. ............................................. 6

• Changed Maximum current under EDR operation MAX rating from –241 µA to –275 µA. ................................................... 6

• Added a diode to the Functional Block Diagram.................................................................................................................. 13

• Added Diode to Soft Overcurrent/Peak-Current Limit image. .............................................................................................. 17

• Added ISENSE Pin section. ................................................................................................................................................ 18

• Added diode to the Design Example Schematic image. ..................................................................................................... 22

• Changed Equation 101 3kHz to 5kHz. ................................................................................................................................. 32

• Changed Recommended Layout for UCC28180 image....................................................................................................... 38

Changes from Revision A (November 2013) to Revision B Page

• Added ESD Rating table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

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5 Description (Continued)

Simple external networks allow for flexible compensation of the current and voltage control loops. In addition,

UCC28180 offers an enhanced dynamic response circuit that is based on the voltage feedback signal to deliver

improved response under fast load transients, both for output overvoltage and undervoltage conditions. An

unique VCOMP discharge circuit provided in UCC28180 is activated whenever the voltage feedback signal

exceeds VOVP_L thus allowing a chance for the control loop to stabilize quickly and avoid encountering the

overvoltage protection function when PWM shutoff can often cause audible noise. Controlled soft start gradually

regulates the input current during start-up and reduces stress on the power switches. Numerous system-level

protection features available in the controller include VCC UVLO, peak current limit, soft overcurrent, output

open-loop detection, output overvoltage protection and open-pin detection (VISNS). A trimmed internal reference

provides accurate protection thresholds and regulation set-point. The user can control low-power standby mode

by pulling the VSENSE pin below 0.82 V.

l TEXAS INSTRUMENTS

GND

ICOMP

ISENSE

GATE

VCC

VSENSE

VCOMP

FREQ

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

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6 Pin Configuration and Functions

8-Pin SOIC

D Package

(TOP VIEW)

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

GATE 8 O Gate Drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A sink

and 1.5-A source capability. Output voltage is typically clamped at 15.2 V (typical).

GND 1 Ground: device ground reference.

ICOMP 2 O Current Loop Compensation: Transconductance current amplifier output. A capacitor connected to GND

provides compensation and averaging of the current sense signal in the current control loop. The controller is

disabled if the voltage on ICOMP is less than 0.2 V, (ICOMPP protection function).

ISENSE 3 I

Inductor Current Sense: Input for the voltage across the external current sense resistor, which represents

the instantaneous current through the PFC boost inductor. This voltage is averaged by the current amplifier to

eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the average inductor current. Cycle-

by-cycle peak current limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded.

An internal 2.3-µA current source pulls ISENSE above 0.085 V to shut down PFC operation if this pin

becomes open-circuited, (ISOP protection function). Use a 220-Ωresistor between this pin and the current

sense resistor to limit inrush-surge currents into this pin.

VCC 7

Device Supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until VCC

exceeds a turn-on threshold of 11.5 V. Operation continues until VCC falls below the turn-off (UVLO)

threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value should be connected from VCC to

GND as close to the device as possible for high-frequency filtering of the VCC voltage.

VCOMP 5 O

Voltage Loop Compensation: Transconductance voltage error amplifier output. A resistor-capacitor network

connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, and VSENSE

exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE

voltage reaches its nominal regulation level. When Enhanced Dynamic Response (EDR) is engaged, a higher

transconductance is applied to VCOMP to reduce the charge or discharge time for faster transient response.

Soft Start is programmed by the capacitance on this pin. VCOMP is pulled low when VCC UVLO,

OLP/Standby, ICOMPP and ISOP functions are activated.

FREQ 4 O Switching Frequency Setting: This pin allows the setting of the operating switching frequency by connecting

a resistor to ground. The programmable frequency range is from 18 kHz to 250 kHz.

VSENSE 6 I

Output Voltage Sense: An external resistor-divider network connected from this pin to the PFC output

voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small capacitor from

this pin to GND filters high-frequency noise. Standby disables the controller and discharges VCOMP when

the voltage at VSENSE drops below the Open-Loop Protection (OLP) threshold of 16.5%VREF (0.82 V). An

internal 100-nA current source pulls VSENSE to GND during pin disconnection. Enhanced Dynamic

Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load

step causes VSENSE to rise above 105% or fall below 95% of the reference voltage. Two level Output Over-

Voltage Protection (OVP): a 4-kΩresistor connects VCOMP to ground to rapidly discharge VCOMP when

VSENSE exceeds 107% (VOVP_L) of the reference voltage. If VSENSE exceeds 109% (VOVP_H) of the

reference voltage, GATE output will be disabled until VSENSE drops below 102% of the reference voltage.

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(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other condition beyond those included under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings(1)

Over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted). Currents are

positive into and negative out of the specified terminal.

MIN MAX UNIT

Input voltage range VCC, GATE –0.3 22 V

FREQ, VSENSE, VCOMP, ICOMP –0.3 7

ISENSE –24 7

Input current range VSENSE, ISENSE –1 1 mA

Junction temperature, TJOperating –55 150 °C

Lead temperature, TSOL Soldering, 10 s 300 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VCC input voltage from a low-impedance source VCCOFF + 1V 21 V

Operating junction temperature, TJ–40 125 °C

Operating frequency 18 250 kHz

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.4 Thermal Information

THERMAL METRIC(1)

UCC28180

UNITD

8 PINS

RθJA Junction-to-ambient thermal resistance(2) 116.1

°C/W

RθJCtop Junction-to-case (top) thermal resistance(3) 62.2

RθJB Junction-to-board thermal resistance(4) 56.4

ψJT Junction-to-top characterization parameter(5) 14.4

ψJB Junction-to-board characterization parameter(6) 55.9

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(1) Not production tested. Characterized by design

7.5 Electrical Characteristics

Unless otherwise noted, VCC=15Vdc, 0.1µF from VCC to GND, –40°C ≤TJ= TA≤+125°C. All voltages are with respect to

GND. Currents are positive into and negative out of the specified terminal.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC BIAS SUPPLY

ICCPRESTART ICC Pre-start current VCC = VCCOFF – 0.2 V 75 µA

ICCSTBY ICC Standby current VSENSE = 0.5 V 1.8 2.4 3.47 mA

ICCON_load ICC Operating current VSENSE = 4.0 V, CGATE = 4.7 nF 5.8 7 8.8 mA

UNDER VOLTAGE LOCKOUT (UVLO)

VCCON VCC Turn on threshold 10.8 11.5 12.1 V

VCCOFF VCC Turn off threshold 9.1 9.5 10.3 V

UVLO Hysteresis 1.6 1.7 2 V

VARIABLE FREQUENCY

fSW

Minimum switching frequency RFREQ = 130 kΩ16.3 18 19.8 kHz

Typical switching frequency RFREQ = 32.7 kΩ61.75 65 68.25 kHz

Maximum switching frequency RFREQ = 8.2 kΩ225 250 275 kHz

VFREQ Voltage at FREQ pin TA= 25°C 1.43 1.5 1.56 V

PWM

DMIN Minimum duty cycle VSENSE = 5.1 V, ISENSE = –0.25 V 0%

DMAX Maximum duty cycle VSENSE = 4.0 V, RFREQ = 32.7 Ω94.8% 96.5% 98%

tOFF(min) Minimum off time VSENSE = 3 V, ICOMP = 0.72 V 450 570 690 ns

SYSTEM PROTECTION

VSOC ISENSE threshold, soft over current (SOC) –0.259 –0.285 –0.312 V

VPCL ISENSE threshold, peak current limit (PCL) –0.345 –0.4 –0.438 V

IISOP ISENSE bias current, ISENSE open-pin protection

(ISOP) ISENSE = 0 V –2.3 –2.95 µA

VISOP ISENSE threshold, ISENSE open-pin protection

(ISOP) ISENSE = open pin 0.085 0.14 V

VOLP VSENSE threshold, open loop protection (OLP) ICOMP = 1 V, ISENSE = 0 V 15.6 16.5 17.6 %VREF

Open loop protection (OLP) Internal pull-down

current VSENSE = 0.5 V 100 325 nA

VUVD VSENSE threshold, output under-voltage detection

(UVD) used for enhanced dynamic response(1) 93.25 95 97 %VREF

VOVD VSENSE threshold, output over-voltage detection

(OVD) used for Enhanced dynamic response(1) 103 105 106.75 %VREF

VOVP_L

Output over-voltage protection low threshold,

VCOMP is discharged by a 4kΩresistor when

VSENSE > VOVP_L

105 107 109 %VREF

VOVP_H Output over-voltage protection high threshold, PWM

shuts off when VSENSE > VOVP_H 107 109 111 %VREF

VOVP_H(RST)

Output over-voltage protection (VOVP_H) reset

threshold, PWM turns on when VSENSE <

VOVP_H(RST)

100 102 104 %VREF

ICOMP threshold, external overload protection 0.2 0.25 %VREF

CURRENT LOOP

gmi Transconductance gain 0.75 0.95 1.1 mS

Output linear range (1) ±50 µA

ICOMP voltage during OLP VSENSE = 0 V 2.7 3 3.3 V

VOLTAGE LOOP

VREF Reference voltage TA= 25°C 4.93 5 5.07 V

–40°C ≤TA≤+125°C 4.87 5 5.15 V

gmv Transconductance gain without EDR –40 –56 –70 µS

gmv-EDR Transconductance gain under EDR –230 –280 –340 µS

Maximum sink current under normal operation VSENSE = 5 V, VCOMP = 4 V 23 40 57 µA

Source current under soft start VSENSE = 4 V, VCOMP = 4 V –29 –40 –52 µA

Maximum current under EDR operation VSENSE = 4 V, VCOMP = 2.5 V –200 –275 µA

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Electrical Characteristics (continued)

Unless otherwise noted, VCC=15Vdc, 0.1µF from VCC to GND, –40°C ≤TJ= TA≤+125°C. All voltages are with respect to

GND. Currents are positive into and negative out of the specified terminal.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VSENSE input bias current VSENSE = 5 V 20 100 250 nA

VCOMP voltage during OLP VSENSE = 0.5 V, IVCOMP= 0.5 mA 0 0.04 0.10 V

VCOMP rapid discharge current VCOMP = 2 V, VCC = floating 0.37 mA

VPRECHARGE VCOMP precharge voltage IVCOMP = –100 µA, VSENSE = 4 V 1.5 V

IPRECHARGE VCOMP precharge current VCOMP = 0 V –1 mA

VSENSE threshold, end-of-soft-start Initial Start-up 98 %VREF

GATE DRIVER

GATE current, peak, sinking(1) CGATE = 4.7 nF 2 A

GATE current, peak, sourcing(1) CGATE = 4.7 nF –1.5 A

GATE rise time CGATE = 4.7 nF, GATE = 2 V to 8 V 8 40 60 ns

GATE fall time CGATE = 4.7 nF, GATE = 8 V to 2 V 8 25 40 ns

GATE low voltage, no load IGATE = 0 A 0 0.01 V

GATE low voltage, sinking IGATE = 20 mA 0.04 0.06 V

GATE low voltage, sourcing IGATE = -20 mA –0.04 –0.06 V

GATE low voltage, sinking, OFF VCC = 5 V, IGATE = 5 mA 0.1 0.2 0.31 V

GATE low voltage, sinking, OFF VCC = 5 V, IGATE = 20 mA 0.4 0.8 1.4 V

GATE high voltage VCC = 20 V, CGATE = 4.7 nF 14.5 15.2 16.1 V

GATE high voltage VCC = 12.2 V, CGATE = 4.7 nF 10.8 11.2 12 V

GATE high voltage VCC = VCCOFF + 0.2 V,

CGATE = 4.7 nF 8.2 9 10.1 V

l TEXAS INSTRUMENTS

±40 10 60 110

ICC ± Supply Current (mA)

TJ ± Temperature (ƒC)

C005

Operating, GATE Load = 4.7 nF

Standby

±40 10 60 110

ICC ± Supply Current (µA)

TJ ± Temperature (ƒC)

C006

Pre-Start

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 5 10 15 20 25

ICC ± Supply Current (mA)

VCC ± Bias Supply Voltage (V)

C004

ICC Turn ON

ICC Turn OFF

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

±40 10 60 110

VCCON/VCCOFF ± UVLO Threshold (V)

TJ ± Temperature (ƒC)

C003

VCC Turn ON

VCC Turn OFF

0.85

0.87

0.89

0.91

0.93

0.95

0.97

0.99

15 35 55 75 95 115 135 155 175 195 215 235 255

DMAX ± Maximum Duty Cycle

FSW ± Switching Frequency (kHz)

C002

115

165

215

265

0 20 40 60 80 100 120 140

FSW ± Switching Frequency (kHz)

RFREQ (KŸ)

C001

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7.6 Typical Characteristics

Figure 1. Switching Frequency vs. Resistor

VCC = 15 V

Figure 2. Maximum Duty Cycle vs. Switching Frequency

Figure 3. UVLO Threshold vs. Temperature

TJ= 25 °C VSENSE= 3 V

No Gate Load FSW = 65 kHz

Figure 4. Supply Current vs. Bias Supply Voltage

VCC = 15 V

Figure 5. Supply Current vs. Temperature

VCC = VCCON – 0.2 V

Figure 6. Pre-Start Supply Current vs. Temperature

l TEXAS INSTRUMENTS

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

19.5

20.0

9 11 13 15 17 19 21

Oscillator Frequency (kHz)

Bias Supply Voltage (V)

C003

245.0

245.5

246.0

246.5

247.0

247.5

248.0

248.5

249.0

249.5

250.0

9 11 13 15 17 19 21

Oscillator Frequency (kHz)

Bias Supply Voltage (V)

C004

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

19.5

20.0

±50 ±25 0 25 50 75 100 125

Oscillator Frequency (kHz)

Temperature (ƒC)

C006

245.0

245.5

246.0

246.5

247.0

247.5

248.0

248.5

249.0

249.5

250.0

±50 ±25 0 25 50 75 100 125

Switching Frequency (kHz)

Temperature (ƒC)

C002

±40 10 60 110

fSW ± Switching Frequency (kHz)

TJ ± Temperature (ƒC)

C007

Switching Frequency

9 11 13 15 17 19 21 23

fSW ± Switching Frequency (kHz)

VCC ± Bias Supply Voltage (V)

C008

Switching Frequency

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Typical Characteristics (continued)

VCC = 15 V FSW = 65 kHz

Figure 7. Oscillator Frequency (65 kHz) vs. Temperature

TJ= 25 °C FSW = 65 kHz

Figure 8. Oscillator Frequency (65 kHz) vs. Bias Supply

Voltage

VCC = 15 V

Figure 9. Oscillator Frequency (18 kHz) vs. Temperature

VCC = 15 V

Figure 10. Oscillator Frequency (250 kHz) vs. Temperature

TJ= 25 °C

Figure 11. Oscillator Frequency (18 kHz) vs. Bias Voltage

TJ= 25 °C

Figure 12. Oscillator Frequency (250 kHz) vs. Bias Voltage

l TEXAS INSTRUMENTS

100

105

110

115

±40 ±15 10 35 60 85 110

VOVP_H/VOVP_L/VOVD/VOVP_H(RST)/VUVD t VSENSE Threshold (% of VREF)

TJ t Temperature (ƒC)

C013

VOVP_H

VOVP_L

VOVD

VOVP_H(RST)

VUVD

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

±40 10 60 110

VOLP ± VSENSE Threshold (V)

TJ ± Temperature (ƒC)

C014

VOLP

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

±40 10 60 110

VREF ± Reference Voltage (V)

TJ ± Temperature (ƒC)

C011

Reference Voltage

±0.50

±0.45

±0.40

±0.35

±0.30

±0.25

±0.20

±0.15

±0.10

±0.05

0.00

±40 10 60 110

VSOC ± ISENSE Threshold (V)

TJ ± Temperature (ƒC)

C012

Soft Over-Current Protection (SOC)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

±40 10 60 110

gmi ± Gain (mA/V)

TJ ± Temperature (ƒC)

C009

Gain

±65

±63

±61

±59

±57

±55

±53

±51

±49

±47

±45

±40 10 60 110

gmv ± Gain (µA/V)

TJ t Temperature (ƒC)

C010

Gain, No EDR

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Typical Characteristics (continued)

VCC = 15 V

Figure 13. Current Loop Gain vs. Temperature

VCC = 15 V

Figure 14. Voltage Loop Gain vs. Temperature

VCC = 15 V

Figure 15. Reference Voltage vs. Temperature

VCC = 15 V

Figure 16. ISENSE Threshold Soft Over Current (SOC) vs.

Temperature

VCC = 15 V

Figure 17. VSENSE Threshold vs. Temperature

VCC = 15 V

Figure 18. VSENSE Threshold Open Loop vs. Temperature

l TEXAS INSTRUMENTS

10 12 14 16 18 20 22

t ± Time (ns)

VCC ± Bias Supply Voltage (V)

C017

Rise Time

Fall Time

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

±40 ±15 10 35 60 85 110

VGATE ± Gate Low Voltage (V)

TJ ± Temperature (ƒC)

C018

VGATE

450

470

490

510

530

550

570

590

610

630

650

±40 ±15 10 35 60 85 110

t ± Time (ns)

TJ ± Temperature (ƒC)

C015

tOFF(min)

±40 ±15 10 35 60 85 110

t ± Time (ns)

TJ ± Temperature (ƒC)

C016

Rise Time

Fall Time

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

Typical Characteristics (continued)

ICOMP = 0.72 V VSENSE = 3 V FSW = 65 kHz

Figure 19. Minimum Off Time vs. Temperature

VCC = 15 V CGATE = 4.7 nF VGATE = 2 V-8 V

Figure 20. Gate Drive Rise/Fall Time vs. Temperature

TJ= 25 °C CGATE = 4.7 nF VGATE = 2 V-8 V

Figure 21. Gate Drive Rise/Fall Time vs. Bias Supply Voltage

VCC = 15 V IGATE = 20 mA

Figure 22. Gate Low Voltage vs. Temperature

l TEXAS INSTRUMENTS

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

8 Detailed Description

8.1 Overview

The UCC28180 is a boost controller for power factor correction operating at a fixed frequency in continuous

conduction mode. The UCC28180 requires few external components to operate as an active PFC pre-regulator.

UCC28180 employs two control loops. An internal error amplifier and 5-V reference provide a slow outer loop to

control output voltage. External compensation of this outer loop is applied by means of the VCOMP pin. The

inner current loop shapes the average input current to match the sinusoidal input voltage. The inner current loop

avoids the need to sense input voltage by exploiting the relationship between input voltage and boost duty-cycle.

External compensation of the inner current loop is applied by means of the ICOMP pin.

The operating switching frequency can be programmed from 18 kHz to 250 kHz simply by connecting the FREQ

pin to ground through a resistor.

UCC28180 includes a number of protection functions designed to ensure it is reliable, and will provide safe

operation under all conditions, including abnormal or fault conditions.

W V my!

5.25VEDR

Soft Over Current(SOC)

0.72V

Peak Current Limit (PCL)

PCL

-2.5X

Oscillator

300ns

Leading Edge

Blanking

5.45V

Q R 5.10V

RSENSE

COUT

LBST

RISENSEfilter

+– Bridge

Rectifier

CISENSEfilter

LINE

INPUT

DBST

VOUT

CCV2

RCV

CCV1

gmv

Voltage Error

Amplifier

gmi

CICOMP S Q

PWM

Comparator

KPC(s)

EMI Filter

VCOMP

CIN

Oscillator

RLOAD

Current

Amplifier

ISENSE

ICOMP

FREQ 4

5VCOMP

6VSENSE

8GATE

GAIN

M1, K1

+4.75V

EDR

Gate Driver

S Q

QR Pre-Drive and

Clamp Circuit

RFB1

RFB2

QBST RGATE

CVSENSE

PWM

RAMP

M2Min Off Time

PCL

Clock

FAULT

0.2V +

ICOMP Protection

ISOP

ISENSE

Open-pin

Protection

+0.82V

OLP/STANDBY

100nA

4.9VEND OF SS

Q R

EDR

END OF SS

FAULT

gmv Enhancement

UCC28180 Block Diagram

VPRECHARGE

Rapid Discharge

when

VCC < VCCOFF

FAULT

UVLO

RFREQ

Under voltage lockout +

VCCON

11 .5V

Q R VCCOFF

9.5V

UVLO

CVCC

Auxiliary Supply

VCC

GND

OVP_H

5.35V

OVP_L

SOC

FAULT

End of soft start detector

ICOMPP

Over voltage protection

Over voltage detector

Under voltage detector

ICOMPP

ISOP

UVLO

OLP

SOC

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

8.2 Functional Block Diagram

‘5‘ TEXAS INSTRUMENTS IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

UVLO

VCC ON 11.5 V S Q

CDECOUPLE

VCC

Auxiliary Supply

GND

VCCOFF 9.5 V

UVLO

5 V

VSENSE

VCOMP

FAULT

Soft-Start

gmv

FAULT

END OF SS

(LATCHED)

1.5 V source for

rapid pre-charge

of VCOMP prior

to Soft-Start

ISS = –40 uA

for VSENSE < 4.25 V

during Soft-Start

–

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

8.3 Feature Description

8.3.1 Soft Start

Soft-Start controls the rate of rise of VCOMP in order to obtain a linear control of the increasing duty cycle as a

function of time. VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO,

ICOMPP, ISOP and OLP (Open-Loop Protection)/STANDBY. Once the fault condition is released, an initial pre-

charge source rapidly charges VCOMP to 1.5 V. After that point, a constant 40 µA of current is sourced into the

compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85%

of its final value. At this point, the sourcing current decreases until the output voltage reaches its final rated

voltage. The soft-start time is controlled by the voltage error amplifier compensation capacitor values selected,

and is user programmable based on desired loop crossover frequency. Once the output voltage exceeds 98% of

rated voltage, soft start is over, the initial pre-charge source is disconnected, and EDR is no longer inhibited.

Figure 23. Soft Start

8.3.2 System Protection

System-level protection features help keep the system within safe operating limits.

8.3.3 VCC Undervoltage LockOut (UVLO)

Figure 24. UVLO

l TEXAS INSTRUMENTS

UCC28180

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Product Folder Links: UCC28180

Feature Description (continued)

During startup, Under-Voltage LockOut (UVLO) keeps the device in the off state until VCC rises above the 11.5-

V enable threshold, VCCON. With a typical 1.7 V of hysteresis on UVLO to increase noise immunity, the device

turns off when VCC drops to the 9.5-V disable threshold, VCCOFF.

If, during a brief AC-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT

circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP

capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current

surge should the AC-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically,

these capacitors can be discharged to less than 1 V within 150 ms of loss of VCC.

8.3.4 Output Overvoltage Protection (OVP)

There are two levels of OVP: When VSENSE exceeds 107% (VOVP_L) of the reference voltage, a 4-kΩresistor

connects VCOMP to ground to rapidly discharge VCOMP. If VSENSE exceeds 109% (VOVP_H) of the reference

voltage, GATE output is disabled until VSENSE drops below 102% of the reference voltage.

8.3.5 Open Loop Protection/Standby (OLP/Standby)

If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE

input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To

prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16.5% of its rated

voltage, causing VSENSE to fall below 0.82 V, the device is put in standby, a state where the PWM switching is

halted and the device is still on but draws standby current below 2.95 mA. This shutdown feature also gives the

designer the option of pulling VSENSE low with an external switch (standby function).

8.3.6 ISENSE Open-Pin Protection (ISOP)

If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then

it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an

internal pull-up source drives ISENSE above 0.085 V so that a detector forces a state where the PWM switching

is halted and the device is still on but draws standby current below 2.95 mA. This shutdown feature avoids

continual operation in OVP and severely distorted input current.

8.3.7 ICOMP Open-Pin Protection (ICOMPP)

If the ICOMP pin shorts to ground, then the GATE output increases to maximum duty cycle. To prevent this,

once ICOMP pin voltage falls below 0.2 V, the PWM switching is halted and the device is still on but draws

standby current below 2.95 mA .

8.3.8 FAULT Protection

VCC UVLO, OLP/Standby, ISOP and ICOMPP funtions constitute the fault protection feature in the UCC28180.

Under fault protection, VCOMP pin is pulled low and the device is in standby.

8.3.9 Output Overvoltage Detection (OVD), Undervoltage Detection (UVD) and Enhanced Dynamic

Response (EDR)

During normal operation, small perturbations on the PFC output voltage rarely exceed ±5% deviation and the

normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the

output voltage perturbation exceeds ±5%, an output over-voltage (OVD) or under-voltage (UVD) is detected and

Enhanced Dynamic Response (EDR) acts to speed up the slow response of the low-bandwidth voltage loop.

During EDR, the transconductance of the voltage error amplifier is increased approximately five times to speed

charging or discharging the voltage-loop compensation capacitors to the level required for regulation. EDR is

disabled when 5.25 V > VSENSE > 4.75 V. The EDR feature is not activated until soft start is completed. The

UVD is disabled during soft over protection (SOC) condition (since UVD and SOC conflict with each other).

*9 TEXAS INSTRUMENTS

Over Voltage Protection

Enhanced Dynamic Response

Open Loop Protection/ Standby

Soft-Start Complete

OPEN LOOP

PROTECTION/STANDBY

RFB1

Output Voltage

Standby

OLP/STANDBY

RFB2

OVERVOLTAGE

DETECTION

EDR

VSENSE

Optional

UNDERVOLTAGE

DETECTION EDR

4.75 V

5.25 V

0.82 V

SOFT-START COMPLETE 4.9 V END OF SS

5.10 V

S Q

5.35 V

OVP_H

OVERVOLTAGE

PROTECTION

5.45 V

OVP_L

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

Feature Description (continued)

Figure 25. OVP_H, OVP_L, EDR, OLP, Soft Start Complete

8.3.10 Overcurrent Protection

Inductor current is sensed by RISENSE, a low value resistor in the return path of input rectifier. The other side of

the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is

always negative. The voltage at ISENSE is buffered by a fixed gain of -2.5 to provide a positive internal signal to

the current functions. There are two overcurrent protection features; Soft Overcurrent (SOC) protects against an

overload on the output and Peak Current Limit (PCL) protects against inductor saturation.

‘5‘ TEXAS INSTRUMENTS LJ

PCL

ISENSE

V / 2.5

( )

RISENSE IN _ RMS(max) ISENSE

P I R=

SOC(min)

ISENSE

L _ PEAK(max)

R1.1 I

PCL

ISENSE

Soft Over Current (SOC)

RISENSE

RISENSEfilter

+±

CISENSEfilter

(Optional)

LINE

INPUT VOUT

0.72V

Peak Current Limit (PCL)

SOC

-2.5x

300ns

Leading Edge

Blanking

VISOP

0.082V ISOP

IISOP

2µA

ISENSE Open-Pin

Protection (ISOP)

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

Feature Description (continued)

Figure 26. Soft Overcurrent/Peak-Current Limit

8.3.11 Soft Overcurrent (SOC)

Soft Overcurrent (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE

reaches –0.285 V. This is a soft control as it does not directly switch off the gate driver. Instead a 4-kΩresistor

connects VCOMP to ground to discharge VCOMP and the control loop is adjusted to reduce the PWM duty

cycle. The under-voltage detection (UVD) is disabled during SOC.

8.3.12 Peak Current Limit (PCL)

Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE

reaches –0.4 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked

to improve noise immunity against false triggering.

8.3.13 Current Sense Resistor, RISENSE

The current sense resistor, RISENSE, is sized using the minimum threshold value of Soft Over Current (SOC),

VSOC(min) . To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle, the

resistor is sized for an overload current of 10% more than the peak inductor current,

(1)

Since RISENSE “sees” the average input current, worst-case power dissipation occurs at input low-line when input

current is at its maximum. Power dissipated by the sense resistor is given by:

(2)

Peak current limit (PCL) protection turns off the output driver when the voltage across the sense resistor reaches

the PCL threshold, VPCL. The absolute maximum peak current, IPCL, is given by:

(3)

lﬁmﬁ INSTRUMENTS :ZFV K27“ TIT TIT

VCC

GND

PWM

8GATE

Gate Driver

S Q

QR Pre-Drive and

Clamp Circuit

PCL

Clock

OVP_H

FAULT

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

Feature Description (continued)

8.3.14 ISENSE Pin

The voltage at the ISENSE pin should be limited between 0 V and –1.1 V. Inrush currents at start-up have the

potential to drive the ISENSE pin significantly more negative so a diode clamp should be used between ISENSE

and GND to prevent the ISENSE pin going more negative than 1.1 V, (see Figure 26). The diode Vf should be

greater than the maximum PCL threshold (–0.438 V) and less than –1.1 V across temperature and component

variations.

8.3.15 Gate Driver

The GATE output is designed with a current-optimized structure to directly drive large values of total

MOSFET/IGBT gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the

MOSFET gate to 15.2 V (typical). When VCC voltage is below the UVLO level, the GATE output is held in the off

state. An external gate drive resistor, RGATE, can be used to limit the rise and fall times and dampen ringing

caused by parasitic inductances and capacitances of the gate drive circuit and to reduce EMI. The final value of

the resistor depends upon the parasitic elements associated with the layout and other considerations. A 10-kΩ

resistor close to the gate of the MOSFET/IGBT, between the gate and ground, discharges stray gate capacitance

and helps protect against inadvertent dv/dt-triggered turn-on.

Figure 27. Gate Driver

8.3.16 Current Loop

The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator

(PWM) stage, the external boost inductor stage and the external current sensing resistor.

8.3.17 ISENSE and ICOMP Functions

The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The

internal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. The

voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the

ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is

determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide AC-line

voltage range.

ICOMP is connected to 3-V internally whenever OVP_H, ISOP, or OLP is triggered.

8.3.18 Pulse Width Modulator

The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output

signal which is high whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined by

a non-linear function of the internal VCOMP voltage.

l TEXAS INSTRUMENTS <7 pwm="" cycle="" a="" v="">

tON tOFF

VICOMP

VRAMP = F(VCOMP)

PWM cycle

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

Feature Description (continued)

The PWM output signal always starts low at the beginning of the cycle, triggered by the internal clock. The output

stays low for a minimum off-time, tOFF_min, after which the ramp rises linearly to intersect the ICOMP voltage. The

ramp-ICOMP intersection determines tOFF, and hence DOFF. Since DOFF = VIN/VOUT by the boost-topology

equation, and since VIN is sinusoidal in wave-shape, and since ICOMP is proportional to the inductor current, it

follows that the control loop forces the inductor current to follow the input voltage wave-shape to maintain boost

regulation. Therefore, the average input current is also sinusoidal in wave-shape.

Figure 28. PWM Generation

8.3.19 Control Logic

The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various

protection functions incorporated into the device. The GATE output duty-cycle may be as high as 98%, but

always has a minimum off-time tOFF_min. Normal duty-cycle operation can be interrupted directly by OVP_H and

PCL. UVLO, ISOP, ICOMMP and OLP/Standby also terminate the GATE output pulse, and further inhibit output

until the SS operation can begin.

8.3.20 Voltage Loop

The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing

stage, the voltage error amplifier stage, and the non-linear gain generation.

8.3.21 Output Sensing

A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control

loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference

voltage.

The very low bias current at the VSENSE input allows the choice of the highest practicable resistor values for

lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves to filter the signal

in a high-noise environment. This filter time constant should generally be less than 100 µs.

8.3.22 Voltage Error Amplifier

The transconductance error amplifier (gmv) generates an output current proportional to the difference between the

voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges

the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system

operating conditions. Proper selection of the compensation network components leads to a stable PFC pre-

regulator over the entire AC-line range and 0% to 100% load range. The total capacitance also determines the

rate-of-rise of the VCOMP voltage at Soft Start, as discussed earlier.

l TEXAS INSTRUMENTS

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

Feature Description (continued)

The amplifier output VCOMP is pulled to GND during any fault or standby condition to discharge the

compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays

complete discharge for their respective time constant (which may be several hundred milliseconds). If VCC bias

voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large

capacitor could be left with substantial voltage on it, negating the benefit of a subsequent Soft Start. The

UCC28180 incorporates a parallel discharge path which operates without VCC bias, to further discharge the

compensation network after VCC is removed.

If the output voltage perturbations exceed ±5%, and output over-voltage (OVD) or under-voltage (UVD) is

detected, the OVD or UVD function invokes EDR which immediately increases the voltage error amplifier

transconductance to about 280 µS. This higher gain facilitates faster charging or discharging the compensation

capacitors to the new operating level. When output voltage perturbations greater than 107%VREF appear at the

VSENSE input, a 4-kΩresistor connects VCOMP to ground to quickly reduce VCOMP voltage. When output

voltage perturbations are greater than 109%VREF, the GATE output is shut off until VSENSE drops below 102%

of regulation.

8.3.23 Non-Linear Gain Generation

The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage is subject

to modification by the SOC function, as discussed earlier.

Together the current gain and the PWM slope adjust to the different system operating conditions (set by the AC-

line voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor, input-

current wave shape following that of the input voltage.

8.4 Device Functional Modes

This device has no functional modes.

l TEXAS INSTRUMENTS

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC28180 is a switch-mode controller used in boost converters for power factor correction operating at a

fixed frequency in continuous conduction mode. The UCC28180 requires few external components to operate as

an active PFC pre-regulator. The operating switching frequency can be programmed from 18 kHz to 250 kHz

simply by connecting the FREQ pin to ground through a resistor.

The internal 5-V reference voltage provides for accurate output voltage regulation over the typical world-wide 85-

VAC to 265-VAC mains input range from zero to full output load. The usable system load ranges from 100 W to

few kW.

Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the

sinusoidal input voltage under continuous inductor current conditions. Under light-load conditions, depending on

the boost inductor value, the inductor current may go discontinuous but still meet Class-A/D requirements of IEC

61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by generating

a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal gain

parameters for maintaining a low-distortion, steady-state, input-current wave shape.

l TEXAS INSTRUMENTS

GND

TP9

TP12

LINE

EARTH

Bias

12Vdc

S10K275E2

VAR1

47 µF

2200 pF

5 mH

0603

GND_EARTH

2200 pF

0.47 µF

1000 pF

JP1

0.1 µF

C12

22.6k

10.0k

820 pF

C15

TP10

270 µF

C16

TP11

0.1 µF

C18

VOUT RTN

+VOUT

5 ohm

t°

RT1

221

4.7µF

C13

NEUTRAL

HS1 COMMON TO Q1, BR1, AND D3

0.47 µF

1 µF

C11

2700pF

0.47µF

C14 13.3k

R13

340k

R11

332k

GND

0.1 µF

C17

3.3

MBR140SFT1G

BR1

GBU8J-BP

332k

R10

R12

C3D04060A

49.9

SPP20N60C3

HS1

COMPONENTS MAY GET HOT

WARNING! HIGH VOLTAGE

NOTES:

LINE INPUT VOLTAGE: 85 VRMS - 265 VRMS, 47 Hz - 63 Hz

PEAK INPUT CURRENT: 7 A

OUTPUT VOLTAGE: 390 VDC nominal

MAXIMUM OUTPUT POWER: 360 W

MAXIMUM OUTPUT CURRENT: 0.923 A

LINE

GND

ICOMP

ISENSE

FREQ

4VCOMP 5

VSENSE 6

VCC 7

GATE 8

UCC28180D

0.33 µF

C10

327 µH

250 VAC

8 A

1N5406

TP6

TP8

TP5

TP4

TP2

TP3

TP7

TP1

1Do Not Populate

Vin = 85 VAC to 265 VAC, 47 Hz to 63 Hz

0.032

17.8k

OUTPUT: 390 VDC NOMINAL, 0.923 A MAX

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

9.2 Typical Application

Figure 29. Design Example Schematic

l TEXAS INSTRUMENTS

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

Typical Application (continued)

9.2.1 Design Requirements

This example illustrates the design process and component selection for a continuous mode power factor

correction boost converter utilizing the UCC28180. The pertinent design equations are shown for a universal

input, 360-W PFC converter with an output voltage of 390 V.

Table 1. Design Goal Parameters

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT CHARACTERISTICS

VIN Input voltage 85 265 VAC

fLINE Input frequency 47 63 Hz

IIN(peak) Peak input current VIN = VIN(min),

IOUT = IOUT(max) 7 A

OUTPUT CHARACTERISTICS

VOUT Output voltage VIN(min) ≤VIN ≤VIN(max),

fLINE(min) ≤fLINE≤fLINE(max),

IOUT ≤IOUT(max)

379 390 402 VDC

Line Regulation VIN(min) ≤VIN≤VIN(max),

IOUT = IOUT(max) 5%

Load Regulation

VIN = 115 VAC,

fLINE = 60 Hz,

IOUT(min) ≤IOUT ≤IOUT(max)

VIN = 230 VAC,

fLINE = 60 Hz,

IOUT(min)≤IOUT ≤IOUT(max)

IOUT Output Load Current VIN(min) ≤VIN ≤VIN(max)

fLINE(min) ≤fLINE ≤fLINE(max) 0 0.923 A

POUT Output Power VIN(min) ≤VIN ≤VIN(max)

fLINE(min) ≤fLINE ≤fLINE(max) 0 360 W

VRIPPLE(SW) High frequency

Output voltage ripple

VIN = 115 VAC,

fLINE = 60 Hz

IOUT = IOUT(max)

2.5 3.9

VP-P

VIN = 230 VAC,

fLINE = 50 Hz

IOUT = IOUT(max)

2.5 3.9

VRIPPLE(f_LINE

)

Line frequency

Output voltage ripple

VIN = 115 VAC,

fLINE = 60 Hz,

IOUT = IOUT(max)

11.6 19.5

VP-P

VIN = 230 VAC,

fLINE = 50 Hz,

IOUT = IOUT(max)

13.3 19.5

VOUT(OVP) Output overvoltage

protection 425

VOUT(UVP) Output undervoltage

protection 370

l TEXAS INSTRUMENTS 360W 0.94 XESV >

IN _ AVG(max)

2 6.436 A

I 4.097 A

= =

IN(max)

IN _ AVG(max)

IN(max)

I 2 4.551A 6.436 A= ´ =

IN(max) IN _ RMS(max)

I 2I=

IN _ RMS(max)

360 W

I 4.551A

0.94 85 V 0.99

= =

´ ´

OUT(max)

IN _ RMS(max)

IN(min)

IV PF

OUT(max)

360 W

I 0.923 A

390 V

= @

OUT(max)

OUT

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

Typical Application (continued)

Table 1. Design Goal Parameters (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CONTROL LOOP CHARACTERISTICS

fSW Switching frequency TJ= 25°C 114 120 126 kHz

f(CO) Voltage Loop Bandwidth VIN = 162 VDC,

IOUT = 0.466 A 8 Hz

Voltage Loop Phase

Margin VIN = 162 VDC,

IOUT = 0.466 A 68 °

PF Power Factor VIN = 115 VAC,

IOUT = IOUT(max) 0.99

THD Total harmonic distortion

VIN = 115 VAC,

fLINE = 60 Hz,

IOUT = IOUT(max)

4.3% 10%

VIN = 230 VAC,

fLINE = 50 Hz

IOUT = IOUT(max)

4% 10%

ηFull load efficiency VIN = 115 VAC,

fLINE = 60 Hz,

IOUT = IOUT(max)

94%

Ambient temperature 25 °C

9.2.2 Detailed Design Procedure

9.2.2.1 Current Calculations

The input fuse, bridge rectifier, and input capacitor are selected based upon the input current calculations. First,

determine the maximum average output current, IOUT(max):

(4)

(5)

The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the

efficiency and power factor initial assumptions:

(6)

(7)

Based upon the calculated RMS value, the maximum input current, IIN (max), and the maximum average input

current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined.

(8)

(9)

(10)

(11)

TEXAS INSTRUMENTS R sz INT + TYPX sw ’ TVPX TVP RF 65kHZ 32.7k 1M $2 x Q + SEX 7 SEX \\‘ Pa 2VF GEII ) PB =2><1v><4.097a=8.195w>

BRIDGE

P 2 1V 4.097 A 8.195 W= ´ ´ =

BRIDGE F _ BRIDGE IN _ AVG(max)

P 2 V I=

115

165

215

265

0 20 40 60 80 100 120 140

FSW ± Switching Frequency (kHz)

RFREQ (KŸ)

C001

FREQ

65kHz 32.7k 1M

R 17.451k

(120kHz 1M ) (32.7k 120kHz) (32.7k 65kHz)

´ W ´ W

= = W

´ W + W ´ - W ´

TYP TYP INT

FREQ

SW INT TYP SW TYP TYP

f R R

R(f R ) (R f ) (R f )

´ ´

´ + ´ - ´

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

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9.2.2.2 Switching Frequency

The UCC28180 switching frequency is user programmable with a single resistor on the FREQ pin to ground. For

this design, the switching frequency, fSW, was chosen to be 120 kHz. Figure 30 (same as Figure 1) could be

used to select the suitable resistor to program the switching frequency or the value can be calculated using

constant scaling values of fTYP and RTYP. In all cases, fTYP is a constant that is equal to 65 kHz, RINT is a constant

that is equal to 1 MΩ, and RTYP is a constant that is equal to 32.7 kΩ. Simply applying the calculation below

yields the appropriate resistor that should be placed between FREQ and GND:

(12)

(13)

A typical value of 17.8 kΩfor the FREQ resistor results in a switching frequency of 118 kHz.

Figure 30. Frequency vs. RFREQ

9.2.2.3 Bridge Rectifier

The input bridge rectifier must have an average current capability that exceeds the input average current.

Assuming a forward voltage drop, VF_BRIDGE, of 1 V across the rectifier diodes, BR1, the power loss in the input

bridge, PBRIDGE, can be calculated:

(14)

(15)

Heat sinking will be required to maintain operation within the bridge rectifier’s safe operating area.

9.2.2.4 Inductor Ripple Current

The UCC28180 is a Continuous Conduction Mode (CCM) controller but if the chosen inductor allows relatively

high-ripple current, the converter will be forced to operate in Discontinuous Mode (DCM) at light loads and at the

higher input voltage range. High-inductor ripple current has an impact on the CCM/DCM boundary and results in

higher light-load THD, and also affects the choices for the input capacitor, RSENSE and CICOMP values. Allowing an

inductor ripple current, ΔIRIPPLE, of 20% or less will result in CCM operation over the majority of the operating

range but requires a boost inductor that has a higher inductance value and the inductor itself will be physically

large. As with all converter designs, decisions must be made at the onset in order to optimize performance with

size and cost. In this design example, the inductor is sized in such a way as to allow a greater amount of ripple

current in order to minimize space with the understanding that the converter operates in DCM at the higher input

voltages and at light loads but optimized for a nominal input voltage of 115 VAC at full load. Although specifically

defined as a CCM controller, the UCC28180 is shown in this application to meet the overall performance goals

while transitioning into DCM at high-line voltage, at a higher load level.

l TEXAS INSTRUMENTS IRIPPLE IRIPPLEIIN(max) AR‘PPLE = 0-4 I RIPPLE= X = V‘NiRWPLE VRIPPLE, \NVINiRECﬂFIEDOmn) A R‘PPLEJN 0-07 V\ ‘r \N \4 f v V‘NiRWPLE V | Cl C: 2.575A F x x | 'R L 2 I 2.575A L 2 LB SW R‘PPLE L 390V 0.5(1 0.5) B 118kHzx2.575A LBST 327 H IR SW BST IR 2.527A

L _ PEAK(max)

2.527 A

I 6.436 A 7.7 A

= + =

RIPPLE(actual)

390 V 0.5(1 0.5)

I 2.527 A

118kHz 327 H

´ -

= =

´ m

OUT

RIPPLE(actual)

SW BST

V D(1 D)

If L

BST

L 327 H= m

BST(min)

390 V 0.5(1 0.5)

L 321 H

118kHz 2.575 A

´ -

³ ³ m

OUT

BST(min)

SW RIPPLE

V D(1 D)

Lf I

L _ PEAK(max)

2.575 A

I 6.436 A 7.724 A

= + =

RIPPLE

L _ PEAK(max) IN(max)

I I 2

= +

2.575 A

C 0.324 F

8 118kHz 8.415 V

= = m

´ ´

RIPPLE

SW IN _ RIPPLE

C8f V

IN _ RIPPLE

V 0.07 120 V 8.415 V= ´ =

IN _ RECTIFIED

V 2 85 V 120 V= ´ =

IN _ RECTIFIED IN

V 2V=

RIPPLE _ IN

V 0.07D =

IN _ RIPPLE RIPPLE _ IN IN _ RECTIFIED(min)

V V V= D

RIPPLE

I 0.4 6.436 A 2.575 A= ´ =

RIPPLE

I 0.4D =

RIPPLE RIPPLE IN(max)

I I I= D

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

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9.2.2.5 Input Capacitor

The input capacitor must be selected based upon the input ripple current and an acceptable high frequency input

voltage ripple. Allowing an inductor ripple current, ΔIRIPPLE, of 40% and a high frequency voltage ripple factor,

ΔVRIPPLE_IN, of 7%, the maximum input capacitor value, CIN, is calculated by first determining the input ripple

current, IRIPPLE, and the input voltage ripple, VIN_RIPPLE:

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

The recommended value for the input x-capacitor can now be calculated:

(24)

(25)

A standard value 0.33-µF Y2/X2 film capacitor is used.

9.2.2.6 Boost Inductor

Based upon the allowable inductor ripple current discussed above, the boost inductor, LBST, is selected after

determining the maximum inductor peak current, IL_PEAK:

(26)

(27)

The minimum value of the boost inductor is calculated based upon the acceptable ripple current, IRIPPLE, at a

worst case duty cycle of 0.5:

(28)

(29)

The recommended minimum value for the boost inductor assuming a 40% ripple current is 321 µH; the actual

value of the boost inductor that will be used is 327 µH. With this actual value used, the actual resultant inductor

current ripple will be:

(30)

(31)

(32)

(33)

TEXAS INSTRUMENTS v v D O \ OUT \4 f v D 390v 120v 0-692 390v PD vF Clo 0.5fS vO QRR VF 125" 1V QRR : nC PD ( ) ( PC 2 on)125‘C RDS(an)125“C 0-359

P 118kHz 0.5 390 V 6.436A(5ns 4.5ns) 0.5 780pF 390 V 8.407 W

é ù

= ´ ´ + + ´ ´ =

ë û

SW SW OUT IN(max) r f OSS OUT

P f 0.5V I (t t ) 0.5C V

é ù

= + +

ë û

OSS

t 5ns

t 4.5ns

C 780pF

COND

P 3.639 A 0.35 4.636 W= ´ W =

DS _ RMS

360 W 16 120 V

I 2 3.639 A

120 V 3 390 V

= - =

p ´

OUT(max) IN _ RECTIFIED(min)

DS _ RMS

IN _ RECTIFIED(min) OUT

P 16V

I 2

V 3 V

= -

DS(on)125 C

R 0.35

°= W

COND DS _ RMS DS(on)125 C

P I R °

( ) ( )

DIODE

P 1V 0.923 A 0.5 119kHz 390 V 0nC 0.923 W= ´ + ´ ´ ´ =

Q 0nC=

F _ 125 C

V 1V

°=

DIODE F _ 125C OUT(max) SW OUT RR

P V I 0.5f V Q= +

(max)

390 V 120 V

DUTY 0.692

390 V

= =

IN _ RECTIFIED(min)

V 2 85 V 120 V= ´ =

OUT IN _ RECTIFIED(min)

(max)

OUT

V V

DUTY V

UCC28180

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The duty cycle is a function of the rectified input voltage and will be continuously changing over the half line

cycle. The duty cycle, DUTY(max), can be calculated at the peak of the minimum input voltage:

(34)

(35)

(36)

9.2.2.7 Boost Diode

The diode losses are estimated based upon the forward voltage drop, VF, at 125°C and the reverse recovery

charge, QRR, of the diode. Using a silicon carbide Schottky diode, although more expensive, will essentially

eliminate the reverse recovery losses and result in less power dissipation:

(37)

(38)

(39)

(40)

This output diode should have a blocking voltage that exceeds the output over voltage of the converter and be

attached to an appropriately sized heat sink.

9.2.2.8 Switching Element

The MOSFET/IGBT switch will be driven by a GATE output that is clamped at 15.2 V for VCC bias voltages

greater than 15.2 V. An external gate drive resistor is recommended to limit the rise time and to dampen any

ringing caused by the parasitic inductances and capacitances of the gate drive circuit; this will also help in

meeting any EMI requirements of the converter. The design example uses a 3.3-Ωresistor; the final value of any

design is dependent upon the parasitic elements associated with the layout of the design. To facilitate a fast turn

off, a standard 40-V, 1-A Schottky diode is placed anti-parallel with the gate drive resistor. A 10-kΩresistor is

placed between the gate of the MOSFET/IGBT and ground to discharge the gate capacitance and protect from

inadvertent dv/dt triggered turn-on.

The conduction losses of the switch MOSFET, in this design are estimated using the RDS(on) at 125°C, found in

the device data sheet, and the calculated drain to source RMS current, IDS_RMS:

(41)

(42)

(43)

(44)

(45)

The switching losses are estimated using the rise time, tr, and fall time, tf, of the MOSFET gate, and the output

capacitance losses.

tr=5 ns (46)

(47)

tr=5 ns (48)

l IEXAS INSTRUMENTS PCOND + PSW : 4.636W +8.407W :13.042w V R S 1 .1 R 0.259 V (1 7.7 A x1.1 2 PR SE 2 PRSENSE = X 9 = W VP '1: SENSE 0.438 V IF. 0 2P 1 CO 0 C0 2 360W 21.28ms F 390V 7300V VOUTiRIPPLEmp) 0-05VOUT vomimppmpp) 0.05 390v 19.5vPP V0 V0 '0 0.923A

OUT _ RIPPLE(pp)

0.923A

V 5.789 V

2 (2 47Hz) 270 F

= =

p ´ ´ m

OUT

OUT _ RIPPLE(pp)

LINE(min) OUT

V2 (2f )C

OUT _ RIPPLE(pp) PP

V 0.05 390 V 19.5 V< ´ =

OUT _ RIPPLE(pp) OUT

V 0.05 V<

OUT(min) 2 2

2 360 W 21.28ms

C 247 F

390 V 300 V

´ ´

³ ³ m

OUT(max) HOLDUP

OUT(min) 2 2

OUT OUT _ HOLDUP(min)

2P t

CV V

PCL

0.438 V

I 13.688 A

0.032

= =

PCL(max)

PCL

SENSE

RSENSE

P 4.551A 0.032 0.663 W= ´ W =

RSENSE IN _ RMS(max) SENSE

P I R=

SENSE

0.259 V

R 0.032

7.7 A 1.1

= = W

SOC(min)

SENSE

L _ PEAK(max)

RI 1.1

COND SW

P P 4.636 W 8.407 W 13.042 W+ = + =

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

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Total FET losses

(49)

The MOSFET requires an appropriately sized heat sink.

9.2.2.9 Sense Resistor

To accommodate the gain of the non-linear power limit, the sense resistor, RSENSE, is sized such that it triggers

the soft over current at 10% higher than the maximum peak inductor current using the minimum soft over current

threshold of the ISENSE pin, VSOC, of ISENSE equal to 0.265 V.

(50)

(51)

The power dissipated across the sense resistor, PRSENSE, must be calculated:

(52)

(53)

The peak current limit, PCL, protection feature is triggered when current through the sense resistor results in the

voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL threshold

is used:

(54)

(55)

To protect the device from inrush current, a standard 220-Ωresistor, RISENSE, is placed in series with the ISENSE

pin. A 1000-pF capacitor is placed close to the device to improve noise immunity on the ISENSE pin.

9.2.2.10 Output Capacitor

The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream

converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle,

tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is:

(56)

(57)

It is advisable to de-rate this capacitor value by 10%; the actual capacitor used is 270 µF.

Verifying that the maximum peak-to-peak output ripple voltage will be less than 5% of the output voltage ensures

that the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the

controller. If the output ripple voltage is greater than 5% of the regulated output voltage, a larger output capacitor

is required. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple

current of the output capacitor is calculated:

(58)

(59)

(60)

(61)

TEXAS INSTRUMENTS IO '0 T 0.923 A IC ﬁ VREFRF vOVD =1.05vREF =1.05x5V = 5.25v ( vO 7 FBZ vo £71 FB2 Vuvo = REF = X = V

UVD REF

V 0.95 V 0.95 5 V 4.75 V= = ´ =

FB1 FB2

OUT(ovp) REF

FB2

R R

V 1.09 V 426.4 V

æ ö

= ´ =

ç ÷

è ø

OUT(ovd)

1M 13k

V 5.25 V 410.7 V

13k

æ ö

W + W

= ´ =

ç ÷

è ø

FB1 FB2

OUT(ovd) OVD

FB2

R R

V V R

æ ö

=ç ÷

è ø

OVD REF

V 1.05 V 1.05 5 V 5.25 V= = ´ =

FB2

5 V 1M

R 13.04k

390 V 5 V

´ W

= = W

REF FB1

FB2

OUT REF

V R

V V

2 2

COUT _ RMS(total)

I 0.653 A 1.848 A 1.96 A= + =

2 2

COUT _ RMS(total) COUT _ 2fline COUT _ HF

I I I= +

COUT _ HF

16 390 V

I 0.923 A 1.5 1.848 A

3 120 V

= - =

p ´

OUT

COUT _ HF OUT(max)

IN _ RECTIFIED(min)

16 V

I I 1.5

3 V

= -

COUT _ 2fline

0.923 A

I 0.653 A

= =

OUT(max)

COUT _ 2fline

UCC28180

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The required ripple current rating at twice the line frequency is equal to:

(62)

(63)

There is a high frequency ripple current through the output capacitor:

(64)

(65)

The total ripple current in the output capacitor is the combination of both and the output capacitor must be

selected accordingly:

(66)

(67)

9.2.2.11 Output Voltage Set Point

For low power dissipation and minimal contribution to the voltage set point, it is recommended to use 1 MΩfor

the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum

allowable voltage across each. Using the internal 5-V reference, VREF, the bottom divider resistor, RFB2, is

selected to meet the output voltage design goals.

(68)

(69)

A standard value 13-kΩresistor for RFB2 results in a nominal output voltage set point of 391 V.

An output over voltage is detected when the output voltage exceeds its nominal set-point level by 5%, as

measured when the voltage at VSENSE is 105% of the reference voltage, VREF. At this threshold, the enhanced

dynamic response (EDR) is triggered and the non-linear gain to the voltage error amplifier will increase the

transconductance to VCOMP and quickly return the output to its normal regulated value. This EDR threshold

occurs when the output voltage reaches the VOUT(ovd) level:

(70)

(71)

(72)

In the event of an extreme output over voltage event, the GATE output will be disabled if the output voltage

exceeds its nominal set-point value by 9%. The output voltage, VOUT(ovp), at which this protection feature is

triggered is calculated as follows:

(73)

An output under voltage is detected when the output voltage falls below 5% below its nominal set-point as

measured when the voltage at VSENSE is 95% of the reference voltage, VREF:

(74)

l TEXAS INSTRUMENTS 10 s FB2 lNiRMS FQ

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

M1M2

VCOMP (V)

C007

1 2 2

0.923 A 390 V 2.5 0.032 7 V

M M 0.751

0.92 115 V 8.475 s

´ ´ ´ W ´

= = m

´ ´ m

K 8.475 s

118kHz

K 7

= = m

OUT(max) OUT SENSE 1

1 2 2

IN _ RMS FQ

I V 2.5R K

M M V K

VSENSE

FB2

10 s

C 769pF

= =

OUT(uvp)

1M 13k

V 4.75 V 371.6 V

13k

æ ö

W + W

= ´ =

ç ÷

è ø

FB1 FB2

OUT(uvp) UVD

FB2

R R

V V R

æ ö

=ç ÷

è ø

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

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Product Folder Links: UCC28180

(75)

(76)

A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that

the RC time constant is limited to approximately 10 µs so as not to significantly reduce the control response time

to output voltage deviations.

(77)

The closest standard value of 820 pF was used on VSENSE for a time constant of 10.66 µs.

9.2.2.12 Loop Compensation

The current loop is compensated first by determining the product of the internal loop variables, M1M2, using the

internal controller constants K1and KFQ. Compensation is optimized maximum load and nominal input voltage,

115 VAC is used for the nominal line voltage for this design:

(78)

(79)

(80)

The VCOMP operating point is found on the following chart, M1M2vs. VCOMP. Once the M1M2result is

calculated above, find the resultant VCOMP voltage at that operating point to calculate the individual M1and M2

components.

Figure 31. M1M2 vs. VCOMP

For the given M1M2of 0.751 V/µs, the VCOMP approximately equal to 3 V, as shown in Figure 31.

The individual loop factors, M1which is the current loop gain factor, and M2which is the voltage loop PWM ramp

slope, are calculated using the following conditions:

The M1non-linear current loop gain factor follows the following identities:

l TEXAS INSTRUMENTS M1 : 0.068 , 0.088 , 0.401 =0.366 118kHz 1 0.0083) 0.0155) 0.0586) 0.0586)

118kHz V V

M (0.1148 3.004 0.1746 3.004 0.0586) 1.035

65kHz s s

= ´ ´ ´ - ´ + =

m m

M 0=

M (0.1148 VCOMP 0.1746 VCOMP 0.0586)

65kHz s

= ´ ´ ´ - ´ +

M (0.1148 VCOMP 0.1746 VCOMP 0.0586)

65kHz s

= ´ ´ ´ - ´ +

M (0.0572 VCOMP 0.0597 VCOMP 0.0155)

65kHz s

= ´ ´ ´ - ´ +

M (0.0166 VCOMP 0.0083)

65kHz s

= ´ ´ ´ -

M 0=

V V

0.747 0.751

s s

m m

1 2 1 2

M M M M´ @

1 2

V V

M M 0.538 1.388 0.747

s s

´ = ´ =

m m

118kHz V V

M 0.1223 (3 0.5) 1.388

65kHz s s

= ´ ´ - =

m m

M 2.056

65kHz s

= ´

M 0.1223 (VCOMP 0.5)

65kHz s

= ´ ´ -

M 0

M 0.313 2.45 0.401 0.366= ´ - =

M 1.007=

M 0.313 VCOMP 0.401= ´ -

M 0.156 VCOMP 0.088= ´ -

M 0.068=

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if VCOMP < 1 V (81)

if 1 V < VCOMP < 2 V (82)

if 2 V < VCOMP < 4.5 V (83)

if 4.5 V < VCOMP < 5 V (84)

In this example, according to the chart in Figure 31, VCOMP is approximately equal to 3 V, so M1 is calculated

to be approximately equal to 0.366:

(85)

The M2non-linear PWM ramp slope will obey the following relationships:

if VCOMP ≤0.5 V (86)

if 0.5 V ≤VCOMP ≤4.6 V (87)

if 4.6 V ≤VCOMP ≤5 V (88)

In this example, with VCOMP approximately equal to 3 V, M2equals 1.388 V/µs:

(89)

Verify that the product of the individual gain factors, M1and M2, is approximately equal to the M1M2factor

determined above, if not, iterate the VCOMP value and recalculate M1M2

(90)

The product of M1and M2is within 1% of the M1M2factor previously calculated:

(91)

(92)

If more accuracy was desired, iteration results in a VCOMP value of 3.004 V where M1M2and M1x M2are both

equal to 0.751 V/µs.

The non-linear gain variable, M3, can now be calculated:

if VCOMP < 5 V (93)

if 0.5 V < VCOMP < 1 V (94)

if 1 V < VCOMP < 2 V (95)

if 2 V < VCOMP < 4.5 V (96)

if 4.5 V < VCOMP < 4.6 V (97)

if 4.6 V < VCOMP < 5 V (98)

In this example, using 3.004 V for VCOMP for a more precise calculation, M3calculates to 1.035 V/µs:

(99)

l TEXAS INSTRUMENTS CI 9m M1 1 IAVG — F C' 7 x 2 x n x 5 kHz p fl & Z 1 Go K12.5R vD rm X 1 Go ‘ D GF RF 1M§2+13kﬂ

FB2

FB1 FB2

R R

13k

G 0.013

1M 13k

= =

W + W

10 100 1k 10k 100k 1M

±180

±170

±160

±150

±140

±130

±120

±110

±100

±90

±80

±100

±80

±60

±40

±20

100

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C005

( )

CLdB CL

G (f) 20log G (f)=

1 SENSE OUT

CL 2

FQ 1 2 BST 1 ICOMP

mi 1

K 2.5R V 1

G (f) K M M L s(f) K C

s(f) g M

= ´

mi 1

IAVG

g M

f 4.314kHz

K 2 2700pF

= =

´ ´ p ´

ICOMP

0.95mS 0.538

C 2330pF

7 2 5kHz

= =

´ ´ p ´

mi 1

ICOMP

1 IAVG

g M

CK 2 f

UCC28180

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For designs that allow a high inductor ripple current, the current averaging pole, which functions to flatten out the

ripple current on the input of the PWM comparator, should be at least decade before the converter switching

frequency. Analysis on the completed converter may be needed to determine the ideal compensation pole for the

current averaging circuit as too large of a capacitor on ICOMP will add phase lag and increase iTHD where as too

small of an ICOMP capacitor will result in not enough averaging and an unstable current averaging loop. The

frequency of the current averaging pole, fIAVG, is chosen to be at approximately 5 kHz for this design as the

current ripple factor, ∆IRIPPLE, was chosen at the onset of the design process to be 40%, which is large enough to

force DCM operation and result in relatively high inductor ripple current. The required capacitor on ICOMP,

CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier:

(100)

(101)

A standard value 2700-pF capacitor for CICOMP results in a current averaging pole frequency of 4.314 kHz.

(102)

The transfer function of the current loop can be plotted:

(103)

(104)

Figure 32. Bode Plot of the Current Averaging Circuit

The voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and the gain from the

pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator to power stage

pole, fPWM_PS. The plotted result is shown in Figure 32.

(105)

l TEXAS INSTRUMENTS rP 1 fP z is Me V0 GP PWMiPS G

f 10Hz=

( )

VCOMP VCOMP

EA mv

VCOMP VCOMP VCOMP _ P

VCOMP VCOMP _ P

1 s(f)R C

G (f) g

R C C

C C s(f) 1 s(f) C C

é ù

ê ú

=ê ú

é ù

æ ö

ê ú

+ +

ê ú

ç ÷

ê ú

ç ÷

ê ú

è ø

ë û

POLE VCOMP VCOMP VCOMP _ P

VCOMP VCOMP _ P

fR C C

2C C

ZERO

VCOMP VCOMP

2 R C

±100

±90

±80

±70

±60

±50

±40

±30

±20

±10

±100

±80

±60

±40

±20

100

0.01 0.1 1 10 100 1000

Phase (ƒ)

Gain (dB)

Frequency (Hz)

PWM to Power Stage Gain

Total Open Loop Gain

Total Open Loop Phase

C008

( )

VL FB PWM _ PS

VLdB VL

G (f) G G (f)

G (f) 20log G (f)

3 OUT

1 2

PWM _ PS

M V

M M 1V

G (f) s(f)

12 f

PWM _ PS 3

1 SENSE OUT OUT

FQ 1 2 IN(nom)

PWM _ PS 3

fK 2.5R V C

2K M M V

f 1.479Hz

7 2.5 0.032 390V 270 F

8.475 s 0.539 1.392 115 V

= =

´ ´ W ´ ´ m

m ´ ´ ´

UCC28180

www.ti.com

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

(106)

(107)

(108)

Figure 33. Bode Plot of the Open Voltage Loop without Error Amplifier

The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20

Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired

to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.

(109)

(110)

(111)

From Figure 33, the gain of the voltage transfer function at 10 Hz is approximately 0.081 dB. Estimating that the

parallel capacitor, CVCOMP_P, is much smaller than the series capacitor, CVCOMP, the unity gain will be at fV, and

the zero will be at fPWM_PS, the series compensation capacitor is determined:

(112)

l TEXAS INSTRUMENTS C v 10HZ C F x xnx C F R 1 R 1 Q C POLE vcow vcow 1 C 4.7 F F GVLJD'a‘ FE PWM7PS EA ) G D //

100

±150

±100

±50

100

0.01 0.1 1 10 100 1000

Phase (ƒ)

Gain (dB)

Frequency (Hz)

EA Gain

Total Closed Loop Gain

Total Closed Loop Phase Margin

C001

( )

VL _ totaldB VL _ total

G (f) 20log G (f)=

VL _ total FB PWM _ PS EA

G (f) G (f)G (f)G (f)=

VCOMP _ P

4.7 F

C 0.381 F

2 20Hz 22.6kk 4.7 F 1

= = m

´ p ´ ´ W ´ m -

VCOMP

VCOMP _ P

POLE VCOMP VCOMP

C2 f R C 1

p -

VCOMP

R 22.89k

2 1.479Hz 4.7 F

= = W

´ p ´ ´ m

VCOMP

ZERO VCOMP

2 f C

VCOMP

C 4.7 F= m

0 0.081dB

VCOMP

10Hz

56 s

1.479Hz

C 6.08 F

10 2 10Hz

m ´

= = m

´ ´ p ´

0 G (f )

VLdB

PWM _ PS

VCOMP

10 2 f

´ p

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

(113)

(114)

The capacitor for VCOMP must have a voltage rating that is greater than the absolute maximum voltage rating of

the VCOMP pin, which is 7 V. The readily available standard value capacitor that is rated for at least 10 V in the

package size that would fit the application was 4.7 µF and this is the value used for CVCOMP in this design

example.

RVCOMP is calculated using the actual CVCOMP capacitor value.

(115)

(116)

(117)

A 22.6-kΩresistor is used for RVCOMP.

(118)

(119)

A 0.47-µF capacitor is used for CVCOMP_P.

The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 34.

(120)

(121)

Figure 34. Closed Loop Voltage Bode Plot

l TEXAS INSTRUMENTS ms m on M; m an 15 2a mm m a ox noun-1mm mm munmc minimum mm x=u mm 230 VAC 50 Hz le Load

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

AMPLITUDE (A)

HARMONIC NUMBER

PWR 573

EN61000-3-2 Class D max

C005

115 VAC, 60 Hz, Full Load

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

AMPLITUDE (A)

HARMONIC NUMBER

PWR 573

EN61000-3-2 Class D max

C004

230 VAC, 50 Hz, Full Load

0.80

0.81

0.82

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

EFFICIENCY

LOAD (A)

85 VAC, 60 Hz

115 VAC, 60 Hz

230 VAC, 50 HZ

265 VAC, 50 Hz

C001

UCC28180

www.ti.com

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

9.2.3 Application Curve

Figure 35. UCC28180EVM-573 Efficiency

(As a Function of Line Voltage and Load Current) Figure 36. UCC28180EVM-573 Power Factor

(As a Function of Line Voltage and Load Current)

Figure 37. UCC28180EVM-573 Total Harmonic Distortion

(As a Function of Line Voltage and Load Current)

Figure 38. UCC28180EVM-573 Current Harmonics,

(230-VAC, 50-Hz Input, Full Load, Without the Fundamental)

Figure 39. UCC28180EVM-573 Current Harmonics,

(115-VAC, 60-Hz Input, Full Load, Without the Fundamental)

l TEXAS INSTRUMENTS Stale

VCC

VCC(ON) 11.5 V

ICC ICC(ON)

UVLO Soft-Start UVLORun Run

Fault/standby

Controller

State

PWM

State OFF Ramp Regulated OFF Regulated OFF

Soft-

Start

Ramp

VCC(OFF) 9.5 V

ICC(stby)<2.95 mA

ICC(prestart) < 75 µA

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

10 Power Supply Recommendations

10.1 Bias Supply

The UCC28180 operates from an external bias supply. It is recommended that the device be powered from a

regulated auxiliary supply. (This device is not intended to be used from a bootstrap bias supply. A bootstrap bias

supply is fed from the input high voltage through a resistor with sufficient capacitance on VCC to hold up the

voltage on VCC until current can be supplied from a bias winding on the boost inductor. For that reason, the

minimal hysteresis on VCC would require an unreasonable value of hold-up capacitance.)

During normal operation, when the output is regulated, current drawn by the device includes the nominal run

current plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply must take

switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor of 0.1-

µF minimum value from VCC to GND with short, wide traces is recommended.

Figure 40. Device Supply States

The device's bias operates in several states. During startup, VCC Under-Voltage LockOut (UVLO) sets the

minimum operational DC input voltage of the controller. There are two UVLO thresholds. When the UVLO turn-on

threshold is exceeded, the PFC controller turns ON. If the VCC voltage falls below the UVLO turn-off threshold,

the PFC controller turns off. During UVLO, current drawn by the device is minimal. After the device turns on, Soft

Start (SS) is initiated and the boost inductor current is ramped up in a controlled manner to reduce the stress on

the external components and avoids output voltage overshoot. During soft start and after the output is in

regulation, the device draws its normal run current. If any of several fault conditions are encountered or if the

device is put in standby with an external signal, the device draws a reduced standby current.

11 Layout

11.1 Layout Guidelines

As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the

integrity of the ground return. Separating the high di/dt induced noise on the power ground from the low current

quiet signal ground is required for adequate noise immunity. Even with a signal layer PCB design, the pin out of

the UCC28180 is ideally suited to minimize noise on the small signal traces. As shown in Figure 41, the

capacitors on VSENSE, VCOMP, ISENSE, ICOMP, and FREQ (if used) must be all be returned directly to the

portion of the ground plane that is the quiet signal GND and not in high-current return path of the converter,

shown as power GND. The trace from the FREQ pin to the frequency programming resistor should be as short

as possible. It is recommended that the compensation components on ICOMP and VCOMP are located as close

as possible to the UCC28180. Placement of these components should take precedence, paying close attention

to keeping their traces away from high noise areas. The bypass capacitors on VCC must be located physically

close the VCC and GND pins of the UCC28180 but should not be in the immediate path of the signal return.

l TEXAS INSTRUMENTS

UCC28180

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SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

Layout Guidelines (continued)

Other layout considerations should include keeping the switch node as short as possible, with a wide trace to

reduce induced ringing caused by parasitic inductance. Every effort should be made to avoid noise from the

switch node from corrupting the small signal traces with adequate clearance and ground shielding. As some

compromises must be made due to limitation of PCB layers or space constraints, traces that must be made long,

such as the signal from the current sense resistor shown in Figure 41, should be as wide as possible, avoid long

narrow traces.

Table 2. Layout Component Description for Figure 41

LAYOUT COMPONENTS

REFERENCE DESIGNATOR FUNCTION

U1 Controller, UCC28180

Q1 Main switch

D2 Boost diode

R5 RGATE

R7 Pull-down resistor on GATE

D1 Turn-off diode on GATE

D4 ISENSE pin diode

C11, C12 VCC bypass capacitors

C7 ICOMP compensation, CICOMP

R1, C6 Placeholders for additional ICOMP compensation, if needed

C8 ISENSE filter, CISENSE

R2 ISENSE inrush current limiting resistor, RISENSE

R3 Frequency programming resistor, RFREQ

C9 Placeholder for FREQ filter, if needed

R6, C13, C14 VCOMP compensation components, RVCOMP, CVCOMP_P, CVCOMP

C15 VSENSE filter, CVSENSE

R11, R12 RFB1 on VSENSE

R13 RFB2 on VSENSE

UCC28180

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

www.ti.com

Product Folder Links: UCC28180

11.2 Layout Example

Figure 41. Recommended Layout for UCC28180

l TEXAS INSTRUMENTS

UCC28180

www.ti.com

SLUSBQ5D –NOVEMBER 2013–REVISED JULY 2016

Product Folder Links: UCC28180

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

These references, additional design tools, and links to additional references, including design software and

models may be found on the web at http://www.power.ti.com under Technical Documents.

• User Guide, Using the UCC28180EVM-573, 360-W Power Factor Correction,SLUUAT3

• Design Spreadsheet, UCC28180 Design Calculator,SLUC506

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Sample: Sample:

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

UCC28180D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 U28180

UCC28180DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 U28180

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension desIgned Io eeeemmodaIe me component Iengm K0 Dlmenslun desIgned to accommodate me componem Ihlckness 7 w Overall with loe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

UCC28180DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 1

l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC28180DR SOIC D 8 2500 340.5 336.1 25.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 2

l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

UCC28180D D SOIC 8 75 507 8 3940 4.32

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

Pack Materials-Page 3

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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