Texas Instruments 的 SN74ALVCH16601 规格书

{5‘ TEXAS INSTRUMENTS www.li.com u—u—u—u GND[ A3[ Vcc I: A4[ A5[ A6[ GNDE A7[ A8[ A9[ MOE AHE M2[ GNDE M3[ M4[ M5[ Vcc I: M6[ M7[ GND[ MBE UEEI[ LEBA[ 10 11 12 13 14 15 16 17 1a 19 20 21 22 23 24 25 26 27 2a 53 52 51 5a 49 4a 47 45 45 44 43 42 41 4a 39 3a 37 35 35 34 33 32 31 3a 29
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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLKBA
CLKENBA
SN74ALVCH1660118-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
•Member of the Texas Instruments Widebus™Family
•UBT™ (Universal Bus Transceiver) CombinesD-Type Latches and D-Type Flip-Flops forOperation in Transparent, Latched, Clocked,or Clock-Enabled Modes•EPIC™ (Enhanced-Performance ImplantedCMOS) Submicron Process•ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)•Latch-Up Performance Exceeds 250 mA PerJESD 17•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Package Options Include Plastic 300-milShrink Small-Outline (DL) and Thin ShrinkSmall-Outline (DGG) Packages
This 18-bit universal bus transceiver is designed for1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16601 combines D-type latches andD-type flip-flops to allow data flow in transparent,latched, and clocked modes.
Data flow in each direction is controlled byoutput-enable ( OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB and CLKBA)inputs. The clock can be controlled by theclock-enable ( CLKENAB and CLKENBA) inputs. ForA-to-B data flow, the device operates in thetransparent mode when LEAB is high. When LEAB islow, the A data is latched if CLKAB is held at a highor low logic level. If LEAB is low, the A data is storedin the latch/flip-flop on the low-to-high transition ofCLKAB. Output enable OEAB is active low. WhenOEAB is low, the outputs are active. When OEAB ishigh, the outputs are in the high-impedance state.<br/>
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16601 is characterized for operation from -40 °C to 85 °C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
{5i TEXAS INSTRUMENTS www.|l.cnm CLKAB LEAB LEBA CLKEA A1 \—V—/ To 17 Other Channels
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CE
1D
C1
CLK
CE
1D
C1
CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
354
To 17 Other Channels
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
FUNCTION TABLE
(1)
INPUTS
OUTPUT
BCLKENAB OEAB LEAB CLKAB A
X H X X X Z
X L H X L L
X L H X H H
H L L X X B
0
(2)
H L L X X B
0
(2)
L L L ↑L L
L L L ↑H H
L L L H X B
0
(2)
L L L L X B
0
(3)
(1) A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA,LEBA, and CLKBA.(2) Output level before the indicated steady-state input conditions wereestablished, provided that CLKAB was high before LEAB went low(3) Output level before the indicated steady-state input conditions wereestablished
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCH1660118-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 V
Except I/O ports
(2)
-0.5 4.6V
I
Input voltage range VI/O ports
(2) (3)
-0.5 V
CC
+ 0.5
V
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 V
I
IK
Input clamp current V
I
< 0 -50 mA
I
OK
Output clamp current V
O
< 0 -50 mA
I
O
Continuous output current ±50 mA
Continuous current through each V
CC
or GND ±100 mA
DGG package 64θ
JA
Package thermal impedance
(4)
°C/WDL package 56
T
stg
Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51.
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 V
V
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 V
V
CC
= 2.7 V to 3.6 V 2
V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 V
V
CC
= 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
V
CC
= 1.65 V -4
V
CC
= 2.3 V -12I
OH
High-level output current mAV
CC
= 2.7 V -12
V
CC
= 3 V -24
V
CC
= 1.65 V 4
V
CC
= 2.3 V 12I
OL
Low-level output current mAV
CC
= 2.7 V 12
V
CC
= 3 V 24
∆t/ ∆v Input transition rise or fall rate 10 ns/V
T
A
Operating free-air temperature -40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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ELECTRICAL CHARACTERISTICS
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= -100 µA 1.65 V to 3.6 V V
CC
- 0.2
I
OH
= -4 mA 1.65 V 1.2
I
OH
= -6 mA 2.3 V 2
V
OH
2.3 V 1.7 V
I
OH
= -12 mA 2.7 V 2.2
3 V 2.4
I
OH
= -24 mA 3 V 2
I
OL
= 100 µA 1.65 V to 3.6 V 0.2
I
OL
= 4 mA 1.65 V 0.45
I
OL
= 6 mA 2.3 V 0.4V
OL
V2.3 V 0.7I
OL
= 12 mA
2.7 V 0.4
I
OL
= 24 mA 3 V 0.55
I
I
V
I
= V
CC
or GND 3.6 V ±5µA
V
I
= 0.58 V 1.65 V 25
V
I
= 1.07 V 1.65 V -25
V
I
= 0.7 V 2.3 V 45
I
I(hold)
V
I
= 1.7 V 2.3 V -45 µA
V
I
= 0.8 V 3 V 75
V
I
= 2 V 3 V -75
V
I
= 0 to 3.6 V
(2)
3.6 V ±500
I
OZ
(3)
V
O
= V
CC
or GND 3.6 V ±10 µA
I
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 40 µA
∆I
CC
One input at V
CC
- 0.6 V, Other inputs at V
CC
or GND 3 V to 3.6 V 750 µA
C
i
Control inputs V
I
= V
CC
or GND 3.3 V 4 pF
C
io
A or B ports V
O
= V
CC
or GND 3.3 V 8 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state toanother.
(3) For I/O ports, the parameter I
OZ
includes the input leakage current.
4
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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74ALVCH1660118-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3 )
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 V±0.2 V ±0.3 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency
(1)
150 150 150 MHz
LE high
(1)
3.3 3.3 3.3t
w
Pulse duration nsCLK high or low
(1)
3.3 3.3 3.3
Data before CLK ↑
(1)
2.3 2.4 2.1
CLK high
(1)
2 1.6 1.6t
su
Setup time Data before LE ↓nsCLK low
(1)
1.3 1.2 1.1
CLKEN before CLK ↑
(1)
2 2 1.7
Data after CLK ↑
(1)
0.7 0.7 0.8
CLK high
(1)
1.3 1.6 1.4t
h
Hold time Data after LE ↓nsCLK low
(1)
1.7 2 1.7
CLKEN after CLK ↑
(1)
0.3 0.5 0.6
(1) This information was not available at the time of publication.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3 )
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN TYP MIN MAX MIN MAX MIN MAX
f
max
(1)
150 150 150 MHz
A or B B or A
(1)
1 4 4.6 4.1
t
pd
LEAB or LEBA
(1)
1 4.6 5.3 4.7 nsA or BCLKAB or CLKBA
(1)
1.2 5.2 5.8 5
t
en
OEAB or OEBA A or B
(1)
1.1 5.3 6.1 5.2 ns
t
dis
OEAB or OEBA A or B
(1)
1.4 4.9 4.8 4.4 ns
(1) This information was not available at the time of publication.
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
Outputs enabled
(1)
41 52C
pd
Power dissipation capacitance C
L
= 50 pF, f = 10 MHz pFOutputs disabled
(1)
6 6
(1) This information was not available at the time of publication.
5
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PARAMETER MEASUREMENT INFORMATION
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
V
CC
= 1.8 V
Figure 1. Load Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74ALVCH1660118-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
V
CC
= 2.5 V ±0.2 V
Figure 2. Load Circuit and Voltage Waveforms
7
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PARAMETER MEASUREMENT INFORMATION
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V
VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
0 V
1.5 V 2.7 V
0 V
1.5 V
0 V
2.7 V
0 V
1.5 V 1.5 V
tw
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
1.5 V
SN74ALVCH16601
18-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES027F – JULY 1995 – REVISED OCTOBER 2004
V
CC
= 2.7 V AND 3.3 V ±0.3 V
Figure 3. Load Circuit and Voltage Waveforms
8
I TEXAS INSTRUMENTS Sample: Sample: Sample:
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74ALVCH16601DGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16601
SN74ALVCH16601DL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16601
SN74ALVCH16601DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16601
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS ’ I+K0 '«PI» Reel Diame|er AD Dimension deSIgned Io accommodate me componem wIdIh E0 Dimension deSIgned Io eecommodaIe me componenI Iengm KO Dlmenslun desIgned to accommodate me componem Ihlckness 7 w OvereII wmm OHhe earner cape i p1 Pitch between successwe cavIIy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O SprockeIHoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALVCH16601DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74ALVCH16601DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
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*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVCH16601DGGR TSSOP DGG 56 2000 367.0 367.0 45.0
SN74ALVCH16601DLR SSOP DL 56 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
l TEXAS INSTRUMENTS T - Tube height| L - Tube length l ,g + w-Tuhe _______________ _ ______________ width 47 — B - Alignment groove width
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74ALVCH16601DL DL SSOP 56 20 473.7 14.24 5110 7.87
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
MECHANICAL DATA DL (RiPDsoicse) PLAST‘C SMALLiOUTLINE PACKAGE 56 29 ”‘33 (3333’ — 00025 (0.535) r 4‘47 0003 (0.203) 005 013 HHHHHHHHHH HHHHHHHH HHHHHHHH 0.4m 10,67) (””0 (“'25) O 0.395 10,03) 0.005(o.13) o m o m 17 m 8 g E \\ g i m HHHHHHHHHHHHHHHHHHHHHHHHHHHH 1 28 0.730 (13.54) 0.720 (10.29) WM _ Sealing PianeJl{/__L 0.110 (2,79) MAX 0008 (0 20) MIN jg _o.04 (o1)0 404004571/r 05/13 NOTES: . AH \inear dimensions are in inches (mili'imelers), , This drawing '15 subject to change without noiice. V FaHs wikhi'n JEDEC M0418 PaweIPAD is a trademaik 0! Texas insirumenis. A E C, Body dimensions do rim inciude maid flush or protrusion noi Io exceed 0,005 (0,15), D {I TEXAS INSTRUMENTS wwwxi. cam
DGGOOSBA .
www.ti.com
PACKAGE OUTLINE
C
TYP
8.3
7.9
1.2 MAX
54X 0.5
56X 0.27
0.17
2X
13.5
(0.15) TYP
0 - 8
0.15
0.05
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
14.1
13.9
B6.2
6.0
4222167/A 07/2015
TSSOP - 1.2 mm max heightDGG0056A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
156
0.08 C A B
29
28
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
DGGOOSSA “““““““““““““““““ E M NEWEEEEEEEEEEEWE EEEEE EEEEE EEEF JQL E
www.ti.com
EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
56X (1.5)
56X (0.3)
54X (0.5)
(R )
TYP
0.05
4222167/A 07/2015
TSSOP - 1.2 mm max heightDGG0056A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
28 29
56
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
DGGOOSBA WEE EEE LEmEHEEEEEEEEEEEL
www.ti.com
EXAMPLE STENCIL DESIGN
(7.5)
54X (0.5)
56X (0.3)
56X (1.5)
(R ) TYP0.05
4222167/A 07/2015
TSSOP - 1.2 mm max heightDGG0056A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
28 29
56
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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