The major applications, critical specifications, and supported packages for the FL256L are shown here. The block diagram above shows this part in the Quad mode. This part also offers a dedicated reset pin. In the Bi 1 and Bi 2 interface, the write, protect, and hold signals replace the IO 2 and IO 3 signals. Additional information about the write, protect, and hold signals can be obtained from the datasheet. For those applications that need a very high read bandwidth, Cypress’ FL256S will be ideal for applications which operate up to 133Mhz SDR or 66Mhz DDR. For applications which require >66Mhz DDR speed, Cypress’ FL256S will be the part to choose.