The Cyclone® III family has introduced a number of new milestones to the low cost FPGA industry. It is the first available low cost 65nm FPGA in the industry which offers more than 100k logic elements. Using TSMC’s 65nm LP process means that for the first time ever, an FPGA fabric was placed on a cell phone process. The power benefits of this engineering strategy are substantial, with up to 50% lower power than the previous architecture, and up to 75% lower power than competing low cost FPGAs. The largest Cyclone® III device, the EP3C120, has a typical static power consumption at 85°C of 170mW. Typical 90nm competing devices have static power consumptions of 480mW. However, two are needed to implement the same functionality, so the total power of an equivalent solution is 960mW. Ignoring the board space and performance advantages of a single chip solution, this power comparison shows that the Cyclone® III device at high densities has more than a 5x advantage over the competing low cost FPGA architectures.