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I TEXAS INSTRUMENTS

Input Stage Offset Voltage Drift (PV/qC)

Amplifiers (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

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Protection

REF

+VS

OUT

-VS

-IN

+IN

 

O IN IN REF

V G V V V

 

 

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49.4 k

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

INA821

SBOS893D –AUGUST 2018–REVISED JUNE 2020

INA821 35-µV Offset, 7-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier

1 Features

1• Low offset voltage: 10 µV (typ), 35 µV (max)

• Gain drift: 5 ppm/°C (G = 1),

35 ppm/°C (G > 1) (max)

• Noise: 7 nV/√Hz

• Bandwidth: 4.7 MHz (G = 1), 290 kHz (G = 100)

• Stable with 1-nF capacitive loads

• Inputs protected up to ±40 V

• Common-mode rejection: 112 dB, G = 10 (min)

• Power supply rejection: 110 dB, G = 1 (min)

• Supply current: 650 µA (max)

• Supply range:

– Single-supply: 4.5 V to 36 V

– Dual-supply: ±2.25 V to ±18 V

• Specified temperature range: –40°C to +125°C

• Packages: 8-pin SOIC, VSSOP, and WSON

2 Applications

•Analog input module

•Flow transmitter

•Battery test

•LCD test

•Electrocardiogram (ECG)

•Surgical equipment

•Process analytics (pH, gas, concentration, force

and humidity)

3 Description

The INA821 is a high-precision instrumentation

amplifier that offers low power consumption and

operates over a wide single-supply or dual-supply

range. A single external resistor sets any gain from 1

to 10,000. The device has high precision as a result

of super-beta input transistors, which provide low

input offset voltage, offset voltage drift, input bias

current, and input voltage and current noise.

Additional circuitry protects the inputs against

overvoltage up to ±40 V.

The INA821 is optimized to provide a high common-

mode rejection ratio. At G = 1, the common-mode

rejection ratio exceeds 92 dB across the full input

common-mode range. The device is designed for low-

voltage operation from a 4.5-V single supply, and

dual supplies up to ±18 V.

The INA821 is available in 8-pin SOIC, VSSOP, and

WSON packages, and is specified over the –40°C to

+125°C temperature range.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

INA821

SOIC (8) 4.90 mm × 3.91 mm

VSSOP (8) 3.00 mm × 3.00 mm

WSON (8) 3.00 mm x 3.00 mm

(1) For all available packages, see the package option addendum

at the end of the data sheet.

INA821 Simplified Internal Schematic Typical Distribution of Input Stage Offset Voltage

Drift

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics: Table of Graphs.................. 8

7.7 Typical Characteristics............................................ 10

8 Detailed Description............................................ 19

8.1 Overview ................................................................. 19

8.2 Functional Block Diagram....................................... 19

8.3 Feature Description................................................. 20

8.4 Device Functional Modes........................................ 26

9 Application and Implementation ........................ 26

9.1 Application Information............................................ 26

9.2 Typical Application .................................................. 29

9.3 Other Application Examples.................................... 31

10 Power Supply Recommendations ..................... 32

11 Layout................................................................... 32

11.1 Layout Guidelines ................................................. 32

11.2 Layout Example .................................................... 33

12 Device and Documentation Support ................. 34

12.1 Device Support .................................................... 34

12.2 Documentation Support ........................................ 34

12.3 Receiving Notification of Documentation Updates 34

12.4 Support Resources ............................................... 34

12.5 Trademarks........................................................... 34

12.6 Electrostatic Discharge Caution............................ 34

12.7 Glossary................................................................ 34

13 Mechanical, Packaging, and Orderable

Information ........................................................... 34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (July 2019) to Revision D Page

• Added DRG (WSON) package and associated content to data sheet .................................................................................. 1

Changes from Revision B (May 2019) to Revision C Page

• Changed DGK (VSSOP) package from advanced information (preview) to production data (active) ................................... 1

• Changed Figure 9, Typical Distribution of Input Offset Current, to show correct image...................................................... 11

• Changed Figure 27, Typical Distribution of Gain Error, G = 1, to show improved data....................................................... 14

Changes from Revision A (December 2018) to Revision B Page

• Added 8-pin DGK (VSSOP) advanced information package and associated content to data sheet..................................... 1

• Changed Applications bullets ................................................................................................................................................. 1

Changes from Original (August 2018) to Revision A Page

• First release of production-data data sheet ........................................................................................................................... 1

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5 Device Comparison Table

DEVICE DESCRIPTION GAIN EQUATION RG PINS AT PIN

INA821 35-µV Offset, 0.4 µV/°C VOS Drift, 7-nV/√Hz Noise, High-

Bandwidth, Precision Instrumentation Amplifier G = 1 + 49.4 kΩ/ RG 2, 3

INA819 35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,

Precision Instrumentation Amplifier G = 1 + 50 kΩ/ RG 2, 3

INA818 35-µV Offset, 0.4 µV/°C VOS Drift, 8-nV/√Hz Noise, Low-Power,

Precision Instrumentation Amplifier G = 1 + 50 kΩ/ RG 1, 8

INA828 50-µV Offset, 0.5 µV/°C VOS Drift, 7-nV/√Hz Noise, Low-Power,

Precision Instrumentation Amplifier G = 1 + 50 kΩ/ RG 1, 8

INA333 25-µV VOS, 0.1 µV/°C VOS Drift, 1.8-V to 5-V, RRO, 50-µA IQ,

Chopper-Stabilized INA G = 1 + 100 kΩ/ RG 1, 8

PGA280 20-mV to ±10-V Programmable Gain IA With 3-V or 5-V

Differential Output; Analog Supply up to ±18 V Digital programmable N/A

INA159 G = 0.2 V Differential Amplifier for ±10-V to 3-V and 5-V

Conversion G = 0.2 V/V N/A

PGA112 Precision Programmable Gain Op Amp With SPI Digital programmable N/A

*9 TEXAS INSTRUMENTS

1±IN 8 +VS

2RG 7 OUT

3RG 6 REF

4+IN 5 ±VS

Not to scale

Thermal

Pad

1±IN 8 +VS

2RG 7 OUT

3RG 6 REF

4+IN 5 ±VS

Not to scale

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6 Pin Configuration and Functions

D and DGK Packages

8-Pin SOIC and 8-Pin VSSOP

Top View

DRG Package

8-Pin WSON

Top View

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

–IN 1 I Negative (inverting) input

+IN 4 O Positive (noninverting) input

OUT 7 — Output

RG 2, 3 I Gain setting pin. Place a gain resistor between pin 2 and pin 3.

REF 6 — Reference input. This pin must be driven by a low impedance source.

–VS 5 — Negative supply

+VS 8 — Positive supply

Thermal pad — — Thermal pad internally connected to –VS. Connect externally to –VS or leave floating.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Short-circuit to VS/ 2.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Supply voltage –20 20 V

Signal input pins Voltage –40 40 V

REF pin –20 20

Signal output pins (–Vs) – 0.5 (+Vs) + 0.5 V

Output short-circuit(2) Continuous

Operating Temperature, TA–50 150

°CJunction Temperature, TJ175

Storage Temperature, Tstg –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage, VS

Single-supply 4.5 36 V

Dual-supply ±2.25 ±18

Specified temperature, TASpecified temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1)

INA821

UNITD (SOIC) DGK (VSSOP) DRG (WSON)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 119.6 215.4 55.6 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 66.3 66.3 57.9 °C/W

RθJB Junction-to-board thermal resistance 61.9 97.8 28.6 °C/W

ψJT Junction-to-top characterization parameter 20.5 10.5 1.8 °C/W

ψJB Junction-to-board characterization parameter 61.4 96.1 28.6 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 12.1 °C/W

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(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).

(2) Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) =√[ΔVOSI2+ (ΔVOSO / G)2].

(3) Specified by characterization.

(4) Input voltage range of the Instrumentation Amplifier input stage. The input range depends on the common-mode voltage, differential

voltage, gain, and reference voltage. See Typical Characteristic curves Figure 51 through Figure 54 for more information.

(5) Total RTI voltage noise is equal to: eN(RTI) =√[eNI2+ (eNO / G)2].

7.5 Electrical Characteristics

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT

VOSI Input stage offset

voltage(1)(2)

INA821ID,

INA821DRG 10 35

µV

INA821IDGK 10 40

TA= –40°C to +125°C(3) INA821ID,

INA821DRG 75

INA821IDGK 80

vs temperature, TA= –40°C to +125°C 0.1 0.4 µV/°C

VOSO Output stage offset

voltage(1)(2)

INA821ID,

INA821DGK 50 350

µV

INA821DRG 50 400

TA= –40°C to +125°C(3) 850

vs temperature, TA= –40°C to +125°C 5 µV/°C

PSRR Power-supply rejection

ratio

G = 1, RTI 110 120

G = 10, RTI 114 130

G = 100, RTI 130 135

G = 1000, RTI 136 140

zid Differential impedance 100 || 1 GΩ|| pF

zic Common-mode

impedance 100 || 7 GΩ|| pF

RFI filter, –3-dB

frequency 45 MHz

VCM Operating input range(4) (V–) + 2 (V+) – 2 V

VS= ±2.25 V to ±18 V, TA= –40°C to +125°C See Figure 51 to Figure 54

Input overvoltage range TA= –40°C to +125°C(3) ±40 V

CMRR Common-mode rejection

ratio

At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,

G = 1 92 105

At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,

G = 10 112 125

At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,

G = 100 132 145

At DC to 60 Hz, RTI, VCM = (V–) + 2 V to (V+) – 2 V,

G = 1000 140 150

BIAS CURRENT

IBInput bias current VCM = VS/ 2 0.15 0.5 nA

TA= –40°C to +125°C 2

IOS Input offset current VCM = VS/ 2 0.15 0.5 nA

TA= –40°C to +125°C 2

NOISE VOLTAGE

eNI Input stage voltage

noise(5) f = 1 kHz, G = 100, RS= 0 Ω7 nV/√Hz

fB= 0.1 Hz to 10 Hz, G = 100, RS= 0 Ω0.14 µVPP

eNO Output stage voltage

noise(5) f = 1 kHz, RS= 0 Ω65 nV/√Hz

fB= 0.1 Hz to 10 Hz, RS= 0 Ω2.5 µVPP

InNoise current f = 1 kHz 130 fA/√Hz

fB= 0.1 Hz to 10 Hz, G = 100 4.7 pAPP

GAIN

G Gain equation 1 + (49.4 kΩ/ RG) V/V

Range of gain 1 10000 V/V

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Electrical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(6) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.

GE Gain error

G = 1, VO= ±10 V ±0.005% ±0.025%

G = 10, VO= ±10 V ±0.025% ±0.15%

G = 100, VO= ±10 V ±0.025% ±0.15%

G = 1000, VO= ±10 V ±0.05%

Gain vs temperature(6) G = 1, TA= –40°C to +125°C ±5 ppm/°C

G > 1, TA= –40°C to +125°C ±35

Gain nonlinearity

G = 1 to 10, VO= –10 V to 10 V, RL= 10 kΩ1 10

ppm

G = 100, VO= –10 V to 10 V, RL= 10 kΩ15

G = 1000, VO= –10 V to 10 V, RL= 10 kΩ10

G = 1 to 100, VO= –10 V to 10 V, RL= 2 kΩ30

OUTPUT

Voltage swing (V–) +

0.15 (V+) – 0.15 V

Load capacitance

stability 1000 pF

ZOClosed-loop output

impedance f = 10 kHz 1.3 Ω

ISC Short-circuit current Continuous to VS/ 2 ±20 mA

FREQUENCY RESPONSE

BW Bandwidth, –3 dB

G = 1 4.7 MHz

G = 10 970

kHzG = 100 290

G = 1000 30

SR Slew rate G = 1, VO= ±10 V 2.0 V/µs

tSSettling time

0.01%, G = 1 to 100, VSTEP = 10 V 6

µs

0.01%, G = 1000, VSTEP = 10 V 40

0.001%, G = 1 to 100, VSTEP = 10 V 10

0.001%, G = 1000, VSTEP = 10 V 50

REFERENCE INPUT

RIN Input impedance 10 kΩ

Voltage range (V–) (V+) V

Gain to output 1 V/V

Reference gain error 0.01%

POWER SUPPLY

VSPower-supply voltage Single-supply 4.5 36 V

Dual-supply ±2.25 ±18

IQQuiescent current VIN = 0 V 600 650 µA

vs temperature, TA= –40°C to +125°C 870

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7.6 Typical Characteristics: Table of Graphs

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

Table 1. Table of Graphs

DESCRIPTION FIGURE

Typical Distribution of Input Stage Offset Voltage Figure 1

Typical Distribution of Input Stage Offset Voltage Drift Figure 2

Typical Distribution of Output Stage Offset Voltage Figure 3

Typical Distribution of Output Stage Offset Voltage Drift Figure 4

Input Stage Offset Voltage vs Temperature Figure 5

Output Stage Offset Voltage vs Temperature Figure 6

Typical Distribution of Input Bias Current, TA= 25°C Figure 7

Typical Distribution of Input Bias Current, TA= 90°C Figure 8

Typical Distribution of Input Offset Current Figure 9

Input Bias Current vs Temperature Figure 10

Input Offset Current vs Temperature Figure 11

Typical CMRR Distribution, G = 1 Figure 12

Typical CMRR Distribution, G = 10 Figure 13

CMRR vs Temperature, G = 1 Figure 14

CMRR vs Temperature, G = 10 Figure 15

Input Current vs Input Overvoltage Figure 16

CMRR vs Frequency (RTI) Figure 17

CMRR vs Frequency (RTI, 1-kΩsource imbalance) Figure 18

Positive PSRR vs Frequency (RTI) Figure 19

Negative PSRR vs Frequency (RTI) Figure 20

Gain vs Frequency Figure 21

Voltage Noise Spectral Density vs Frequency (RTI) Figure 22

Current Noise Spectral Density vs Frequency (RTI) Figure 23

0.1-Hz to 10-Hz RTI Voltage Noise, G = 1 Figure 24

0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000 Figure 25

0.1-Hz to 10-Hz RTI Current Noise Figure 26

Typical Distribution of Gain Error, G = 1 Figure 27

Typical Distribution of Gain Error, G = 10 Figure 28

Input Bias Current vs Common-Mode Voltage Figure 29

Gain Error vs Temperature, G = 1 Figure 30

Gain Error vs Temperature, G = 10 Figure 31

Supply Current vs Temperature Figure 32

Gain Nonlinearity, G = 1 Figure 33

Gain Nonlinearity, G = 10 Figure 34

Offset Voltage vs Negative Common-Mode Voltage Figure 35

Offset Voltage vs Positive Common-Mode Voltage Figure 36

Positive Output Voltage Swing vs Output Current Figure 37

Negative Output Voltage Swing vs Output Current Figure 38

Short-Circuit Current vs Temperature Figure 39

Large-Signal Frequency Response Figure 40

THD+N vs Frequency Figure 41

Overshoot vs Capacitive Loads Figure 42

Small-Signal Response, G = 1 Figure 43

Small-Signal Response, G = 10 Figure 44

Small-Signal Response, G = 100 Figure 45

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Typical Characteristics: Table of Graphs (continued)

Table 1. Table of Graphs (continued)

DESCRIPTION FIGURE

Small-Signal Response, G = 1000 Figure 46

Large-Signal Step Response Figure 47

Closed-Loop Output Impedance Figure 48

Differential-Mode EMI Rejection Ratio Figure 49

Common-Mode EMI Rejection Ratio Figure 50

Input Common-Mode Voltage vs Output Voltage, G = 1, VS= 5 V Figure 51

Input Common-Mode Voltage vs Output Voltage, G = 100, VS= 5 V Figure 52

Input Common-Mode Voltage vs Output Voltage, VS= ±5 V Figure 53

Input Common-Mode Voltage vs Output Voltage, VS= ±15 V Figure 54

A HM

Temperature (qC)

Input-Referred Offset Voltage (PV)

-50 -25 0 25 50 75 100 125 150

-100

-75

-50

-25

100

D005

Mean

+3V

-3V

Temperature (qC)

Input-Referred Offset Voltage (PV)

-50 -25 0 25 50 75 100 125 150

-500

-400

-300

-200

-100

100

200

300

400

500

D006

Mean

+3V

-3V

Input Stage Offset Voltage (PV)

Amplifiers (%)

-200 -100 0 100 200

D003

Output Offset Voltage Drift (PV/qC)

Amplifiers (%)

-5 -4 -3 -2 -1 0 1 2 3 4 5

D004

Input Stage Offset Voltage (PV)

Amplifiers (%)

-30 30-25 -20 -15 -10 -5 0 5 10 15 20 25

D001

Input Stage Offset Voltage Drift (PV/qC)

Amplifiers (%)

-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4

D002

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7.7 Typical Characteristics

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

N = 2667 Mean = 3.1 µV Std. Dev. = 8.1 µV

Figure 1. Typical Distribution of

Input Stage Offset Voltage

N = 81 Mean = -0.03 µV/°C Std. Dev. = 0.09 µV/°C

Figure 2. Typical Distribution of

Input Stage Offset Voltage Drift

N = 2667 Mean = 7.7 µV Std. Dev. = 50.7 µV

Figure 3. Typical Distribution of

Output Stage Offset Voltage

N = 81 Mean = –1.09 µV/°C Std. Dev. = 0.94 µV/°C

Figure 4. Typical Distribution of

Output Stage Offset Voltage Drift

81 units

Figure 5. Input Stage Offset Voltage vs Temperature

81 units

Figure 6. Output Stage Offset Voltage vs Temperature

*9 TEXAS INSTRUMENTS

Temperature (qC)

Input Offset Current (nA)

-50 -30 -10 10 30 50 70 90 110 130 150

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

D010

Avg

3V

3V

Common-Mode Rejection Ratio (PV/V)

Amplifiers (%)

-20 -16 -12 -8 -4 0 4 8 12 16 20

D011

Input Offset Current (pA)

Amplifiers (%)

-300 -200 -100 0 100 200 300

D050

Temperature (qC)

Input Bias Current (nA)

-50 -30 -10 10 30 50 70 90 110 130 150

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

D009

Avg

3V

3V

Input Bias Current (pA)

Amplifiers (%)

-300 -200 -100 0 100 200 300

D007

Input Bias Current (pA)

Amplifiers (%)

-200 -150 -100 -50 0 50 100 150 200

D008

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

N = 292 Mean = 45 pA Std. Dev. = 62 pA

TA= 25°C

Figure 7. Typical Distribution of Input Bias Current,

TA= 25°C

N = 292 Mean = 34 pA Std. Dev. = 52 pA

TA= 90°C

Figure 8. Typical Distribution of Input Bias Current,

TA= 90°C

N = 94 Mean = –38.82 pA Std. Dev. = 47.24 pA

Figure 9. Typical Distribution of Input Offset Current

N = 294 G = 1

Figure 10. Input Bias Current vs Temperature

N = 294 G = 1

Figure 11. Input Offset Current vs Temperature

N = 294 Mean = 4.87 µV/V Std. Dev. = 4.14 µV/V

G = 1

Figure 12. Typical CMRR Distribution, G = 1

l TEXAS INSTRUMENTS an 150 31 \ 175 \ (\l ) \ YH Ompm vmxage (v) 150 140

Frequency (Hz)

Common-Mode Rejection Ratio (dB)

100

120

140

160

10 100 1k 10k 100k 1M 10M

D016D016D016

G = 1

G = 10

G = 100

G = 1000

Frequency (Hz)

Common-Mode Rejection Ratio (dB)

100

120

140

10 100 1k 10k 100k 1M

D017

G = 1

G = 10

G = 100

G = 1000

Temperature (qC)

Common-Mode Rejection Ratio (dB)

-50 -25 0 25 50 75 100 125 150

100

125

150

175

D014

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

Input Voltage (V)

Input Current (mA)

Output Voltage (V)

-50 -40 -30 -20 -10 0 10 20 30 40 50

-10 -20

-8 -16

-6 -12

-4 -8

-2 -4

0 0

2 4

4 8

6 12

8 16

10 20

D015

Input Current

Output Voltage

Common-Mode Rejection Ratio (PV/V)

Amplifiers (%)

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

D012

Temperature (qC)

Common-Mode Rejection Ratio (dB)

-50 -25 0 25 50 75 100 125 150

100

125

150

D013

Unit 1

Unit 2

Unit 3

Unit 4

Unit 5

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

N = 294 Mean = 0.51 µV/V Std. Dev. = 0.42 µV/V

G = 10

Figure 13. Typical CMRR Distribution, G = 10

N = 5 G = 1

Figure 14. CMRR vs Temperature, G = 1

N = 5 G = 10

Figure 15. CMRR vs Temperature, G = 10

VS= ±18 V

Figure 16. Input Current vs Input Overvoltage

Figure 17. CMRR vs Frequency (RTI) Figure 18. CMRR vs Frequency

(RTI, 1-kΩsource imbalance)

l TEXAS INSTRUMENTS ‘50 ‘50 an mun

Frequency (Hz)

Current Noise Spectral

Density (fA/—Hz)

100m 1 10 100 1k 10k

100

D022

Time (1 s/div)

Noise (0.5 PV/div)

D023

Frequency (Hz)

Gain (dB)

-60

-40

-20

10 100 1k 10k 100k 1M 10M

D020

G = 1

G = 10

G = 100

G = 1000

Frequency (Hz)

Voltage Noise

Spectral Density (nV/—Hz)

100m 1 10 100 1k 10k 100k

100

1000

D021D021

G = 1

G = 10

G = 100

G = 1000

Frequency (Hz)

Positive Power Supply

Rejection Ratio (dB)

-40

-20

100

120

140

160

1 10 100 1k 10k 100k

D018

G = 1

G = 10

G = 100

G = 1000

Frequency (Hz)

Negative Power Supply

Rejection Ratio (dB)

-40

-20

100

120

140

160

1 10 100 1k 10k 100k

D019D019

G = 1

G = 10

G = 100

G = 1000

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

Figure 19. Positive PSRR vs Frequency (RTI) Figure 20. Negative PSRR vs Frequency (RTI)

Figure 21. Gain vs Frequency Figure 22. Voltage Noise Spectral Density vs Frequency

(RTI)

Figure 23. Current Noise Spectral Density vs Frequency

(RTI)

G = 1

Figure 24. 0.1-Hz to 10-Hz RTI Voltage Noise, G = 1

l TEXAS INSTRUMENTS mu

Common-Mode Voltage (V)

Input Bias Current (nA)

-15 -12 -9 -6 -3 0 3 6 9 12 15

-0.5

-0.3

-0.1

0.1

0.3

0.5

D028

45qC

25qC

125qC

Temperature (qC)

Gain Error (ppm)

-50 -30 -10 10 30 50 70 90 110 130 150

-40

-20

100

D029

Gain Error (ppm)

Amplifiers (%)

-250 -200 -150 -100 -50 0 50 100 150 200 250

D026

Input Stage Offset Voltage (PV)

Amplifiers (%)

-900 -600 -300 0 300 600 900

D027D027

Time (1 s/div)

Noise (20 nV/div)

D024

Time (1 s/div)

Noise (0.5 pA/div)

D025

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

G = 1000

Figure 25. 0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000

G = 1

Figure 26. 0.1-Hz to 10-Hz RTI Current Noise

N = 5412 Mean = 30 ppm Std. Dev. = 55 ppm

G = 1

Figure 27. Typical Distribution of Gain Error, G = 1

N = 293 Mean = 152 ppm Std. Dev. = 291 ppm

G = 10

Figure 28. Typical Distribution of Gain Error, G = 10

VS= ±15 V

Figure 29. Input Bias Current vs Common-Mode Voltage

Average of 294 units G = 1

Figure 30. Gain Error vs Temperature, G = 1

l TEXAS INSTRUMENTS ‘snu 175 150

Input Common-Mode Voltage (V)

Offset Voltage (PV)

-75

-50

-25

100

125

150

175

-15 -14.6 -14.2 -13.8 -13.4 -13 -12.6 -12.2

D034D034D034

40qC

25qC

85qC

125qC

Input Common-Mode Voltage (V)

Offset Voltage (PV)

-50

-25

100

125

150

12 12.4 12.8 13.2 13.6 14 14.4 14.8

D035D035

40qC

25qC

85qC

125qC

Output Voltage (V)

Nonlinearity (ppm)

-10 -8 -6 -4 -2 0 2 4 6 8 10

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

D032D032D032

Output Voltage (V)

Nonlinearity (ppm)

-10 -8 -6 -4 -2 0 2 4 6 8 10

-16

-14

-12

-10

-8

-6

-4

-2

D033

Temperature (qC)

Gain Error (ppm)

-50 -25 0 25 50 75 100 125 150

-1500

-1250

-1000

-750

-500

-250

250

500

750

1000

1250

1500

D030

Temperature (qC)

IQ (mA)

-50 -30 -10 10 30 50 70 90 110 130 150

0.3

0.36

0.42

0.48

0.54

0.6

0.66

0.72

0.78

0.84

0.9

D031

VS = r 15 V

VS = r 2.25 V

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

Average of 294 units G = 10

Figure 31. Gain Error vs Temperature, G = 10 Figure 32. Supply Current vs Temperature

G = 1

Figure 33. Gain Nonlinearity, G = 1

G = 10

Figure 34. Gain Nonlinearity, G = 10

Figure 35. Offset Voltage vs Negative Common-Mode

Voltage Figure 36. Offset Voltage vs Positive Common-Mode

Voltage

‘5‘ TEXAS INSTRUMENTS as as: . sigma 25%: E:

Frequency (Hz)

Total Harmonic Distortion + Noise (%)

-40

10 100 1k 10k 100k

0.001

0.01

0.1

-60

-80

-100

Total Harmonic Distortion + Noise (dB)

D040

G = 1

G = 10

G = 100

Capacitive Load (pF)

Overshoot (%)

1 10 100 1000

D041D041

Positive Overshoot

Negative Overshoot

Temperature (qC)

Short-Circuit Current (mA)

-50 -30 -10 10 30 50 70 90 110 130 150

-60

-50

-40

-30

-20

-10

D038

ISC, Source

ISC, Sink

Frequency (Hz)

Output Amplitude (Vp)

100 1k 10k 100k 1M 10M

D039

Vs = r15 V

Vs = r5 V

Output Current (mA)

Output Voltage (V)

0 2 4 6 8 10 12 14 16

14.1

14.2

14.3

14.4

14.5

14.6

14.7

14.8

14.9

D036

±qC

25qC

85qC

125qC

Output Current (mA)

Output Voltage (V)

0 2 4 6 8 10 12 14 16

-15

-14.9

-14.8

-14.7

-14.6

-14.5

-14.4

-14.3

-14.2

-14.1

-14

D037

±qC

25qC

85qC

125qC

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

Figure 37. Positive Output Voltage Swing vs Output Current Figure 38. Negative Output Voltage Swing vs Output Current

Figure 39. Short-Circuit Current vs Temperature Figure 40. Large-Signal Frequency Response

500-kHz measurement bandwidth

1-VRMS output voltage 100-kΩload

Figure 41. THD+N vs Frequency Figure 42. Overshoot vs Capacitive Loads

‘5‘ TEXAS INSTRUMENTS

Time (10 µs/div)

Amplitude (2 V/div)

D046D046

Output

Input

Frequency (Hz)

Output Impedence (:)

1 10 100 1k 10k 100k 1M 10M

0.1

100

D047D047

Time (µs)

Output Amplitude (mV)

-5 -2.5 0 2.5 5 7.5 10 12.5 15

-75

-50

-25

D044D044D044

Time (µs)

Output Amplitude (mV)

-25 0 25 50 75

-75

-50

-25

D045

Time (µs)

Output Amplitude (mV)

-5 -2.5 0 2.5 5 7.5 10 12.5 15

-75

-50

-25

D042

Time (µs)

Output Amplitude (mV)

-5 -2.5 0 2.5 5 7.5 10 12.5 15

-75

-50

-25

D043

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

G = 1 RL= 10 kΩCL= 100 pF

Figure 43. Small-Signal Response

G = 10 RL= 10 kΩCL= 100 pF

Figure 44. Small-Signal Response

G = 100 RL= 10 kΩCL= 100 pF

Figure 45. Small-Signal Response

G = 1000 RL= 10 kΩCL= 100 pF

Figure 46. Small-Signal Response

Figure 47. Large-Signal Step Response Figure 48. Closed-Loop Output Impedance

l TEXAS INSTRUMENTS 120 140

-20

-15

-10

-5

±20 ±10 0 10 20

Common-Mode Voltage (V)

Output Voltage (V)

G = 1

G = 100

C006

-5

-4

-3

-2

-1

±6 ±4 ±2 0 2 4 6

Common-Mode Voltage (V)

Output Voltage (V)

G = 1

G = 100

C006

0 1 2 3 4 5 6

Common-Mode Voltage (V)

Output Voltage (V)

VREF = 0 V

VREF = 2.5 V

C006

0 1 2 3 4 5 6

Common-Mode Voltage (V)

Output Voltage (V)

VREF = 0 V

VREF = 2.5 V

C006

Frequency (Hz)

EMIRR (dB)

100

120

10M 100M 1G 10G

D048

Frequency (Hz)

EMIRR (dB)

100

120

140

10M 100M 1G 10G

D049

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Typical Characteristics (continued)

at TA= 25°C, VS= ±15 V, RL= 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)

Figure 49. Differential-Mode EMI Rejection Ratio Figure 50. Common-Mode EMI Rejection Ratio

VS= 5 V G = 1

Figure 51. Input Common-Mode Voltage vs Output Voltage

VS= 5 V G = 100

Figure 52. Input Common-Mode Voltage vs Output Voltage

VS= ±5 V VREF = 0 V

Figure 53. Input Common-Mode Voltage vs Output Voltage

VS= ±15 V VREF = 0 V

Figure 54. Input Common-Mode Voltage vs Output Voltage

25 k

RBVB

+VS

-VS

+VS

-VS

+VS

-VS

+VS

-VS

+VS

-VS

Super-

NPN

Super-

NPN

(External)

+VS

-VS

Overvoltage

Protection

Overvoltage

Protection

-IN +IN

REF

OUT

Q1Q2

A1A2A3

+VS

IB Cancellation IB Cancellation

25 k

40 k

RG RG

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8 Detailed Description

8.1 Overview

The INA821 is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage

and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how

the differential input voltage is buffered by Q1and Q2and is forced across RG, which causes a signal current to

flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the

input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1and R2produces

output voltages on A1and A2that are approximately 0.8 V lower than the input voltages.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal

signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these

transistors limit input current to approximately 8 mA.

8.2 Functional Block Diagram

‘5‘ TEXAS INSTRUMENTS 49.4 k



49.4 k

G 1

10 k

24.7 k

10 k

10 k10 k

24.7 k

Overvoltage

Protection

Overvoltage

Protection

REF

+VS

V-

OUT

V+

-VS

-IN

+IN



49.4 k

G 1 R

 

O IN IN REF

V G V V V

 

 

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8.3 Feature Description

8.3.1 Setting the Gain

Figure 55 shows that the gain of the INA821 is set by a single external resistor (RG) connected between the RG

pins (pins 1 and 8).

Figure 55. Simplified Diagram of the INA821 With Gain and Output Equations

The value of RGis selected according to:

(1)

Table 2 lists several commonly used gains and resistor values. The 49.4-kΩterm in Equation 1 is a result of the

sum of the two internal 24.7-kΩfeedback resistors. These on-chip resistors are laser-trimmed to accurate

absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy

and drift specifications of the INA821. As shown in Figure 55 and explained in more details in the Layout section,

make sure to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, that are

placed as close to the device as possible.

Table 2. Commonly-Used Gains and Resistor Values

DESIRED GAIN RG(Ω) NEAREST 1% RG(Ω)

1 NC NC

2 49.4 k 49.9 k

5 12.35 k 12.4 k

10 5.489 k 5.49 k

20 2.600 k 2.61 k

50 1.008 k 1 k

100 499 499

200 248 249

500 99 100

1000 49.4 49.9

l TEXAS INSTRUMENTS AVO mu 120

Frequency (Hz)

EMIRR (dB)

100

120

140

10M 100M 1G 10G

D049

Frequency (Hz)

EMIRR (dB)

100

120

10M 100M 1G 10G

D048

EMIRR (dB)

RF _ PEAK 20

V 10

100 mV

§ ·

¨ ¸

§ ·

¨ ¸

' ˜

¨ ¸

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8.3.1.1 Gain Drift

The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The contribution of

RGto gain accuracy and drift is determined from Equation 1.

The best gain drift of 5 ppm/℃(maximum) is achieved when the INA821 uses G = 1 without RGconnected. In

this case, gain drift is limited by the slight mismatch of the temperature coefficient of the integrated 10-kΩ

resistors in the differential amplifier (A3). At gains greater than 1, gain drift increases as a result of the individual

drift of the 24.7-kΩresistors in the feedback of A1and A2relative to the drift of the external gain resistor (RG.)

The low temperature coefficient of the internal feedback resistors significantly improves the overall temperature

stability of applications using gains greater than 1 V/V over alternate options.

Low resistor values required for high gain make wiring resistance an important consideration. Sockets add to the

wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of

approximately 100 or greater. To maintain stability, avoid parasitic capacitance of more than a few picofarads at

RGconnections. Careful matching of any parasitics on the RGpins maintains optimal CMRR over frequency; see

Figure 17.

8.3.2 EMI Rejection

Texas Instruments developed a method to accurately measure the immunity of an amplifier over a broad

frequency spectrum extending from 10 MHz to 6 GHz. This method uses an EMI rejection ratio (EMIRR) to

quantify the ability of the INA821 to reject EMI. The offset resulting from an input EMI signal is calculated using

Equation 2:

where

• VRF_PEAK is the peak amplitude of the input EMI signal. (2)

Figure 56 and Figure 57 show the INA821 EMIRR graph for differential and common-mode EMI rejection across

this frequency range. Table 3 lists the EMIRR values for the INA821 at frequencies commonly encountered in

real-world applications. Applications listed in Table 3 are centered on or operated near the particular frequency

shown. Depending on the end-system requirements, additional EMI filters may be required near the signal inputs

of the system. Incorporating known good practices, such as using short traces, low-pass filters, and damping

resistors combined with parallel and shielded signal routing, may be required.

Figure 56. Common-Mode EMIRR Testing Figure 57. Differential-Mode EMIRR Testing

l TEXAS INSTRUMENTS

-20

-15

-10

-5

±20 ±10 0 10 20

Common-Mode Voltage (V)

Output Voltage (V)

G = 1

G = 100

C006

-5

-4

-3

-2

-1

±6 ±4 ±2 0 2 4 6

Common-Mode Voltage (V)

Output Voltage (V)

G = 1

G = 100

C006

0 1 2 3 4 5 6

Common-Mode Voltage (V)

Output Voltage (V)

VREF = 0 V

VREF = 2.5 V

C006

0 1 2 3 4 5 6

Common-Mode Voltage (V)

Output Voltage (V)

VREF = 0 V

VREF = 2.5 V

C006

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Table 3. INA821 EMIRR for Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION DIFFERENTIAL

EMIRR COMMON-MODE

EMIRR

400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultrahigh-frequency (UHF)

applications 60 dB 88 dB

900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (up to 1.6 GHz), GSM, aeronautical mobile, UHF applications 58 dB 60 dB

1.8 GHz GSM applications, mobile personal communications, broadband, satellite,

L-band (1 GHz to 2 GHz) 66 dB 89 dB

2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific

and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 73 dB 98 dB

3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 99 dB 111 dB

5 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and

satellite operation, C-band (4 GHz to 8 GHz) 83 dB 91 dB

8.3.3 Input Common-Mode Range

The linear input voltage range of the INA821 input circuitry extends within 2 V of power supplies and maintains

excellent common-mode rejection throughout this range. The common-mode range for the most common

operating conditions are shown in Figure 58 to Figure 61. The common-mode range for other operating

conditions is best calculated using the Common-Mode Input Range Calculator for Instrumentation Amplifiers.

VS= 5 V G = 1

Figure 58. Input Common-Mode Voltage vs Output Voltage

VS= 5 V G = 100

Figure 59. Input Common-Mode Voltage vs Output Voltage

VS= ±5 V VREF = 0 V

Figure 60. Input Common-Mode Voltage vs Output Voltage

VS= ±15 V VREF = 0 V

Figure 61. Input Common-Mode Voltage vs Output Voltage

l TEXAS INSTRUMENTS H age (V)

Input Voltage (V)

Input Current (mA)

Output Voltage (V)

-50 -40 -30 -20 -10 0 10 20 30 40 50

-10 -20

-8 -16

-6 -12

-4 -8

-2 -4

0 0

2 4

4 8

6 12

8 16

10 20

D015

Input Current

Output Voltage

+VS

-VS

Overvoltage

Protection

Input Transistor

-V

Input Voltage

Source

ZD1

ZD2

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8.3.4 Input Protection

The inputs of the INA821 device are individually protected for voltages up to ±40 V. For example, a condition of

–40 V on one input and +40 V on the other input does not cause damage. Internal circuitry on each input

provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry

limits the input current to a value of approximately 8 mA.

Figure 62. Input Current Path During an Overvoltage Condition

During an input overvoltage condition, current flows through the input protection diodes into the power supplies,

as shown in Figure 62. If the power supplies are unable to sink current, then Zener diode clamps (ZD1 and ZD2

in Figure 62) must be placed on the power supplies to provide a current pathway to ground. Figure 63 shows the

input current for input voltages from –40 V to +40 V when the INA821 is powered by ±15-V supplies.

Figure 63. Input Current vs Input Overvoltage

l TEXAS INSTRUMENTS

5.49 k

VCM = 10 V

+15 V

VOUT = 1 V

±15 V

RS+

1 k

REF

+VS±VS

INA

RS±

0.99 k

VDIFF = VOUT / G

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8.3.5 Operating Voltage

The INA821 operates over a power-supply range of 4.5 V to 36 V (±2.25 V to ±18 V).

CAUTION

Supply voltages higher than 40 V (±20 V) can permanently damage the device.

Parameters that vary over supply voltage or temperature are shown in the Typical

Characteristics section of this data sheet.

8.3.6 Error Sources

Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors

that result from a change in temperature is normally difficult and costly. Therefore, minimize these errors by

choosing high-precision components, such as the INA821, that have improved specifications in critical areas that

impact the precision of the overall system. Figure 64 shows an example application.

Figure 64. Example Application With G = 10 V/V and a 1-V Output Voltage

Resistor-adjustable devices (such as the INA821) show the lowest gain error in G = 1 because of the inherently

well-matched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G =

10 V/V or G = 100 V/V), the gain error becomes a significant error source because of the contribution of the

resistor drift of the 24.7-kΩfeedback resistors in conjunction with the external gain resistor. Except for very high

gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset

drift.

The INA821 offers excellent gain error over temperature for both G > 1 and G = 1 (no external gain resistor).

Table 5 summarizes the major error sources in common INA applications and compares the three cases of G = 1

(no external resistor) and G = 10 (5.49-kΩexternal resistor) and G = 100 (499-Ωexternal resistor). All

calculations are assuming an output voltage of VOUT = 1 V. Thus, the input signal VDIFF (given by VDIFF= VOUT/G)

exhibits smaller and smaller amplitudes with increasing gain G. In this example, VDIFF = 1 mV at G = 1000. All

calculations refer the error to the input for easy comparison and system evaluation. As Table 5 shows, errors

generated by the input stage (such as input offset voltage) are more dominant at higher gain, while the effects of

output stage are suppressed because they are divided by the gain when referring them back to the input. the

gain error and gain drift error are much more significant for gains greater than 1 because of the contribution of

the resistor drift of the 24.7-kΩfeedback resistors in conjunction with the external gain resistor. In most

applications, static errors (absolute accuracy errors) can readily be removed during calibration in production,

while the drift errors are the key factors limiting overall system performance.

l TEXAS INSTRUMENTS

(e +

NI2

eNO

VDIFF

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Table 4. System Specifications for Error Calculation

QUANTITY VALUE UNIT

VOUT 1 V

VCM 10 V

VS 1 V

RS+ 1000 Ω

RS– 999 Ω

RG tolerance 0.01 %

RG drift 10 ppm/°C

Temperature range upper limit 105 °C

Table 5. Error Calculation

ERROR SOURCE ERROR CALCULATION

INA821 VALUES

SPECIFICATION UNIT G = 1

ERROR

(ppm)

G = 100

ERROR

(ppm)

G = 1000

ERROR

(ppm)

ABSOLUTE ACCURACY AT 25°C

Input offset voltage VOSI / VDIFF 35 µV 35 350 3500

Output offset voltage VOSO / (G × VDIFF) 300 µV 350 350 350

Input offset current IOS × maximum (RS+, RS–) / VDIFF 0.5 nA 1 5 50

CMRR (min) VCM / (10CMRR/20 × VDIFF)92 (G = 1),

112 (G = 10),

132 (G = 100) dB 251 251 251

PSRR (min) (VCC – VS)/ (10PSRR/20 × VDIFF)110 (G = 1),

114 (G = 10),

130 (G = 100) dB 3 20 32

Gain error from INA (max) GE(%) × 1040.02 (G = 1),

0.15 (G = 10, 100) % 200 1500 1500

Gain error from external resistor RG (max) GE(%) × 1040.01 % 100 100 100

Total absolute accuracy error (ppm) at 25°C,

worst case sum of all errors — — 940 2576 5738

Total absolute accuracy error (ppm) at 25°C,

average rms sum of all errors — — 487 1603 3834

DRIFT TO 105°C

Gain drift from INA (max) GTC × (TA– 25) 5 (G = 1),

35 (G = 10, 100) ppm/°C 400 2800 2800

Gain drift from external resistor RG (max) GTC × (TA– 25) 10 ppm/°C 800 800 800

Input offset voltage drift (max) (VOSI_TC / VDIFF) × (TA– 25) 0.4 µV/°C 32 320 3200

Output offset voltage drift [VOSO_TC / ( G × VDIFF)] × (TA– 25) 5 µV/°C 400 400 400

Offset current drift IOS_TC × maximum (RS+, RS–) ×

(TA– 25) / VDIFF 20 pA/°C 2 16 160

Total drift error to 105°C (ppm), worst case sum of all errors — — 1634 4336 7360

Total drift error to 105°C (ppm), typical rms sum of all errors — — 980 2957 4348

RESOLUTION

Gain nonlinearity 10 (G = 1, 10),

15 (G = 100) ppm of FS 10 10 15

Voltage noise (at 1 kHz) eNI = 7,

eNO = 65 µVPP 1335 886 3566

Current noise (at 1kHz) IN× maximum (RS+, RS–) × √BW /

VDIFF 0.13 pA/√Hz 0.4 2 11

Total resolution error (ppm), worst case sum of all errors — — 1345 896 3581

Total resolution error (ppm), typical rms sum of all errors — — 1335 886 3566

TOTAL ERROR

Total error (ppm), worst case sum of all errors — — 3919 7808 16724

Total error (ppm), typical rms sum of all errors — — 1726 3478 6806

‘5‘ TEXAS INSTRUMENTS

10 k

24.7 k

10 k

10 k10 k

24.7 k

Over-

Voltage

Protection

Over-

Voltage

Protection

REF

+VS

V-

OUT

V+

-VS

-IN

+IN

RREF

INA821

SBOS893D –AUGUST 2018–REVISED JUNE 2020

www.ti.com

Product Folder Links: INA821

8.4 Device Functional Modes

The INA821 has a single functional mode and is operational when the power supply voltage is greater than 4.5 V

(±2.25 V). The maximum power-supply voltage for the INA821 is 36 V (±18 V).

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Reference Pin

The output voltage of the INA821 is developed with respect to the voltage on the reference pin (REF.) Often in

dual-supply operation, REF (pin 6) connects to the low-impedance system ground. In single-supply operation,

offsetting the output signal to a precise midsupply level is useful (for example, 2.5 V in a 5-V supply

environment). To accomplish this level shift, a voltage source must be connected to the REF pin to level-shift the

output so that the INA821 drives a single-supply analog-to-digital converter (ADC).

The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 65, any

resistance at the reference pin ( RREF in Figure 65) is in series with one of the internal 10-kΩresistors.

Figure 65. Parasitic Resistance Shown at the Reference Pin

l TEXAS INSTRUMENTS L

+IN

±IN

REF

+VS±VS

INA821

5 V

OPA191

100 k

5 V

1 F

5 V

100 k

OUT

100

120

10 100 1k 10k

Common-Mode Rejection Ratio (dB)

0 Ω

10 Ω

5 Ω

15 Ω

20 Ω

Frequency (Hz)

INA821

www.ti.com

SBOS893D –AUGUST 2018–REVISED JUNE 2020

Product Folder Links: INA821

Application Information (continued)

The parasitic resistance at the reference pin (RREF) creates an imbalance in the four resistors of the internal

difference amplifier that results in a degraded common-mode rejection ratio (CMRR). Figure 66 shows the

degradation in CMRR of the INA821 as a result of the increased resistance at the reference pin. For the best

performance, keep the source impedance to the REF pin (RREF) less than 5 Ω.

Figure 66. The Effect of Increasing Resistance at the Reference Pin

Voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference

pin. However, if a resistor voltage divider generates a reference voltage, buffer the divider by an op amp, as

shown in Figure 67, to avoid CMRR degradation.

Figure 67. Use an Op Amp to Buffer Reference Voltages

TI Device

47 kW47 kW

TI Device

10 kW

Microphone,

Hydrophone,

and So Forth

Thermocouple

TI Device

Center tap provides

bias current return.

INA821

SBOS893D –AUGUST 2018–REVISED JUNE 2020

www.ti.com

Product Folder Links: INA821

Application Information (continued)

9.1.2 Input Bias Current Return Path

The input impedance of the INA821 is extremely high (approximately 100 GΩ.) However, a path must be

provided for the input bias current of both inputs. This input bias current is typically 150 pA. High input

impedance means that this input bias current changes little with varying input voltage.

For proper operation, Input circuitry must provide a path for this input bias current. Figure 68 shows various

provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds

the common-mode range of the INA821 and the input amplifiers saturate. If the differential source resistance is

low, the bias current return path connects to one input (as shown in the thermocouple example in Figure 68).

With a higher source impedance, using two equal resistors provides a balanced input with possible advantages

of a lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.

Figure 68. Providing an Input Common-Mode Current Path

l TEXAS INSTRUMENTS Voun VnX VREF ’(wa 3 X Vm V [i]

V = V G + V = G + V

OUT V D REF--REF

´ ´

VIN ´

R + R

V = V G + V = (I R ) G + V

OUT I D REF IN 3--REF

´ ´ ´

RG = 10.4 NŸ

R3 =

20 Ÿ

R2 = 4.17 NŸ

R1 = 100 NŸ

INA821 VOUT

±10 V

±20 mA

2.5 V ± 2.3 V

+VS

-VS

REF

15 V

REF5025

1 F

VOUT

VIN

GND

1 F1 F

15 V

-15 V

-IN

+IN

OUT

INA821

www.ti.com

SBOS893D –AUGUST 2018–REVISED JUNE 2020

Product Folder Links: INA821

9.2 Typical Application

Figure 69 shows a three-pin programmable-logic controller (PLC) design for the INA821. This PLC reference

design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ±2.3 V (or 200 mV to

4.8 V). Typically, PLCs have these input and output ranges.

Figure 69. PLC Input (±10 V, 4 mA to 20 mA)

9.2.1 Design Requirements

For this application, the design requirements are as follows:

• 4-mA to 20-mA input with less than 20-Ωburden

• ±20-mA input with less than 20-Ωburden

• ±10-V input with impedance of approximately 100 kΩ

• Maximum 4-mA to 20-mA or ±20 mA burden voltage equal to ±0.4 V

• Output range within 0 V to 5 V

9.2.2 Detailed Design Procedure

There are two modes of operation for the circuit shown in Figure 69: current input and voltage input. This design

requires R1>> R2>> R3. Given this relationship, Equation 3 calculates the current input mode transfer function.

where

• G represents the gain of the instrumentation amplifier.

• VDrepresents the differential voltage at the INA821 inputs.

• VREF is the voltage at the INA821 REF pin.

• IIN is the input current. (3)

Equation 4 shows the transfer function for the voltage input mode.

where

• VIN is the input voltage (4)

l TEXAS INSTRUMENTS R R v V £1 V‘N VD v v , G VD Re 49.4 k 49.4 k n

C001

-20 -10 0 10 20

Output Voltage (V)

Input Current (mA) C001

-10 -5 0 5 10

Output Voltage (V)

Input Voltage (V)

: :

 

49.4 k 49.4 k

R 10.4 k

G 1 5.75 1

V V

OUT REF

G = == 5.75

4.8 V 2.5 V

400 mV

-V

R V

1 D

V V

IN -D

R + R

V = V R

D IN 2 =´ ® = 4.167 kW

INA821

SBOS893D –AUGUST 2018–REVISED JUNE 2020

www.ti.com

Product Folder Links: INA821

Typical Application (continued)

R1sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. The R1

value is 100 kΩbecause increasing the R1value also increases noise. The value of R3must be extremely small

compared to R1and R2. The value of R3is 20 Ωbecause that resistance value is smaller than R1and yields an

input voltage of ±400 mV when operating in current mode (±20 mA).

Use Equation 5 to calculate R2if VD= ±400 mV, VIN = ±10 V, and R1= 100 kΩ.

(5)

The value obtained from Equation 5 is not a standard 0.1% value, so 4.17 kΩis selected. R1and R2use 0.1%

tolerance resistors to minimize error.

Use Equation 6 to calculate the gain of the instrumentation amplifier.

(6)

Equation 7 calculates the gain-setting resistor value using the INA821 gain equation (Equation 1).

(7)

Use a standard 0.1% resistor value of 10.5 kΩfor this design.

9.2.3 Application Curves

Figure 70 and Figure 71 show typical characteristic curves for the circuit in Figure 69.

Figure 70. PLC Output Voltage vs Input Voltage Figure 71. PLC Output Voltage vs Input Current

0.5

1.5

2.5

3.5

4.5

0 50 100 150 200

Output Voltage (V)

Temperature (°C)

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0 50 100 150 200

Error (ƒC)

Temperature (°C) C001

-IN

+IN

REF

+VS

-VS

INA821

15 V

VOUT

0 V at 0°C

5 V at 200°C

25 mV/°C

-15 V

4.99

k

4.99

k

100 

Pt100 RTD

100 

105 k

801 

1.18 k

REF5050

100

k

1 F

VOUT

VIN

GND

1 F

OUT

INA821

www.ti.com

SBOS893D –AUGUST 2018–REVISED JUNE 2020

Product Folder Links: INA821

9.3 Other Application Examples

9.3.1 Resistance Temperature Detector Interface

Figure 72 illustrates a 3-wire interface circuit for resistance temperature detectors (RTDs). The circuit

incorporates analog linearization and has an output voltage range from 0 V to 5 V. The linearization technique

employed is described in Analog linearization of resistance temperature detectors analog application journal.

Series and parallel combinations of standard 1% resistor values are used to achieve less than 0.02°C of error

over a 200°C temperature span.

Figure 72. A 3-Wire Interface for RTDs With Analog Linearization

Figure 73. Transfer Function of 3-Wire RTD Interface Figure 74. Temperature Error Over Full Temperature

Range

l TEXAS INSTRUMENTS

INA821

SBOS893D –AUGUST 2018–REVISED JUNE 2020

www.ti.com

Product Folder Links: INA821

10 Power Supply Recommendations

The nominal performance of the INA821 is specified with a supply voltage of ±15 V and midsupply reference

voltage. The device also operates using power supplies from ±2.25 V (4.5 V) to ±18 V (36 V) and non-midsupply

reference voltages with excellent performance. Parameters that can vary significantly with operating voltage and

reference voltage are shown in the Typical Characteristics section.

11 Layout

11.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals. Even slight mismatch in parasitic capacitance at the gain

setting pins can degrade CMRR over frequency. For example, in applications that implement gain switching

using switches or PhotoMOS®relays to change the value of RG, select the component so that the switch

capacitance is as small as possible and most importantly so that capacitance mismatch between the RG pins

is minimized.

• Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Place the external components as close to the device as possible. As shown in Figure 75, keep RGclose to

the pins to minimize parasitic capacitance.

• Keep the traces as short as possible.

• Connect exposed thermal pad to negative supply –V.

‘5‘ TEXAS INSTRUMENTS

OUT

+IN

-IN

OUT

-V

REF

+VS±VS

INA821

±IN 8+VS

RG 7OUT

RG 6REF

4 +IN 5-VS

GND

+IN

±IN

Use ground pours for

shielding the input

signal pairs

GND

-V

Low-impedance

connection for

reference terminal

Place bypass

capacitors as close to

IC as possible

REF

INA821

www.ti.com

SBOS893D –AUGUST 2018–REVISED JUNE 2020

Product Folder Links: INA821

11.2 Layout Example

Figure 75. Example Schematic and Associated PCB Layout

l TEXAS INSTRUMENTS

INA821

SBOS893D –AUGUST 2018–REVISED JUNE 2020

www.ti.com

Product Folder Links: INA821

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

•SPICE-based analog simulation program — TINA-TI software folder

•Common-Mode Input Range Calculator for Instrumentation Amplifiers

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note

• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet

• Texas Instruments, OPAx191 36-V, Low Power, Precision, CMOS, Rail-to-Rail Input/Output, Low Offset

Voltage, Low Input Bias Current Op Amp data sheet

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

I TEXAS INSTRUMENTS Samples Samples Sample: Sample: Samples Samples

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

INA821ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821

INA821IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1X4Q

INA821IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1X4Q

INA821IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821

INA821IDRGR ACTIVE SON DRG 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821

INA821IDRGT ACTIVE SON DRG 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 INA821

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension destgned to accommodate the component tengtti K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pttch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

INA821IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

INA821IDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

INA821IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

INA821IDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

INA821IDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 1

I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

INA821IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0

INA821IDGKT VSSOP DGK 8 250 366.0 364.0 50.0

INA821IDR SOIC D 8 2500 853.0 449.0 35.0

INA821IDRGR SON DRG 8 3000 367.0 367.0 35.0

INA821IDRGT SON DRG 8 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 2

‘J

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

Yl“‘+

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud ﬂasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com

LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Deﬁned Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH oﬂer eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com

MECHANICAL DATA DLHST‘ 3 SM ALL OU’ \j Q, [AC mam/c wz/m AH Mnec' dwmenswors c'e m m hmeters Dwmenswmmg one «meranmg per ASME vaAeaL Th5 dvuwmg 1: sub 0 change mum: "om SON {31'qu Cuihne Nomad) suckuge cmvhgmuhon. We pacmge We’ma‘ pad mm be Jcered to (he boarc (or Warm: and mec'vumca‘ performance See me Pmdud Dam Sweet M de us veguvdmg the exposed Ovev'm pud mmensmns JEDEC M07229 Duckuge 'egistvutu'v pendmg. {if TEXAS INSTRUMENTS www.1i.com

www.ti.com

PACKAGE OUTLINE

8X 0.3

0.2

2.4 0.1

1.5

1.45 0.1

6X 0.5

0.8

0.7

8X 0.6

0.4

0.05

0.00

A3.1

2.9 B

3.1

2.9

(DIM A) TYP

OPT 01 SHOWN

WSON - 0.8 mm max heightDRG0008B

PLASTIC SMALL OUTLINE - NO LEAD

4218886/A 01/2020

DIMENSION A

OPTION 01 (0.1)

OPTION 02 (0.2)

PIN 1 INDEX AREA

SEATING PLANE

0.05 C

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.08 C

THERMAL PAD

EXPOSED

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

8X (0.25)

(2.4)

(2.7)

6X (0.5)

(1.45)

( 0.2) VIA

TYP

(0.475)

(0.95)

8X (0.7)

(R0.05) TYP

WSON - 0.8 mm max heightDRG0008B

PLASTIC SMALL OUTLINE - NO LEAD

4218886/A 01/2020

SYMM

LAND PATTERN EXAMPLE

SCALE:20X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

SOLDER MASK

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

8X (0.25)

8X (0.7)

(1.47)

(1.07)

(2.7)

(0.635)

6X (0.5)

WSON - 0.8 mm max heightDRG0008B

PLASTIC SMALL OUTLINE - NO LEAD

4218886/A 01/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

82% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

SYMM

METAL

TYP

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

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warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments 的 INA821 规格书

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