Slide 1 Slide 2 Slide 3 Slide 4 Slide 5 Slide 6 Slide 7 Slide 8 Slide 9 Slide 10 Slide 11 Slide 12 Slide 13 Slide 14 Slide 15 Slide 16 Slide 17 Slide 18 Slide 19 Product List
DAC-Architecture-Slide14

This figure shows a typical example of a 14-bit core of the TxDAC family. This is an excellent illustration of the "segmented" DAC architecture. The five MSBs (most significant bits) are fully decoded into 31 equal current switches. The next four bits are fully decoded into 15 equal current switches. The five LSBs are binary decoded. Note that a second latch (51 bits) is used to drive the output current switches, which eliminates the delay "skew" added by the decoding logic which follows the input 14-bit latch. The timing between this latch and each switch is critical. All the currents are combined to produce the final output current. This architecture yields excellent low-distortion performance. In practice, the DAC is fully differential for better linearity and to minimize second-order distortion.

PTM Published on: 2009-08-10