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As discussed previously for four wire, shown here are the specifics to MSP430 SBW support. The connections required reduce simplifying the physical design requirements to interface to the MSP430. The connections consist of the clock, SBWTCK as well as the bidirectional data line, SBWTDIO. These pins of the given MSP430 are to be connected to pin 1, TDO/TDI, and pin 7, TCK, respectively in order for the SBW interface to properly function with a MSP430 JTAG programmer. GND and VCC connections apply as described earlier for the four wire implementation and are identical. Handing of the TEST pin at the programmer side, pin 8 on the header, is only required in the case that a physical JTAG fuse on a given MSP430 target device needs to be blown post-programming. If this is the case, it is important to also provide R2 as shown above. This will protect the TCK pin of the programmer from the high fuse blow voltage that is driven onto the TEST/SBWTCK pin during the fuse blow procedure. An additional requirement is regarding capacitance on the RST/SBWTDIO pin. Often, having a small capacitance on this pin is helpful in-design to reduce noisy transitions that can appear, resetting the device during power transients or noisy events such as ESD discharges and PCB-related noise coupling. A typical value is 10 nF however must be kept below a maximum of 2.2 nF for valid SBW communication. Values exceeding this may degrade the high/low edge transitions to a point that SBW communication is no longer possible. In designs that need a larger capacitor on RST for any reason, it should only be populated AFTER the SBW programming of the target. Here the designer can also find a table indicating MSP430 devices and sub families supporting the SBW mode. Support for SBW is found typically on TI’s smaller devices due to the advantages of consuming fewer pins with a minimized application design impact. All newer F5xx and F6xx devices support both four wire and two wire SBW, independent of physical size or pin count.
