EPC 的 EPC2214 规格书

RoHS (A @ Halogen-Free
eGaN® FET DATASHEET EPC2214
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
EPC2214 – Automotive 80 V (D-S)
Enhancement Mode Power Transistor
VDS , 80 V
RDS(on) , 20 mΩ
ID , 10 A,
AEC-Q101
EPC2214 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 1.35 mm x 1.35 mm
Applications
• Lidar/Pulsed Power Applications
• DC-DC Conversion
• Wireless Power Transfer
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 80 V
ID
Continuous (TA = 25°C) 10 A
Pulsed (25°C, TPULSE = 300 µs) 47
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Static Characteristics (TJ= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.2 mA 80 V
IDSS Drain-Source Leakage VDS = 64 V, VGS = 0 V, TJ = 25°C 0.003 0.15 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.003 1.1 mA
Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125°C 0.01 2.5 mA
Gate-to-Source Reverse Leakage VGS = -4 V, TJ = 25°C 0.003 0.15 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 2 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 6 A 15 20 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
# Defined by design. Not subject to production test.
Thermal Characteristics
PARAMETER TYP UNIT
R
θ
JC Thermal Resistance, Junction-to-Case 2.7
°C/WR
θ
JB Thermal Resistance, Junction-to-Board 7.5
R
θ
JA Thermal Resistance, Junction-to-Ambient (Note 1) 81
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET EPC2214
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40
30
20
10
00 0.5 1.0 1.5 2.0 2.5 3.0
ID
–
Drain Current (A)
VDS – Drain-to-Source Voltage (A)
Figure 1: Typical Output Characteristics at 25°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
3.0 3.5 2.0 2.5 4.0 4.5 5.0
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 3 A
ID = 6 A
ID = 9 A
ID = 12 A
60
50
40
30
20
10
0
ID
–
Drain Current (A)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
25˚C
125˚C
VDS = 3 V
VGS – Gate-to-Source Voltage (V)
Figure 2: Transfer Characteristics
25°C
125°C
VDS = 3 V
40
30
20
10
0
60
50
40
30
20
10
0
Figure 4: RDS(on) vs. VGS for Various Temperatures
25°C
125°C
ID = 6 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
3.0 3.5 2.0 2.5 4.0 4.5 5.0
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance#
VDS = 40 V, VGS = 0 V
198 238
pF
CRSS Reverse Transfer Capacitance 1.8
COSS Output Capacitance#129 194
COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 0 to 40 V, VGS = 0 V 171
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 211
RG Gate Resistance 0.65 Ω
QG Total Gate Charge#VDS = 40 V, VGS = 5 V, ID = 6 A 1.8 2.2
nC
QGS Gate to Source Charge
VDS = 40 V, ID = 6 A
0.5
QGD Gate to Drain Charge 0.3
QG(TH) Gate Charge at Threshold 0.4
QOSS Output Charge#VDS = 40 V, VGS = 0 V 8 12
QRR Source-Drain Recovery Charge 0
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
\
eGaN® FET DATASHEET EPC2214
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Capacitance (pF)
1000
100
10
1
0 20 40 60
80
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD – Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8: Reverse Drain-Source Characteristics
25°C
VGS = 0 V
125°C
40
30
20
10
0
Capacitance (pF)
0 20 40 60 80
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
350
300
250
200
150
100
50
0
0 0.5 1.0 1.5 2.0
Figure 7: Gate Charge
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
ID = 6 A
VDS = 40 V
5
4
3
2
1
0
0 20 40 60 8010 30 50 70
Figure 6: Output Charge and COSS Stored Energy
Q
OSS
– Output Charge (nC)
EOSS – COSS Stored Energy (μJ)
VDS – Drain-to-Source Voltage (V)
14.0
11.2
8.4
5.8
2.8
0
0.45
0.36
0.27
0.18
0.09
0.00
Figure 9: Normalized On-State Resistance vs. Temperature
ID = 6 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
All measurements were done with substrate shortened to source.
fir * "T T—I
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Figure 11: Transient Thermal Response Curves
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.05
0.02
Single Pulse
0.01
0.2
0.1
Duty Cycle:
10-5 10-4 10-3 10-2 10-1 1 101
1
0.1
0.01
0.001
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
Junction-to-Board
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
0.1
0.02
0.05
Single Pulse
0.01
0.2
Duty Cycle:
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
Figure 10: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 2 mA
6) 63 e G) ‘ 69 —— Dlmenslon[mm) target mln max a 0.00 7.90 3,30 0 1.75 1,65 1.95 c (na1e2) 3.50 3,45 3.55 d 4.00 3,90 4.10 e 4.00 3,90 4.10 f(n0|e2| 2.00 1,95 2.05 g 1.5 1.5 1.6
eGaN® FET DATASHEET EPC2214
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2214
YYYY
ZZZZ EPC2214 2214 YYYY ZZZZ
Die orientation dot
Gate Pad bump is
under this corner
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
Part
Number
Laser Markings
DIE MARKINGS
YYYY
ZZZZ
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” reel
a
d e f g
c
b
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
Figure 12: Safe Operating Area 100
10
1
0.1 0.1 1 10 100
ID – Drain Current (A)
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Limited by RDS(on)
Pulse Width
1 ms
100 µs
10 µs
EPC2214 (note 1)
2214
eGaN® FET DATASHEET EPC2214
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6
Information subject to
change without notice.
Revised May, 2020
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED
LAND PATTERN
(measurements in µm)
The land pattern is solder mask defined
Solder mask is 10 μm smaller per side than bump
DIE OUTLINE
Pad View
Side View
DIM
Micrometers
MIN Nominal MAX
A1320 1350 1380
B1320 1350 1380
c450
d225
DIM Micrometers
A1350
B1350
c450
d1 205
DIM Micrometers
A1350
B1350
c450
d1 225
dc c
d1
d1
d c c
3 9
2 8
1 7
6
5
4
A
B
RECOMMENDED
STENCIL DRAWING
(measurements in µm)
Recommended stencil should be 4 mil (100 µm) thick,
must be laser cut, openings per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
dc c
d1
d1
d c c
3 9
2 8
1 7
6
5
4
A
BB
A
dc c
d
d c c
805
685 +/−15120 +/−12
Seating Plane
3 9
2 8
1 7
6
5
4
Pad 1 is Gate;
Pads 4, 5, 6, 7 are Drain;
Pads 2, 3, 8, 9 are Source.
Pad 1 is Gate;
Pads 4, 5, 6, 7 are Drain;
Pads 2, 3, 8, 9 are Source.