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LTLII‘IM TECHNOLOGY L7 LJUW 1

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL APPLICATION

FEATURES DESCRIPTION

Nanopower Buck-Boost

DC/DC with Energy Harvesting

Battery Life Extender

The LT C

3330 integrates a high voltage energy harvesting

power supply plus a DC/DC converter powered by a primary

cell battery to create a single output supply for alternative

energy applications. The energy harvesting power sup-

ply, consisting of an integrated full-wave bridge rectifier

and a high voltage buck converter, harvests energy from

piezoelectric, solar, or magnetic sources. The primary cell

input powers a buck-boost converter capable of opera-

tion down to 1.8V at its input. Either DC/DC converter

can deliver energy to a single output. The buck operates

when harvested energy is available, reducing the quiescent

current draw on the battery to essentially zero, thereby

extending the life of the battery. The buck-boost powers

VOUT only when harvested energy goes away.

A low noise LDO post regulator and a supercapacitor

balancer are also integrated, accommodating a wide range

of output storage configurations. Voltage and current set-

tings for both inputs and outputs are programmable via

pin-strapped logic inputs. The LTC3330 is available in a

5mm × 5mm QFN-32 package.

APPLICATIONS

n Dual Input, Single Output DC/DCs with Input

Prioritizer

n Energy Harvesting Input: 3.0V to 19V Buck DC/DC

n Primary Cell Input: 1.8V to 5.5V Buck-Boost DC/DC

n Zero Battery IQ When Energy Harvesting Source is

Available

n Ultralow Quiescent Current: 750nA at No-Load

n Low Noise LDO Post Regulator

n Integrated Supercapacitor Balancer

n Up to 50mA of Output Current

n Programmable DC/DC and LDO Output Voltages,

Buck UVLO, and Buck-Boost Peak Input Current

n Integrated Low Loss Full-Wave Bridge Rectifier

n Input Protective Shunt: Up to 25mA at VIN ≥ 20V

n 5mm × 5mm QFN-32 Package

n Energy Harvesting

n Solar Powered Systems with Primary Cell Backup

n Wireless HVAC Sensors and Security Devices

n Mobile Asset Tracking L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Extended Battery Life with

Energy Harvesting

PIEZO

MIDE

V25W

1µF

6.3V

4.7µF, 6.3V

GND

LTC3330

3330 TA01a

AC1

VIN

CAP

VIN2

BAT

OUT[2:0]

LDO[2:0]

IPK[2:0]

UV[3:0]

AC2

SWA

22µH

SWB

VOUT

LDO_IN

SCAP

BAL

LDO_EN

EH_ON

PGVOUT

PGLDO

LDO_OUT

VIN3

3V TO 19V

SOLAR

PANEL

4.7µF

6.3V

PRIMARY

CELL

1.8V TO 5.5V

22µF

25V

1µF

6.3V

22µF

6.3V

1.2V TO 3.3V

50mA

1.8V TO 5V

50mA

10mF

2.7V

10mF

2.7V

OPTIONAL

47µF

6.3V

–

VOUT

50mV/DIV

AC-COUPLED

EH_ON

2V/DIV

IBAT

100mA/DIV

200µs/DIV 3330 TA01b

BAT = 3.6V

VOUT = 1.8V

ILOAD = 50mA

ACTIVE ENERGY

HARVESTER

REDUCES BATTERY

CURRENT TO ZERO

LTC3330 ‘32) EU ‘30) ‘29) ‘23) ‘27) ‘25) ‘25) 2 L7LJ1‘JW

LTC3330

3330fc

For more information www.linear.com/LTC3330

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

VIN

Low Impedance Source ..........................–0.3 to 19V*

Current-Fed, ISW = 0A ........................................25mA

AC1, AC2 .............................................................0 to VIN

BAT, VOUT, VIN3, LDO_IN, SCAP, PGVOUT,

PGLDO, LDO_EN ............................................. –0.3 to 6V

VIN2 .................... –0.3V to [Lesser of (VIN + 0.3V) or 6V]

CAP ...................... [Higher of –0.3V or (VIN – 6V)] to VIN

LDO_OUT, LDO[2:0] .................–0.3V to LDO_IN + 0.3V

BAL ...............................................–0.3V to SCAP + 0.3V

OUT[2:0], IPK[2:0],

EH_ON .............–0.3V to [Lesser of (VIN3 + 0.3V) or 6V]

UV[3:0] ............ –0.3V to [Lesser of (VIN2 + 0.3V) or 6V]

IAC1, IAC2 ..............................................................±50mA

ISW, ISWA, ISWB, IVOUT ..........................................350mA

ILDO_OUT .................................................................50mA

Operating Junction Temperature Range

(Notes 2, 3) ............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

*VIN has an internal 20V clamp

(Note 1)

GND

31 30 29 28 27 26 25

9 10 11 12

TOP VIEW

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

13 14 15 16

1BAL

SCAP

VIN2

UV3

UV2

UV1

UV0

AC1

LDO0

LDO1

LDO2

LDO_IN

LDO_OUT

IPK2

IPK1

IPK0

OUT2

OUT1

OUT0

EH_ON

PGVOUT

PGLDO

VIN3

LDO_EN

AC2

VIN

CAP

VOUT

SWB

SWA

BAT

TJMAX = 125°C, θJA = 44°C/W

EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3330EUH#PBF LTC3330EUH#TRPBF 3330 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C

LTC3330IUH#PBF LTC3330IUH#TRPBF 3330 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC3330 L7 LJUW 3

LTC3330

3330fc

For more information www.linear.com/LTC3330

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Buck Input Voltage Range l 19 V

VBAT Buck-Boost Input Voltage Range l1.8 5.5 V

IVIN VIN Quiescent Current

VIN Input in UVLO

Buck Enabled, Sleeping

Buck Enabled, Not Sleeping

VIN = 2.5V, BAT = 0V

VIN = 16V, BAT = 0V

VIN = 4V, BAT = 0V

VIN = 18V, BAT = 0V

VIN = 5V, BAT = 0V, ISW1 = 0A (Note 4)

450

840

1200

1800

150

700

1400

1800

2500

225

µA

IBAT BAT Quiescent Current

BAT Input with VIN Active

Buck-Boost Enabled, Sleeping

Buck-Boost Enabled, Not Sleeping

BAT = 1.8V, VIN = 5V

BAT = 5V, VIN = 0V

BAT = 5V, VIN = 0V, ISWA = ISWB = 0A

(Note 4)

–10

750

200

1200

300

µA

IVOUT VOUT Leakage Current VOUT = 5.0V, OUT[2:0] = 111, Sleeping 100 150 nA

VINUVLO VIN Undervoltage Lockout Thresholds

(Rising or Falling)

3V Level l2.91 3.00 3.09 V

4V Level l3.88 4.00 4.12 V

5V Level l4.85 5.00 5.15 V

6V Level l5.82 6.00 6.18 V

7V Level l6.79 7.00 7.21 V

8V Level l7.76 8.00 8.24 V

9V Level l8.73 9.00 9.27 V

10V Level l9.70 10.0 10.30 V

11V Level l10.67 11.0 11.33 V

12V Level l11.64 12.0 12.36 V

13V Level l12.61 13.0 13.39 V

14V Level l13.58 14.0 14.42 V

15V Level l14.55 15.0 15.45 V

16V Level l15.52 16.0 16.48 V

17V Level l16.49 17.0 17.51 V

18V Level l17.46 18.0 18.54 V

VSHUNT VIN Shunt Regulator Voltage IVIN = 1mA l19.0 20.0 21.0 V

ISHUNT Maximum Protective Shunt Current 25 mA

Internal Bridge Rectifier Loss (|VAC1 – VAC2| – VIN) IBRIDGE = 10µA

IBRIDGE = 50mA

700

1350

800

1550

900

1750

Internal Bridge Rectifier Reverse Leakage Current VREVERSE = 18V 20 nA

Internal Bridge Rectifier Reverse Breakdown

Voltage

IREVERSE = 1µA VSHUNT 30 V

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless

otherwise specified.

LTC3330 4 L7LJ1W

LTC3330

3330fc

For more information www.linear.com/LTC3330

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT Regulated Buck/Buck-Boost Output Voltage 1.8V Output Selected

Sleep Threshold

Wake-Up Threshold

1.728

1.806

1.794

1.872

2.5V Output Selected

Sleep Threshold

Wake-Up Threshold

2.425

2.508

2.492

2.575

2.8V Output Selected

Sleep Threshold

Wake-Up Threshold

2.716

2.809

2.791

2.884

3.0V Output Selected

Sleep Threshold

Wake-Up Threshold

2.910

3.010

2.990

3.090

3.3V Output Selected

Sleep Threshold

Wake-Up Threshold

3.200

3.311

3.289

3.400

3.6V Output Selected

Sleep Threshold

Wake-Up Threshold

3.492

3.612

3.588

3.708

4.5V Output Selected

Sleep Threshold

Wake-Up Threshold

4.365

4.515

4.485

4.635

5.0V Output Selected

Sleep Threshold

Wake-Up Threshold

4.850

5.017

4.983

5.150

PGVOUT Falling Threshold As a Percentage of VOUT Target (Note 5) l88 92 96 %

IPEAK_BUCK Buck Peak Switch Current 200 250 350 mA

IBUCK Available Buck Output Current 100 mA

IPEAK_BB Buck-Boost Peak Switch Current 250mA Target Selected 200 250 350 mA

150mA Target Selected 120 150 210 mA

100mA Target Selected 80 100 140 mA

50mA Target Selected 40 50 70 mA

25mA Target Selected 20 25 35 mA

15mA Target Selected 12 15 21 mA

10mA Target Selected 8 10 14 mA

5mA Target Selected 4 5 7 mA

IBB Available Buck-Boost Current IPEAK_BB = 250mA, BAT = 1.8V,

VOUT = 3.3V

50 mA

RP_BUCK Buck PMOS Switch On-Resistance 1.4 Ω

RN_BUCK Buck NMOS Switch On-Resistance 1.2 Ω

RP_BB Buck-Boost PMOS Input and Output Switch

On-Resistance

IPK[2:0] = 111

IPK[2:0] = 110

IPK[2:0] = 101

IPK[2:0] = 100

IPK[2:0] = 011

IPK[2:0] = 010

IPK[2:0] = 001

IPK[2:0] = 000

0.7

0.9

1.2

2.1

3.9

6.3

9.2

17.7

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless

otherwise specified.

LTC3330 L7 LJUW 5

LTC3330

3330fc

For more information www.linear.com/LTC3330

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

RN_BB Buck-Boost NMOS Input and Output Switch

On-Resistance

IPK2 = 1

IPK2 = 0

0.6

3.8

ILEAK(P) PMOS Switch Leakage Buck/Buck-Boost Regulators –20 20 nA

ILEAK(N) NMOS Switch Leakage Buck/Buck-Boost Regulators –20 20 nA

Maximum Buck Duty Cycle Buck/Buck-Boost Regulators l100 %

VLDO_IN LDO_IN Input Range l1.8V 5.5V V

ILDO_IN LDO_IN Quiescent Current LDO_IN = 5.0V, ILDO_OUT = 0mA 400 600 nA

ILDO_OUT LDO_OUT Leakage Current LDO_OUT = 3.3V, LDO[2:0] = 110 100 150 nA

LDO_OUT Regulated LDO Output Voltage Error as a Percentage of Target, 100µA

Load

–2.0

–3.0

2.0

3.0

LDO Line Regulation (1.8V to 5.5V) LDO_OUT = 1.2V, 10mA Load 2 mV/V

LDO Load Regulation (10µA to 10mA) LDO_IN = 5.0V, LDO_OUT = 3.3V 0.5 mV/mA

LDO Dropout Voltage LDO_OUT = 3.3V, 10mA LOAD 50 mV

RP_LDO LDO PMOS Switch On-Resistance LDO_IN = 3.3V, ILDO_OUT = 10mA 5 Ω

LDO Current Limit LDO_IN = 5.0V 50 mA

PGLDO Rising Threshold As a Percentage of the 3.3V LDO_OUT

Target

l88 92 96 %

PGLDO Falling Threshold As a Percentage of the 3.3V LDO_OUT

Target

l86 90 94 %

VSCAP Supercapacitor Balancer Input Range l2.5 5.5 V

ISCAP Supercapacitor Balancer Quiescent Current SCAP = 5.0V 150 225 nA

ISOURCE Supercapacitor Balancer Source Current SCAP = 5.0V, BAL = 2.4V 10 mA

ISINK Supercapacitor Balancer Sink Current SCAP = 5.0V, BAL = 2.6V 10 mA

VBAL Supercapacitor Balance Point Percentage of SCAP Voltage l49 50 51 %

VIH Digital Input High Voltage Pins LDO_EN, OUT[2:0], LDO[2:0],

IPK[2:0], UV[3:0]

l1.2 V

VIL Digital Input Low Voltage Pins LDO_EN, OUT[2:0], LDO[2:0],

IPK[2:0], UV[3:0]

l0.4 V

IIH Digital Input High Current Pins LDO_EN, OUT[2:0], LDO[2:0],

IPK[2:0], UV[3:0]

0 10 nA

IIL Digital Input Low Current Pins LDO_EN, OUT[2:0], LDO[2:0],

IPK[2:0], UV[3:0]

0 10 nA

VOH PGVOUT, PGLDO Output High Voltage

EH_ON Output High Voltage

BAT = 5V, 1µA Out of Pin

VIN = 6V, 1µA Out of Pin

4.0

3.8

VOL PGVOUT, PGLDO, EH_ON Output Low Voltage BAT = 5V, 1µA into Pin l0.4 V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3330E is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3330E is guaranteed to meet specifications from 0°C to

85°C. The LTC3330I is guaranteed over the –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

Note 3: TJ is calculated from the ambient TA and power dissipation PD

according to the following formula: TJ = TA + (PD • θJA).

Note 4: Dynamic supply current is higher due to gate charge being

delivered at the switching frequency.

Note 5: The PGVOUT Rising threshold is equal to the sleep threshold. See

VOUT specification.

LTC3330 6 L7LJ1‘JW

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL PERFORMANCE CHARACTERISTICS

UVLO Threshold vs Temperature VSHUNT vs Temperature IVOUT vs Temperature

Total Bridge Rectifier Drop vs

Bridge Current Bridge Leakage vs Temperature Bridge Frequency Response

IVIN in UVLO vs VIN IVIN in Sleep vs VIN IBAT in Sleep vs BAT

VIN (V)

IVIN (nA)

2200

2000

1600

1200

1800

1400

1000

800

600

400

200

096 15

3330 G01

183 12

125°C

85°C

25°C

–40°C

BAT (V)

1.5

IBAT (nA)

2100

1800

1500

1200

900

600

300

03.5 4.5

3330 G03

5.52.5

85°C

25°C

–40°C

125°C

TEMPERATURE (°C)

–50

PERCENTAGE OF TARGET SETTING (%)

103

102

101

100

97 0 25 50 75 100

3330 G04

125–25

APPLIES TO EACH UVLO SETTING

BRIDGE CURRENT (A)

VBRIDGE (mV)

1800

1600

1400

1200

1000

800

600

400

200

3330 G07

1µ 10µ 100m10m100µ

–40°C

25°C

85°C

125°C

|VAC1 – VAC2| – VIN

TEMPERATURE (°C)

–50

VSHUNT (V)

21.0

20.8

20.6

20.4

20.2

20.0

19.8

19.6

19.2

19.4

19.0 0 25 50 75 100

3330 G05

125–25

ISHUNT = 1mA

ISHUNT = 25mA

TEMPERATURE (°C)

–50

IVOUT (nA)

150

140

130

120

110

100

50 0 25 50 75 100

3330 G05

125–25

VOUT IN REGULATION, SLEEPING

FREQUENCY (Hz)

VIN (V)

3330 G09

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

010 100 100M10M1M10k1k 100k

4.8VP-P APPLIED TO AC1/AC2 INPUT

MEASURED IN UVLO

TA = 25°C, unless otherwise noted.

TEMPERATURE (°C)

–55

BRIDGE LEAKAGE (nA)

08035 125

3330 G08

170–10

VIN = 18V, LEAKAGE AT AC1 OR AC2

VIN (V)

IVIN (nA)

6000

5000

4000

3000

2000

1000

096 15

3330 G02

183 12

125°C

–40°C

85°C

25°C

LTC3330 T FALUN L7 LJUW 7

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL PERFORMANCE CHARACTERISTICS

3V Output vs Temperature 3.3V Output vs Temperature 3.6V Output vs Temperature

4.5V Output vs Temperature 5V Output vs Temperature

RDS(ON) of Buck-Boost PMOS/NMOS

vs Temperature, 250mA IPEAK Setting

1.8V Output vs Temperature 2.5V Output vs Temperature 2.8V Output vs Temperature

TEMPERATURE (°C)

–50

VOUT (V)

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

1.68

1.66

1.64 0 25 50 75 100

3330 G10

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

2.55

2.50

2.45

2.40

2.35

2.30

2.25 0 25 50 75 100

3330 G11

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

2.85

2.80

2.75

2.70

2.65

2.60

2.55 0 25 50 75 100

3330 G12

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

3.05

3.00

2.95

2.90

2.85

2.80

2.75

2.70 0 25 50 75 100

3330 G13

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

3.35

3.30

3.25

3.20

3.15

3.10

3.05

3.00 0 25 50 75 100

3330 G14

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

3.65

3.60

3.55

3.50

3.45

3.40

3.35

3.30

3.25 0 25 50 75 100

3330 G15

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

4.60

4.55

4.50

4.45

4.40

4.35

4.30

4.25

4.20

4.15

4.10 0 25 50 75 100

3330 G16

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TEMPERATURE (°C)

–50

VOUT (V)

5.10

5.00

4.90

4.80

4.70

4.60

4.50 0 25 50 75 100

3330 G17

125–25

SLEEP THRESHOLD

PGVOUT FALLING

WAKE-UP THRESHOLD

TA = 25°C, unless otherwise noted.

TEMPERATURE (°C)

–50

RDS(ON) (Ω)

1.6

1.4

1.2

1.0

0.8

0.6

0.4 0 25 50 75 100

3330 G18

125–25

PMOS, BAT = 1.8V

PMOS, BAT = 5V

NMOS, BAT = 1.8V

NMOS, BAT = 5V

LTC3330 I? Wh- NWWM W J‘m‘JLJLL'JJLW. J~\»\s‘x\f\v\9\:\\v\k___ 8 L7LJ1‘JW

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL PERFORMANCE CHARACTERISTICS

Buck-Boost Load Regulation, 3.3V Buck-Boost Line Regulation, 3.3V Buck-Boost Switching Waveforms

Buck Load Regulation, 3.3V Buck Line Regulation, 3.3V Buck Switching Waveforms

RDS(ON) of Buck-Boost PMOS/NMOS

vs Temperature, 5mA IPEAK Setting

IPEAK_BB vs Temperature, 250mA

IPEAK Setting

IPEAK_BB vs Temperature, 5mA

IPEAK Setting

TA = 25°C, unless otherwise noted.

TEMPERATURE (°C)

–50

RDS(ON) (Ω)

00 25 50 75 100

3330 G19

125–25

PMOS, BAT = 1.8V

NMOS, BAT = 1.8V

PMOS, BAT = 5V

NMOS, BAT = 5V

TEMPERATURE (°C)

–50

IPEAK_BB (mA)

300

290

280

270

260

230

220

210

250

200

240

0 25 50 75 100

3330 G20

125–25

BAT = 3.6V

TEMPERATURE (°C)

–50

IPEAK_BB (mA)

6.0

5.8

5.6

5.4

5.2

4.6

4.4

4.2

5.0

4.0

4.8

0 25 50 75 100

3330 G21

125–25

BAT = 3.6V

ILOAD (A)

VOUT (V)

3.400

3.375

3.350

3.325

3.300

3.275

3.225

3.250

3.200

3330 G22

1µ 10µ 10m 100m1m100µ

BAT = 5V

BAT = 1.8V

COUT = 100µF

L = 22µH

IPK[2:0] = 111

BAT (V)

1.8

VOUT (V)

3.400

3.375

3.350

3.325

3.300

3.275

3.250

3.225

3.200 2.6 3.0 3.4 3.8 4.2 4.6

3330 G23

52.2

LOAD = 1mA

LOAD = 100mA

COUT = 100µF

L = 22µH

IPK[2:0] = 111

BAT = 1.8V, VOUT = 3.3V

ILOAD = 10mA

L = 22µH, COUT = 100µF

SWA VOLTAGE

2V/DIV

SWB VOLTAGE

2V/DIV

OUTPUT

VOLTAGE

50mV/DIV

AC-COUPLED

INDUCTOR

CURRENT

200mA/DIV

3330 G24

20µs/DIV

0mA

ILOAD (A)

VOUT (V)

3.400

3.375

3.350

3.325

3.300

3.275

3.225

3.250

3.200

3330 G25

1µ 10µ 10m 100m1m100µ

VIN = 4V

COUT = 100µF

L = 22µH

VIN (V)

VOUT (V)

3.400

3.375

3.350

3.325

3.300

3.275

3.250

3.225

3.200 8 10 12 14 16

3330 G26

186

LOAD = 1mA

LOAD = 100mA

COUT = 100µF

L = 22µH

VIN = 18V, VOUT = 3.3V

ILOAD = 10mA

L = 22µH, COUT = 100µF

SW VOLTAGE

10V/DIV

OUTPUT

VOLTAGE

50mV/DIV

AC-COUPLED

INDUCTOR

CURRENT

200mA/DIV 0mA

3330 G27

8µs/DIV

LTC3330 L7 HEW

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL PERFORMANCE CHARACTERISTICS

Buck-Boost Load Step Response Buck Load Step Response

Prioritizer Buck-Boost to Buck

Transition

Buck Efficiency vs ILOAD

Buck Efficiency vs VIN for

ILOAD = 100mA, L = 22µH

IPEAK_BUCK vs Temperature

RDS(ON) of Buck PMOS/NMOS

vs Temperature

Prioritizer Buck to Buck-Boost

Transition

Buck Efficiency vs VIN for

ILOAD = 100mA, L = 100µH

TEMPERATURE (°C)

–50

IPEAK_BUCK (mA)

300

290

280

270

260

250

240

230

220

200

210

0 25 50 75 100

3330 G28

125–25

VIN = 5V

TEMPERATURE (°C)

–50

RDS(ON) (Ω)

2.0

1.8

1.6

1.4

1.2

0.8

1.0

0 25 50 75 100

3330 G29

125–25

VIN = 5V

PMOS

NMOS

TA = 25°C, unless otherwise noted.

BAT = 3V, VOUT = 3.3V

COUT = 100µF, L = 22µF

LOAD STEP FROM 1mA TO 50mA

OUTPUT

VOLTAGE

20mV/DIV

AC-COUPLED

LOAD

CURRENT

25mA/DIV 1mA

3330 G31

2ms/DIV

VIN = 18V, VOUT = 3.3V

COUT = 100µF, L = 22µF

LOAD STEP FROM 1mA TO 50mA

OUTPUT

VOLTAGE

20mV/DIV

AC-COUPLED

LOAD

CURRENT

25mA/DIV 1mA

3330 G32

2ms/DIV

VIN TRANSITIONS 17V TO 18V, UV[3:0] = 1110

BAT = 4.1V, VOUT = 3.3V

ILOAD = 50mA, COUT = 100µF, LBUCK = 22µH,

LBUCK-BOOST = 22µH

0mA

EH_ON

5V/DIV

BUCK

INDUCTOR

CURRENT

200mA/DIV

OUTPUT

VOLTAGE

50mV/DIV

DC-COUPLED,

OFFSET = 3.3V

BUCK-BOOST

INDUCTOR

CURRENT

200mA/DIV

3330 G33

100µs/DIV

0mA

VIN TRANSITIONS 18V TO 17V, UV[3:0] = 1110

BAT = 4.1V, VOUT = 3.3V

ILOAD = 50mA, COUT = 100µF, LBUCK = 22µH,

LBUCK-BOOST = 22µH

0mA

EH_ON

5V/DIV

BUCK

INDUCTOR

CURRENT

200mA/DIV

OUTPUT

VOLTAGE

50mV/DIV

DC-COUPLED,

OFFSET = 3.3V

BUCK-BOOST

INDUCTOR

CURRENT

200mA/DIV 0mA

3330 G30

100µs/DIV

ILOAD (A)

EFFICIENCY (%)

3330 G34

100

01µ 10µ 10m 100m1m100µ

1.8V

2.5V

3.3V

VIN = 6V, L = 22µH, DCR = 0.19Ω

VOUT SETTING

VIN (V)

EFFICIENCY (%)

3330 G35

100

75 4 6 108 12 14 16 18

1.8V

2.5V

2.8V

3.3V

3.6V

4.5V

DCR = 0.19Ω VOUT SETTING

VIN (V)

EFFICIENCY (%)

3330 G36

100

75 4 6 108 12 14 16 18

DCR = 0.45Ω

1.8V

2.5V

2.8V

3.3V

3.6V

4.5V

VOUT SETTING

LTC3330 1 O L7ELUEN2

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL PERFORMANCE CHARACTERISTICS

Buck-Boost Efficiency vs BAT for

VOUT = 1.8V, 250mA IPEAK Setting

Buck-Boost Efficiency vs BAT for

VOUT = 3.3V, 250mA IPEAK Setting

Buck-Boost Efficiency vs BAT for

VOUT = 5V, 250mA IPEAK Setting

Buck-Boost Efficiency vs BAT for

VOUT = 1.8V, 5mA IPEAK Setting

Buck-Boost Efficiency vs BAT for

VOUT = 3.3V, 5mA IPEAK Setting

Buck-Boost Efficiency vs BAT for

VOUT = 5V, 5mA IPEAK Setting

Buck Efficiency vs VIN, for

VOUT = 3.3V

Buck-Boost Efficiency vs ILOAD,

250mA IPEAK Setting

Buck-Boost Efficiency vs ILOAD,

5mA IPEAK Setting

TA = 25°C, unless otherwise noted.

BAT (V)

EFFICIENCY (%)

3330 G45

100

401.8 2.2 32.6 3.4 3.8 4.2 54.6

L = 1000µH, DCR = 5.1Ω

1mA

50µA

10µA

100µA

20µA

5µA

LOAD CURRENT

BAT (V)

EFFICIENCY (%)

3330 G44

100

401.8 2.2 32.6 3.4 3.8 4.2 54.6

L = 1000µH, DCR = 5.1Ω

1mA

50µA

10µA

100µA

20µA

5µA

LOAD CURRENT

BAT (V)

EFFICIENCY (%)

3330 G40

100

401.8 2.2 32.6 3.4 3.8 4.2 54.6

L = 22µH, DCR = 0.36Ω

50mA

50µA

10µA

100µA

20µA

5µA

LOAD CURRENT

BAT (V)

EFFICIENCY (%)

3330 G41

100

401.8 2.2 32.6 3.4 3.8 4.2 54.6

L = 22µH, DCR = 0.36Ω

50mA

50µA

10µA

100µA

20µA

5µA

LOAD CURRENT

BAT (V)

EFFICIENCY (%)

3330 G42

100

401.8 2.2 32.6 3.4 3.8 4.2 54.6

L = 22µH, DCR = 0.36Ω

50mA

50µA

10µA

100µA

20µA

5µA

LOAD CURRENT

VIN (V)

EFFICIENCY (%)

3330 G37

100

04 6 108 12 14 16 18

100mA

100µA

50µA

30µA

20µA

10µA

5µA

L = 22µH, DCR = 0.19Ω

LOAD CURRENT

BAT (V)

EFFICIENCY (%)

3330 G43

100

401.8 2.2 32.6 3.4 3.8 4.2 54.6

L = 1000µH, DCR = 5.1Ω

1mA

50µA

10µA

100µA

20µA

5µA

LOAD CURRENT

ILOAD (A)

EFFICIENCY (%)

3330 G38

100

01µ 10µ 10m1m100µ

BAT = 3.6V

L = 22µH

DCR = 0.36Ω

1.8V

2.5V

3.3V

VOUT SETTING

ILOAD (A)

EFFICIENCY (%)

3330 G39

100

01µ 10µ 1m100µ

BAT = 3.6V

L = 1000µH

DCR = 5.1Ω

1.8V

2.5V

3.3V

VOUT SETTING

LTC3330 L7 LJUW 1 1

LTC3330

3330fc

For more information www.linear.com/LTC3330

TYPICAL PERFORMANCE CHARACTERISTICS

LDO Load Regulation, 1.2V LDO Line Regulation, 1.2V

LDO Start-Up

LDO Load Regulation, 3.3V LDO Line Regulation, 3.3V

ILDO_IN vs LDO_IN

LDO_OUT vs Temperature,

LDO_OUT = 3.3V

LDO Load Step

LDO_IN (V)

1.5

ILDO_IN (nA)

900

800

700

600

500

400

300

200

100

02.5 3.5 4.5

3330 G46

5.5

125°C

85°C

25°C

–40°C

TA = 25°C, unless otherwise noted.

ILOAD (A)

LDO_OUT (V)

1.224

1.218

1.212

1.206

1.200

1.194

1.182

1.188

1.176

3330 G47

1µ 10µ 10m 100m1m100µ

LDO_IN = 5V

LDO_IN = 1.8V

LDO_IN (V)

1.8

LDO_OUT (V)

1.224

1.218

1.212

1.206

1.200

1.194

1.188

1.182

1.176 2.6 3 3.4 3.8 4.2 4.6

3330 G48

52.2

LOAD = 100µA

LOAD = 10mA

TEMPERATURE (°C)

–50

LDO_OUT (V)

3.36

3.34

3.32

3.30

3.28

3.24

3.26

0 25 50 75 100

3330 G49

125–25

LDO_IN = 3.6V, 100µA LOAD

ILOAD (A)

LDO_OUT (V)

3.36

3.34

3.32

3.30

3.26

3.28

3.24

3330 G50

1µ 10µ 10m 100m1m100µ

LDO_IN = 5V

LDO_IN = 3.6V

LDO_IN (V)

3.4

LDO_OUT (V)

3.36

3.34

3.32

3.30

3.28

3.26

3.24 3.8 4 4.2 4.4 4.6 4.8

3330 G51

53.6

LOAD = 100µA

LOAD = 10mA

LDO_IN = 5V, LDO[2:0] = 110

CLDO_OUT = 22µF

LDO_OUT

VOLTAGE

1V/DIV

LDO_EN

VOLTAGE

5V/DIV

3330 G52

2ms/DIV

LDO_IN = 5V, LDO_OUT = 3.3V

CLDO_OUT = 33µF

LOAD STEP BETWEEN 1mA AND 50mA

LDO_OUT

VOLTAGE

AC-COUPLED

20mV/DIV

LOAD

CURRENT

50mA/DIV

3330 G53

2ms/DIV

0mA

LTC3330 12

LTC3330

3330fc

For more information www.linear.com/LTC3330

PIN FUNCTIONS

BAL (Pin 1): Supercapacitor Balance Point. The common

node of a stack of two supercapacitors is connected to

BAL. A source/sink balancing current of up to 10mA is

available. Tie BAL along with SCAP to GND to disable the

balancer and its associated quiescent current.

SCAP (Pin 2): Supply and Input for Supercapacitor

Balancer. Tie the top of a 2-capacitor stack to SCAP and

the middle of the stack to BAL to activate balancing. Tie

SCAP along with BAL to GND to disable the balancer and

its associated quiescent current.

VIN2 (Pin 3): Internal Low Voltage Rail to Serve as Gate

Drive for Buck NMOS Switch. Connect a 4.7µF (or larger)

capacitor from VIN2 to GND. This pin is not intended for

use as an external system rail.

UV3, UV2, UV1, UV0 (Pins 4, 5, 6, 7): UVLO Select Bits

for the Buck Switching Regulator. Tie high to VIN2 or low to

GND to select the desired UVLO rising and falling thresholds

(see Table 4). The UVLO falling threshold must be greater

than the selected VOUT regulation level. Do not float.

AC1 (Pin 8): Input Connection for Piezoelectric Element,

Other AC Source, or current limited DC source (used in

conjunction with AC2 for differential AC inputs).

AC2 (Pin 9): Input Connection for Piezoelectric Element,

Other AC Source, or current limited DC source (used in

conjunction with AC1 for differential AC inputs).

ISCAP vs SCAP

Supercapacitor Balancer Source/

Sink Current

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

SCAP (V)

ISCAP (nA)

250

200

150

100

03 4 4.5 53.5

3330 G55

5.52.5

85°C

125°C

25°C

–40°C

VBAL/VSCAP (%)

BALANCER SOURCE/SINK CURRENT (mA)

–10

–20 20 30 50 60 70 80 9040

3330 G56

10010

SCAP = 5V

SCAP = 2.5V

VIN (Pin 10): Rectified Input Voltage. A capacitor on this

pin serves as an energy reservoir and input supply for the

buck regulator. The VIN voltage is internally clamped to a

maximum of 20V (typical).

CAP (Pin 11): Internal Rail Referenced to VIN to Serve

as Gate Drive for Buck PMOS Switch. Connect a 1μF (or

larger) capacitor between CAP and VIN. This pin is not

intended for use as an external system rail.

SW (Pin 12): Switch Node for the Buck Switching Regula-

tor. Connect a 22µH or greater external inductor between

this node and VOUT.

VOUT (Pin 13): Regulated Output Voltage Derived from the

Buck or Buck-Boost Switching Regulator.

SWB (Pin 14): Switch Node for the Buck-Boost Switching

Regulator. Connect an external inductor (value in Table 3)

between this node and SWA.

SWA (Pin 15): Switch Node for the Buck-Boost Switching

Regulator. Connect an external inductor (value in Table 3)

between this node and SWB.

BAT (Pin 16): Battery Input. BAT serves as the input to

the buck-boost switching regulator.

RDS(ON) of LDO PMOS vs

Temperature

TEMPERATURE (°C)

–50

RDS(ON) (Ω)

0 25 50 75 100

3330 G54

125–25

LDO_IN = 1.8V

LDO_IN = 2.5V LDO_IN = 3.3V

LDO_IN = 5V

LTC3330 L7HEJWEGR 1 3

LTC3330

3330fc

For more information www.linear.com/LTC3330

IPK0, IPK1, IPK2 (Pins 17, 18, 19): IPEAK_BB Select Bits

for the Buck-Boost Switching Regulator. Tie high to VIN3

or low to GND to select the desired IPEAK_BB (see Table 3).

Do not float.

LDO_OUT (Pin 20): Regulated LDO Output. This output

can be used as a quiet supply. One of the eight settings

provides for a current limited switched output where

LDO_OUT = LDO_IN.

LDO_IN (Pin 21): Input Voltage for the LDO regulator.

LDO2, LDO1, LDO0 (Pins 22, 23, 24): LDO Voltage Select

Bits. Tie high to LDO_IN or low to GND to select the desired

LDO_OUT voltage (see Table 2). Do not float.

LDO_EN (Pin 25): LDO Enable Input. Active high input with

logic levels referenced to LDO_IN. Do not float.

VIN3 (Pin 26): Internal Low Voltage Rail Used by the

Prioritizer. Logic high reference for IPK[2:0] and OUT[2:0].

Connect a 1µF (or larger) capacitor from VIN3 to GND.

This pin is not intended for use as an external system rail.

PGLDO (Pin 27): Power Good Output for LDO_OUT. Logic

level output referenced to an internal maximum rail (see

Operation). PGLDO transitioning high indicates 92% (typi-

cal) regulation has been reached on LDO_OUT. PGLDO

remains high until LDO_OUT falls to 90% (typical) of the

programmed regulation point.

PIN FUNCTIONS

PGVOUT (Pin 28): Power Good Output for VOUT. Logic

level output referenced to an internal maximum rail (see

Operation). PGVOUT transitioning high indicates regula-

tion has been reached on VOUT (VOUT = Sleep Rising).

PGVOUT remains high until VOUT falls to 92% (typical)

of the programmed regulation point.

EH_ON (Pin 29): Switcher Status. Logic level output ref-

erenced to VIN3. EH_ON is high when the buck switching

regulator is in use. It is pulled low when the buck-boost

switching regulator is in use.

OUT0, OUT1, OUT2 (Pins 30, 31,

32): VOUT Voltage Select

Bits. Tie high to VIN3 or low to GND to select the desired

VOUT (see Table 1). Do not float.

GND (Exposed Pad Pin 33): Ground. The exposed pad

must be connected to a continuous ground plane on the

second layer of the printed circuit board by several vias

directly under the LTC3330.

LTc3330

LTC3330

3330fc

For more information www.linear.com/LTC3330

BLOCK DIAGRAM

3330 BD

BANDGAP

REFERENCE

INTERNAL

RAIL

GENERATION

PRIORITIZER

UVLO

UVLO_SET

SLEEP

VIN

VREF

AC1

20V

AC2

BAT

EH_ON

SLEEP

ILIM_SET

VREF

VIN2

VIN3

VMAX

BAT VOUT

PGVOUT

PGLDO

–

SLEEP

0.9*VREF

VREF

–

0.925*VREF

VIN2 LDO_INVIN3

VIN3

CAP 11

VIN2

GND 33

SWA

SWB

LDO_IN

VOUT

LDO_OUT

SCAP

BAL

VIN3

BUCK-BOOST

CONTROL

ILIM_SETUVLO_SET

3 3

32, 31, 30 22, 23, 24

4, 5, 6, 7 UV[3:0]

19, 18, 17 IPK[2:0] OUT[2:0] LDO[2:0]

BUCK

CONTROL

LDO_EN 25

–

LTC3330 IPEAKJB L7HEJWEGR 1 5

LTC3330

3330fc

For more information www.linear.com/LTC3330

OPERATION

Modes of Operation

The following four tables detail all programmable settings

on the LTC3330.

Table 1. Output Voltage Selection

OUT2 OUT1 OUT0 VOUT

0 0 0 1.8V

0 0 1 2.5V

0 1 0 2.8V

0 1 1 3.0V

1 0 0 3.3V

1 0 1 3.6V

1 1 0 4.5V

1 1 1 5.0V

Table 2. LDO Voltage Selection

LDO2 LDO1 LDO0 LDO_OUT

0 0 0 1.2V

0 0 1 1.5V

0 1 0 1.8V

0 1 1 2.0V

1 0 0 2.5V

1 0 1 3.0V

1 1 0 3.3V

1 1 1 = LDO_IN

Table 3. IPEAK_BB Selection

IPK2 IPK1 IPK0 ILIM LMIN

0 0 0 5mA 1000µH

0 0 1 10mA 470µH

0 1 0 15mA 330µH

0 1 1 25mA 220µH

1 0 0 50mA 100µH

1 0 1 100mA 47µH

1 1 0 150mA 33µH

1 1 1 250mA 22µH

Table 4. VIN UVLO Threshold Selection

UV3 UV2 UV1 UV0

UVLO

RISING

UVLO

FALLING

0 0 0 0 4V 3V

0 0 0 1 5V 4V

0 0 1 0 6V 5V

0 0 1 1 7V 6V

0 1 0 0 8V 7V

0 1 0 1 8V 5V

0 1 1 0 10V 9V

0 1 1 1 10V 5V

1 0 0 0 12V 11V

1 0 0 1 12V 5V

1 0 1 0 14V 13V

1 0 1 1 14V 5V

1 1 0 0 16V 15V

1 1 0 1 16V 5V

1 1 1 0 18V 17V

1 1 1 1 18V 5V

LTc3330 VOLTAGE (V)

LTC3330

3330fc

For more information www.linear.com/LTC3330

OVERVIEW

The LTC3330 combines a buck switching regulator and

a buck-boost switching regulator to produce an energy

harvesting solution with battery backup. The converters are

controlled by a prioritizer that selects which converter to

use based on the availability of a battery and/or harvestable

energy. If harvested energy is available the buck regula-

tor is active and the buck-boost is OFF. With an optional

LDO and supercapacitor balancer and an array of different

configurations the LTC3330 suits many applications.

BUCK CONVERTER

The synchronous buck converter is an ultralow quiescent

current power supply tailored to energy harvesting applica-

tions. It is designed to interface directly to a piezoelectric

or alternative A/C power source, rectify the input voltage,

and store harvested energy on an external capacitor while

maintaining a regulated output voltage. It can also bleed

off any excess input power via an internal protective shunt

regulator.

INTERNAL BRIDGE RECTIFIER

An internal full-wave bridge rectifier accessible via the dif-

ferential AC1 and AC2 inputs rectifies AC sources such as

those from a piezoelectric element. The rectified output is

stored on a capacitor at the VIN pin and can be used as an

energy reservoir for the buck converter. The bridge rectifier

has a total drop of about 800mV at typical piezo-generated

currents (~10μA), but is capable of carrying up to 50mA.

Either side of the bridge can be operated independently

as a single-ended AC or DC input.

BUCK UNDERVOLTAGE LOCKOUT (UVLO)

When the voltage on VIN rises above the UVLO rising

threshold the buck converter is enabled and charge is

transferred from the input capacitor to the output capacitor.

When the input capacitor voltage is depleted below the

UVLO falling threshold the buck converter is disabled.

These thresholds can be set according to Table 4 which

offers UVLO rising thresholds from 4V to 18V with large

or small hysteresis windows. This allows for program-

ming of the UVLO window near the peak power point of

OPERATION

Figure 1. Ideal VIN, VIN2 and CAP Relationship

the input source. Extremely low quiescent current (450nA

typical) in UVLO allows energy to accumulate on the input

capacitor in situations where energy must be harvested

from low power sources.

INTERNAL RAIL GENERATION (CAP, VIN2, VIN3)

Two internal rails, CAP and VIN2, are generated from VIN

and are used to drive the high side PMOS and low side

NMOS of the buck converter, respectively. Additionally the

VIN2 rail serves as logic high for the UVLO threshold select

bits UV[3:0]. The VIN2 rail is regulated at 4.8V above GND

while the CAP rail is regulated at 4.8V below VIN. These are

not intended to be used as external rails. Bypass capaci-

tors are connected to the CAP and VIN2 pins to serve as

energy reservoirs for driving the buck switches. When VIN

is below 4.8V, VIN2 is equal to VIN and CAP is held at GND.

Figure 1 shows the ideal VIN, VIN2 and CAP relationship.

VIN (V)

VOLTAGE (V)

0105

3330 F01

VIN

VIN2

CAP

VIN3 is an internal rail used by the buck and the buck-boost.

When the LTC3330 runs the buck VIN3 will be a Schottky

diode drop below VIN2. When it runs the buck-boost VIN3

is equal to BAT.

BUCK OPERATION

The buck regulator uses a hysteretic voltage algorithm

to control the output through internal feedback from the

VOUT sense pin. The buck converter charges an output

capacitor through an inductor to a value slightly higher

than the regulation point. It does this by ramping the

inductor current up to IPEAK_BUCK through an internal

LTC3330 L7HEJWEGR 1 7

LTC3330

3330fc

For more information www.linear.com/LTC3330

OPERATION

PMOS switch and then ramping it down to 0mA through

an internal NMOS switch. This efficiently delivers energy

to the output capacitor. The ramp rate is determined by

VIN, VOUT, and the inductor value. When the buck brings

the output voltage into regulation the converter enters a

low quiescent current sleep state that monitors the output

voltage with a sleep comparator. During this operating

mode load current is provided by the output capacitor.

When the output voltage falls below the regulation point

the buck regulator wakes up and the cycle repeats. This

hysteretic method of providing a regulated output reduces

losses associated with FET switching and maintains an

output at light loads. The buck delivers a minimum of

100mA of average load current when it is switching. VOUT

can be set from 1.8V to 5V via the output voltage select

bits, OUT[2:0] (see Table 1).

When the sleep comparator senses that the output has

reached the sleep threshold the buck converter may be in

the middle of a cycle with current still flowing through the

inductor. Normally both synchronous switches would turn

off and the current in the inductor would freewheel to zero

through the NMOS body diode, but the NMOS switch is

kept on to prevent the conduction loss that would occur in

the diode if the NMOS were off. If the PMOS is on when the

sleep comparator trips the NMOS will turn on immediately

in order to ramp down the current. If the NMOS is on it

will be kept on until the current reaches zero.

Though the quiescent current when the buck is switching

is much greater than the sleep quiescent current, it is still

a small percentage of the average inductor current which

results in high efficiency over most load conditions. The

buck operates only when sufficient energy has been ac-

cumulated in the input capacitor and the length of time the

converter needs to transfer energy to the output is much

less than the time it takes to accumulate energy. Thus, the

buck operating quiescent current is averaged over a long

period of time so that the total average quiescent current

is low. This feature accommodates sources that harvest

small amounts of ambient energy.

BUCK-BOOST CONVERTER

The buck-boost uses the same hysteretic voltage algorithm

as the buck to control the output, VOUT, with the same

sleep comparator. The buck-boost has three modes of

operation: buck, buck-boost, and boost. An internal mode

comparator determines the mode of operation based on

BAT and VOUT. Figure 2 shows the four internal switches

of the buck-boost converter. In each mode the inductor

current is ramped up to IPEAK_BB, which is programmable

via the IPK[2:0] bits and ranges from 5mA to 250mA (see

Table 3).

In BUCK mode M4 is always on and M3 is always off. The

inductor current is ramped up through M1 to IPEAK_BB and

down to 0mA through M2. In boost mode M1 is always

on and M2 is always off. The inductor current is ramped

up to IPEAK_BB when M3 is on and is ramped down to

0mA when M4 is on as VOUT is greater than BAT in boost

mode. Buck-boost mode is very similar to boost mode in

that M1 is always on and M2 is always off. If BAT is less

than VOUT the inductor current is ramped up to IPEAK_BB

through M3. When M4 turns on the current in the inductor

will start to ramp down. However, because BAT is close to

VOUT and M1 and M4 have finite on-resistance the current

ramp will exhibit a slow exponential decay, lowering the

average current delivered to VOUT. For this reason the

lower current threshold is set to IPEAK_BB/2 in buck-boost

mode to maintain high average current to the load. If BAT

is greater than VOUT in buck-boost mode the inductor cur-

rent still ramps up to IPEAK_BB and down to IPEAK_BB/2. It

can still ramp down if BAT is greater than VOUT because

the final value of the current in the inductor would be

(VIN – VOUT)/ (RON1 + RON4). If BAT is exactly IPEAK_BB/

2•(RON1 + RON4) above VOUT the inductor current will

Figure 2: Buck-Boost Power Switches

3330 F02

SWA SWB

BAT

M4 VOUT

M3M2

LTc3330

LTC3330

3330fc

For more information www.linear.com/LTC3330

not reach the IPEAK_BB/2 threshold and switches M1 and

M4 will stay on all the time. For higher BAT voltages the

mode comparator will switch the converter to buck mode.

M1 and M4 will remain on for BAT voltages up to VOUT +

IPEAK_BB•(RON1 + RON4). At this point the current in the

inductor is equal to IPEAK_BB and the IPEAK_BB compara-

tor will trip turning off M1 and turning on M2 causing the

inductor current to ramp down to IZERO, completing the

transition from buck-boost mode to buck mode.

VOUT Power Good

A power good comparator is provided for the VOUT output.

It transitions high the first time the LTC3330 goes to sleep,

indicating that VOUT has reached regulation. It transitions

low when VOUT falls to 92% (typical) of its value at regula-

tion. The PGVOUT output is referenced to an internal rail

that is generated to be the highest of VIN2, BAT, and VOUT

less a Schottky diode drop.

Prioritizer

The input prioritizer on the LTC3330 decides whether to use

the energy harvesting input or the battery input to power

VOUT. If a battery is powering the buck-boost converter

and harvested energy causes a UVLO rising transition on

VIN, the prioritizer will shut off the buck-boost and turn on

the buck, orchestrating a smooth transition that maintains

regulation of VOUT. When harvestable energy disappears,

the prioritizer will first poll the battery voltage. If the battery

voltage is above 1.8V the prioritizer will switch back to

the buck-boost while maintaining regulation. If the battery

voltage is below 1.8V the buck-boost is not enabled and

VOUT cannot be supported until harvestable energy is again

available. If either BAT or VIN is grounded, the prioritizer

allows the other input to run if its input is high enough for

operation. The specified quiescent current in UVLO is valid

upon start-up of the VIN input and when the battery has

taken over regulation of the output. If the battery is less

than 1.8V when UVLO is entered and the prioritizer does

not enable the buck-boost several hundred nanoamperes

of additional quiescent current will appear on VIN.

When the prioritizer selects the VIN input the current on

the BAT input drops to zero. However, if the voltage on

BAT is higher than VIN2, a fraction of the VIN quiescent

current will appear on BAT due to internal level shifting.

This only affects a small range of battery voltages and

UVLO settings.

A digital output, EH_ON, is low when the prioritizer has

selected the BAT input and is high when the prioritizer has

selected the VIN input. The EH_ON output is referenced

to VIN3.

Low Drop Out Regulator

An integrated low drop out regulator (LDO) is available with

its own input, LDO_IN. It will regulate LDO_OUT to seven

different output voltages based on the LDO[2:0] pins. An

eighth mode is provided to turn the LDO into a current-

limited switch in which the PMOS is always on. LDO_EN

enables the LDO when high and when low eliminates all

quiescent current on LDO_IN. The LDO is designed to

provide 50mA over a range of LDO_IN and LDO_OUT

combinations. A current limit set above 50mA is available

to dial back the current if the output is grounded or the

load demands more than 50mA. The LDO also features a

1ms soft-start for smooth output start-up.

A power good signal on the PGLDO pin indicates when

the voltage at LDO_OUT rises above 92% (typical) of its

final value, or after tripped, when the LDO_OUT falls below

90% of that value. The PGLDO output is referenced to an

internal rail that is generated to be the highest of VIN2,

BAT, and VOUT less a Schottky diode drop.

Supercapacitor Balancer

An integrated supercapacitor balancer with 150nA of

quiescent current is available to balance a stack of two

supercapacitors. Typically the input, SCAP, will tie to

VOUT to allow for increased energy storage at VOUT with

supercapacitors. The BAL pin is tied to the middle of the

stack and can source and sink 10mA to regulate the BAL

pin’s voltage to half that of the SCAP pin’s voltage. To

disable the balancer and its associated quiescent current

the SCAP and BAL pins can be tied to ground.

OPERATION

LTC3330 L7HEJWEGR 1 9

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

The LTC3330 allows for energy harvesting from a variety

of alternative energy sources in order to extend the life of

a battery powered wireless sensor system. The extremely

low quiescent current of the LTC3330 facilitates harvesting

from sources generating only microamps of current. The

onboard bridge rectifier is suitable for AC piezoelectric

or electromagnetic sources as well as providing reverse

protection for DC sources such as solar and thermoelectric

generators. The LTC3330 powers the VOUT output con-

tinuously by seamlessly switching between the energy

harvesting and battery inputs.

When harvestable energy is available, it is transferred

through the bridge rectifier where it accumulates on the

VIN capacitor. A low quiescent current UVLO mode allows

the voltage on the capacitor to increase towards a pro-

grammed UVLO rising threshold. When the voltage rises

to this level, the buck converter turns on and transfers

energy to VOUT. As energy is transferred the voltage at

VIN may decrease to the UVLO falling threshold. If this

happens, the buck converter turns off and the buck-boost

then turns on to service the load from the battery input

while more energy is harvested. When the buck is running

the quiescent current on the BAT pin is essentially zero.

The LTC3330 is well suited to wireless systems which

consume low average power but occasionally need a

higher concentrated burst of power to accomplish a task. If

these bursts occur with a low duty cycle such that the total

energy needed for a burst can be accumulated between

bursts then the output can be maintained entirely by the

harvester. If the bursts need to happen more frequently or

if harvestable energy goes away the battery will be used.

Piezo Energy Harvesting

Ambient vibrational energy can be harvested with a

piezoelectric transducer which produces a voltage and

current in response to strain. Common piezoelectric ele-

ments are PZT (lead zirconate titanate) ceramics, PVDF

(polyvinylidene fluoride) polymers, or other composites.

Ceramic piezoelectric elements exhibit a piezoelectric effect

when the crystal structure of the ceramic is compressed

and internal dipole movement produces a voltage. Polymer

elements comprised of long-chain molecules produce a

voltage when flexed as molecules repel each other. Ceram-

ics are often used under direct pressure while a polymer

is commonly used as a cantilevered beam.

A wide range of piezoelectric elements are available and

produce a variety of open-circuit voltages and short-circuit

currents. Typically the open-circuit voltage and short-circuit

currents increase with available vibrational energy as shown

in Figure 3. Piezoelectric elements can be placed in series

or in parallel to achieve desired open-circuit voltages.

Piezos produce the most power when they operate at

approximately half the open circuit voltage for a given

vibration level. The UVLO window can be programmed to

straddle this voltage so that the piezo operates near the

peak power point. In addition to the normal configuration

of connecting the piezo across the AC1 and AC2 inputs, a

piezo can be connected from either AC1 or AC2 to ground.

The resulting configuration is a voltage doubler as seen

in Figure 4 where the intrinsic capacitance of the piezo is

used as the doubling capacitor.

Figure 3. Typical Piezoelectric Load Lines for Piezo Systems

T220-A4-503X

PIEZO CURRENT (µA)

PIEZO VOLTAGE (V)

02010

3330 F03

INCREASING

VIBRATION ENERGY

LTC3330 4‘? I J:\ I I I I I I z’l/é/ l I A I I\ [I / l I ’ .l 1 [I // m : \E\' \- I 20 L7ELUEN2

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

A second piezo may be connected from AC2 to ground. This

may be of use if the second piezo is mechanically tuned to

a different resonant frequency present in the system than

the first piezo. Of the two piezos the one operating at the

higher open circuit voltage will win over the other piezo

and its doubled voltage will appear on the VIN capacitor.

To achieve maximum power transfer from the piezo with

the doubler the UVLO window should be set to the open

circuit voltage of the piezo.

Piezoelectric elements are available from the manufactur-

ers listed in Table 5.

Table 5. Piezoelectric Element Manufacturers

Advanced Cerametrics www.advancedcerametrics.com

Piezo Systems www.piezo.com

Measurement Specialties www.meas-spec.com

PI (Physik Instrumente) www.pi-usa.us

MIDE Technology Corporation www.mide.com

Morgan Technical Ceramics www.morganelectroceramics.com

Electromagnetic Energy Harvesting

Another alternative AC source is an electromagnetic vibra-

tion harvester in which a magnet vibrating inside a coil

induces an AC voltage and current in the coil that can then

be rectified and harvested by the LTC3330. The vibration

could be ambient to the system or it could be caused by

an impulse as in a spring loaded switch.

Solar Energy Harvesting

The LTC3330 can harvest solar energy as the bridge recti-

fier can be used to provide reverse protection for a solar

panel. A solar cell produces current in proportion to the

amount of light falling on it. Figure 5 shows the relationship

between current and voltage for a solar panel illuminated

with several levels of light. The maximum power output

occurs near the knee of each curve where the cell transi-

tions from a constant current device to a constant voltage

device. Fortunately, the peak power point doesn’t change

much with illumination and an appropriate UVLO window

can be selected so that the panel operates near the peak

power point for a majority of light conditions.

GND

LTC3330

PIEZO MODEL

VIN

CIN

AC1

3330 F04

IP sin(wt) CP

Figure 4. LTC3330 Voltage Doubler Configuration

Two solar panels can be connected to the LTC3330, one

from AC1 to ground and another from AC2 to ground. Each

panel could be aimed in a different direction to capture light

from different angles or at different times of the day as the

sun moves. The panels should be similar or the same so

that the selected UVLO window is optimal for both panels.

BAT , VIN, and VOUT Capacitors

The input capacitor for the buck-boost on the BAT pin should

be bypassed with at least 4.7µF to GND. In cases where the

series resistance of the battery is high, a larger capacitor

may be desired to handle transients. A larger capacitor may

also be necessary when operating close to 1.8V with the

higher IPEAK_BB selections to prevent the battery voltage

from falling below 1.8V when the buck-boost is switching.

The input capacitor to the buck on VIN and the VOUT

capacitor can vary widely and should be selected to op-

timize the use of an energy harvesting source depending

Figure 5. Typical Solar Panel Characteristics

VPANEL (V)

IPANEL (µA)

WPANEL (µW)

500

400

300

200

100

1500

1200

900

600

300

2 3 4 5

3330 F05

SANYO 1815 SOLAR PANEL

1800 LUX

500 LUX

200 LUX

1000 LUX

PANEL VOLTAGE

PANEL POWER

LTC3330 tLOAD + , 1 VUVLOFALLING VIN VSHUNT E V‘N 1 VIN VDC HYS L7 LJUW 2 1

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

on whether storage of the harvested energy is needed at

the input or the output. Storing energy at the input takes

advantage of the high input voltage as the energy stored

in a capacitor increases with the square of its voltage.

Storage at the output may be necessary to handle load

transients greater than the 100mA the buck can provide.

The input or output capacitor should be sized to store

enough energy to provide output power for the length

of time required. If enough energy is stored so that the

buck does not reach the UVLO falling threshold during

a load transient then the battery current will always be

zero. Spacing load transients so that the average power

required to service the application is less than or equal

to the power available from the energy harvesting source

will then greatly extend the life of the battery. The VIN

capacitor should be rated to withstand the highest voltage

ever present at VIN.

The following equation can be used to size the input

capacitor to meet the power requirements of the output

for the desired duration:

PLOAD tLOAD =

2ηCIN VIN2– VUVLOFALLING2

( )

UVLOFALLING

≤ V

SHUNT

Here η is the average efficiency of the buck converter over

the input voltage range and VIN is the input voltage when

the buck begins to switch. Typically VIN will be the UVLO

rising threshold. This equation may overestimate the input

capacitor necessary as it may be acceptable to allow the

load current to deplete the output capacitor all the way to

the lower PGVOUT threshold. It also assumes that the input

source charging has a negligible effect during this time.

The duration for which the buck or buck-boost regulator

sleeps depends on the load current and the size of the VOUT

capacitor. The sleep time decreases as the load current

increases and/or as the output capacitor decreases. The

DC sleep hysteresis window is ±6mV for the 1.8V output

and scales linearly with the output voltage setting (±12mV

for the 3.6V setting, etc.). Ideally this means that the sleep

time is determined by the following equation:

tSLEEP =COUT

DC_HYS

LOAD

This is true for output capacitors on the order of 100μF

or larger, but as the output capacitor decreases towards

10μF, delays in the internal sleep comparator along with

the load current itself may result in the VOUT voltage slew-

ing past the DC thresholds. This will lengthen the sleep

time and increase VOUT ripple. A capacitor less than 10μF

is not recommended as VOUT ripple could increase to an

undesirable level. If transient load currents above 100mA

are required then a larger capacitor should be used at the

output. This capacitor will be continuously discharged

during a load condition and the capacitor can be sized for

an acceptable drop in VOUT:

COUT = ILOAD – IDC/DC

( )

LOAD

OUT

+ – V

OUT

–

Here VOUT+ is the value of VOUT when PGVOUT goes high

and VOUT– is the desired lower limit of VOUT. IDC/DC is

the average current being delivered from either the buck

converter or the buck-boost converter. The buck converter

typically delivers 125mA on average to the output as the

inductor current is ramped up to 250mA and down to

zero. The current the buck-boost delivers depends on the

mode of operation and the IPEAK_BB setting. In buck mode

the deliverable current is IPEAK_BB/2. In buck-boost and

boost modes the deliverable current also depends on the

VIN to VOUT ratio:

Buck-boost mode:

DC/DC =

4IPEAK_BB

OUT

Boost mode:

DC/DC =

2IPEAK_BB

OUT

A standard surface mount ceramic capacitor can be used

for COUT, though some applications may be better suited

to a low leakage aluminum electrolytic capacitor or a

supercapacitor. These capacitors can be obtained from

manufacturers such as Vishay, Illinois Capacitor, AVX,

or CAP-XX.

LTC3330 d 43 @ ||||.,:llllll| a m w 22 L7ELUEN2

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

Supercapacitor Balancer

If supercapacitors are used at VOUT the onboard

supercapacitor balancer can be used to balance them

with ±10mA of balance current. A list of supercapacitor

suppliers is provided in Table 6.

Table 6. Supercapacitor Suppliers

CAP-XX www.cap-xx.com

NESS CAP www.nesscap.com

Maxwell www.maxwell.com

Bussman www.cooperbussman.com

AVX www.avx.com

Illinios Capacitor www.illcap.com

Tecate Group www.tecategroup.com

By seamlessly combining a battery source and an en-

ergy harvesting source, the LTC3330 enables the use of

supercapacitors in energy harvesting applications. The

battery provides the initial current required to overcome

the effects of the diffusion current when voltage is first

applied to the supercapacitors. The energy harvesting

source can then support the lower steady state leakage

current and average load current.

LDO Capacitors

The input to the low dropout regulator, LDO_IN, should

be bypassed with at least 4.7µF to GND. If LDO_IN is con-

nected to VOUT the VOUT capacitor may adequately bypass

the LDO input. If the board connection between LDO_IN

and VOUT is long then an additional 1µF bypass capacitor

to GND near the LDO_IN pin may be required.

The LDO_OUT capacitor should be at least 22µF to keep

load step responses within 2% of regulation. A smaller

capacitor may lead to worse transient response and/or

instability whereas a higher capacitor will improve tran-

sient response.

CAP, VIN2, and VIN3 Capacitors

A 1μF or larger capacitor must be connected between VIN

and CAP and a 4.7μF capacitor must be connected between

VIN2 and GND. These capacitors hold up the internal rails

during buck switching and compensate the internal rail

generation circuits. In applications where the voltage at VIN

is limited to less than 6V, the CAP pin can be tied to GND

and the VIN2 pin can be tied to VIN as shown in Figure 6.

An optional 5.6V Zener diode can be connected to VIN

to clamp VIN in this scenario. The leakage of the Zener

diode below its clamping voltage should be considered

as it could be comparable to the quiescent current of the

LTC3330. This circuit does not require the capacitors on

VIN2 and CAP, saving two components and allowing for a

lower voltage rating for the single VIN capacitor.

A 1µF or larger bypass capacitor must be connected from

VIN3 to ground. VIN3 is an internal rail that is shared by

both the buck and buck-boost. It is not intended for use as

a system rail. It is used as a the logic high reference level

for the IPK[2:0] and OUT[2:0] digital inputs. In the event

that these pins are dynamically driven in the application,

external inverters may be needed and they must use VIN3

as a rail. However, care must be taken not to overload

VIN3 and the quiescent current of such logic should be

kept minimal. The output resistance of the VIN3 pin is

typically 15kΩ.

Figure 6. Low Voltage Solar Harvester with Reduced

Component Count (VIN < 6V)

LTC3330

3330 F06

AC1

VIN

CAP

VIN2

AC2

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

22µH

1.8V

VIN3

1µF

6.3V

33µH

Li-ION

UVLOR = 4V

UVLOF = 3V

IPEAK_BB = 150mA

22µF

6.3V

5.6V

(OPTIONAL)

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

SWA

SWB

GND

22µF

6.3V

SOLAR

PANEL

–

SOLAR

PANEL

–

4.7µF

6.3V

LTC3330 L7HEJWEGR 23

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

Inductor Selection

The buck is optimized to work with a 22µH inductor in

typical applications. A larger inductor will benefit high

voltage applications by increasing the on-time of the PMOS

switch and improving efficiency by reducing gate charge

loss. Choose an inductor with a DC current rating greater

than 350mA. The DCR of the inductor can have an impact

on efficiency as it is a source of loss. Tradeoffs between

price, size, and DCR should be evaluated.

The buck-boost is optimized to work with a minimum induc-

tor of 22μH for the 250mA IPEAK_BB setting. For the other

seven IPEAK_BB settings the inductor value should increase

as the IPEAK_BB selection decreases to maintain the same

IPEAK_BB • L product. The minimum inductor values for the

buck-boost for each IPEAK_BB setting are listed in Table 3.

Larger inductors may increase efficiency. Choose an

inductor with an ISAT rating at least 50% greater than the

selected IPEAK value. Table 7 lists several inductors that

work well with both the buck and the buck-boost.

Table 7. Recommended Inductors for the LTC3330

PART NUMBER L(µH) MANUFACTURER SIZE (mm) (L × W × H) MAX IDC

(mA)

MAX DCR

(Ω)

744043102

LPS5030-105ML

LPS4018-105ML

LPS3314-105ML

B82442T1105K050

1000 Würth Electronic

Coilcraft

EPCOS

4.8 × 4.8 × 2.8

5.51 × 5.51 × 2.9

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

5.6 × 5 × 5

110

150

5.1

9.5

744043471

LPS4018-474ML

LPS3314-474ML

B82442T147K050

470 Würth Electronic

Coilcraft

EPCOS

4.8 × 4.8 × 2.8

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

5.6 × 5 × 5

125

160

110

240

2.6

7.8

4.73

744042331

LPS4018-334ML

LPS3314-334ML

B82442T1334K050

330 Würth Electronic

Coilcraft

EPCOS

4.8 × 4.8 × 1.8

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

5.6 × 5 × 5

130

190

110

280

4.5

5.9

9.3

3.29

744042221

LPS4018-224ML

LPS3314-224ML

B82442T1224K050

220 Würth Electronic

Coilcraft

EPCOS

4.8 × 4.8 × 1.8

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

5.6 × 5 × 5

160

260

160

330

3.2

3.7

2.2

744031101

LPS4018-104ML

LPS3314-104ML

B82442T1104K050

100 Würth Electronic

Coilcraft

EPCOS

3.8 × 3.8 × 1.65

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

5.6 × 5 × 5

180

360

230

510

2.4

1.4

2.75

0.99

744031470

LPS4018-473ML

LPS3314-473ML

B82442T1473K050

47 Würth Electronic

Coilcraft

EPCOS

3.8 × 3.8 × 1.65

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

5.6 × 5 × 5

250

550

330

700

0.65

1.4

0.519

744031330

LPS4018-333ML

LPS3314-333ML

1070BS-330ML

B82442T1333K050

33 Würth Electronic

Coilcraft

Toko

EPCOS

3.8 × 3.8 × 1.65

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

3.2 × 3.2 × 2

5.6 × 5 × 5

320

640

380

230

840

0.66

0.42

0.92

0.61

0.36

744031220

LPS5030-223ML

LPS4018-223ML

LPS3314-223ML

1070AS-220M

B82442T1223K050

22 Würth Electronic

Coilcraft

Toko

EPCOS

3.8 × 3.8 × 1.65

5.51 × 5.51 × 2.9

3.9 × 3.9 × 1.7

3.3 × 3.3 × 1.3

3.2 × 3.2 × 2

5.6 × 5 × 5

360

750

800

450

410

1040

0.45

0.19

0.36

0.72

0.64

0.238

744029220

1069BS-220M

22 Würth Electronic

Toko

2.8 × 2.8 × 1.35

3.2 × 3.2 × 1.8

300

290

0.97

0.495

LTc3330 ﬂaw "1'3 T ”J |_l_...+l—| j :I: .||—| '— .||— III | _| -—H- || || -I|-‘

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

Summary of Digital Inputs and Outputs

There are 14 digital pin-strapped logic inputs to the

LTC3330 and three digital logic outputs. These and the

rails they are referenced to are summarized in Table 8.

Table 8. Digital Pin Summary

INPUT PIN LOGIC HIGH LEVEL

UV[3:0] VIN2

IPK[2:0] VIN3

OUT[2:0] VIN3

LDO[2:0] LDO_IN

LDO_EN LDO_IN up to 6V

OUTPUT PIN LOGIC HIGH LEVEL

PGVOUT MAX (BAT, VIN2, VOUT)

PGLDO MAX (BAT, VIN2, VOUT)

EH_ON VIN3

LTC3330 System Solutions

The LTC3330 can be paired with other Linear Technology low

quiescent current integrated circuits to form a multirail sys-

tem. Figure 7 shows an LTC3330 powering an LTC3388-3

from its 5V output. The LTC3388-3, an 800nA Buck

converter, is configured here to produce a negative 5V

rail by tying the VOUT pin to ground and tying its GND pin

to the regulated –5V output. The result is a ±5V energy

harvesting power supply with battery backup.

Figure 7. Dual ±5V Power Supply with a 3.3V LDO Output

LTC3330

3330 F07

AC1

VIN

CAP

VIN2

AC2

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

22µH

VIN3

1µF

6.3V

22µH

Li-ION

UVLOR = 12V**

UVLOF = 11V

IPEAK_BB = 250mA

22µF

25V 1µF, 6.3V

4.7µF, 6.3V

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

SWA

SWB

GND

22µF

6.3V

3.3V *EXPOSED PAD MUST BE ELECTRICALLY ISOLATED FROM

SYSTEM GROUND AND CONNECTED TO THE –5V RAIL

**FOR PEAK POWER TRANSFER, CENTER THE UVLO WINDOW

AT HALF THE RECTIFIED OPEN CIRCUIT VOLTAGE OF THE PIEZO

4.7µF

6.3V

MIDE V25W

VIN PGOOD

CAP

VIN2 SW

EN VOUT

LTC3388-3*

GND

D0 STBY

4.7µF

6.3V

1µF, 6.3V

22µF

6.3V

–5V

2.2µF

10V

22µF

6.3V

22µH

LTC3330 I—IDI—| l|—_||_. J_—' _|_ IIH '_ | | -.|._| '—I 1’“ .u 1: L7 LJUW 25

LTC3330

3330fc

For more information www.linear.com/LTC3330

When paired with the 550nA LTC4071 shunt battery charger

with low battery disconnect the LTC3330 can charge a bat-

tery from an energy harvesting source as shown in Figure 8.

A battery is connected to the BAT pin of the LTC4071. If

the battery voltage drops below a selected level the battery

will be disconnected and protected from further discharge.

A charging resistor is connected from VIN of the LTC3330

to VCC of the LTC4071 to create a charging path. VCC is

then the input to the LTC3330 buck-boost at the BAT pin.

The charging resistor should be sized in accordance with

the available energy from the energy harvesting source

to allow the VIN pin voltage of the LTC3330 to reach the

APPLICATIONS

Figure 8. Energy Harvesting Battery Charger with Low Battery Disconnect

UVLO rising threshold and prioritize powering the output

at VOUT.

Higher Efficiency Battery Powered Buck

If the battery voltage will always be higher than the regu-

lated output of the LTC3330 then the battery powered

buck-boost will always run in buck mode. In this case the

inductor that is usually placed between SWA and SWB

can go directly to VOUT from SWA, bypassing internal

switch M4 of the buck-boost (Figure 9). This will reduce

conduction losses in the converter and improve the ef-

ficiency at higher loads.

LTC3330

3330 F08

AC1

VIN

CAP

VIN2

AC2

3.3V

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

22µH

VIN3

1µF

6.3V

220µH

Li-ION

UVLOR = 12V*

UVLOF = 11V

IPEAK_BB = 25mA

22µF

25V

330k

1µF, 6.3V

4.7µF, 6.3V

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

SWA

SWB

GND

22µF

6.3V

1.8V

4.7µF

6.3V

MIDE V25W

22µF

6.3V

BAT ADJ

NTC

LTC4071

GND

VCC

LBSEL

*FOR PEAK POWER TRANSFER, CENTER THE UVLO WINDOW

AT HALF THE RECTIFIED OPEN CIRCUIT VOLTAGE OF THE PIEZO

LTC3330 I—‘DHII—"W ”HF __”_ ||| MPH % u||_‘ /_ , 25 L7ELUEN2

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

Figure 9. Higher Efficiency Battery Powered Buck Regulator

Efficiency Comparison Between Normal Buck-Boost

and Bypassed SWB Configuration

BAT (V)

EFFICIENCY (%)

3330 F09b

100

752.5 3 3.5 4 4.5 5.55

VOUT = 1.8V, BYPASS SWB

VOUT = 1.8V, INCLUDE SWB

VOUT = 3.3V, BYPASS SWB

VOUT = 3.3V, INCLUDE SWB

L = 22µH, DCR = 0.36Ω, 100mA LOAD

LTC3330

3330 F09a

AC1 SWB SWA

VIN

CAP

VIN2

AC2

1.8V

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

22µH

VIN3

1µF

6.3V

UVLOR = 14V*

UVLOF = 13V

IPEAK_BB = 250mA

22µF

25V 1µF, 6.3V

4.7µF, 6.3V

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

GND

22µF

6.3V

1.5V

4.7µF

6.3V

MIDE V25W

22µF

6.3V

22µH

Li-ION

*FOR PEAK POWER TRANSFER, CENTER THE UVLO WINDOW

AT HALF THE RECTIFIED OPEN CIRCUIT VOLTAGE OF THE PIEZO

LTC3330 L7HEJWEGR 27

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

Alternative Power Sources

The LTC3330 can accommodate a wide variety of input

sources. Figure 10 shows the LTC3330 internal bridge

rectifier connected to a 120V RMS AC line in series with

four 150k current limiting resistors. This produces a

peak current of 250µA with the LTC3330 shunt holding

VIN at 20V. This current may be increased by reducing

the resistor values since the shunt can sink 25mA and

the bridge is rated for 50mA. An optional external Zener

diode (shown) may be required if the current exceeds

25mA. A transformer may also be used to step down the

voltage and reduce the power loss in the current limiting

resistors. This is a high voltage application and minimum

spacing between the line, neutral, and any high voltage

components should be maintained per the applicable UL

specification. For general off-line applications refer to UL

Regulation 1012.

Figure 11 shows an application where copper panels

are placed near a standard fluorescent room light to

capacitively harvest energy from the electric field around

the light. The frequency of the emission will be double the

line frequency for magnetic ballasts but could be higher

if the light uses electronic ballast. The peak AC voltage

and the total available energy will scale with the size of

the panels used and with the proximity of the panels to

the electric field of the light.

Using EH_ON to Program VOUT

The EH_ON output indicates whether the energy harvesting

input or the battery is powering the output. The application

on the last page of this data sheet shows the EH_ON output

tied to the OUT2 input. When EH_ON is low the output is

programmed to 2.5V and the battery powers the output.

When energy harvesting is available EH_ON is high and

the output is programmed to 3.6V allowing for increased

storage of harvested energy. If energy harvesting goes

away, the output is again programmed to 2.5V and the

buck-boost converter will be in sleep until the output is

discharged to the wake-up threshold. If the energy stored

at 3.6V is enough to ride through a temporary loss of

energy harvesting then the only drain on the battery will

be the quiescent current in sleep.

L7H11N§AQ

LTC3330

3330fc

For more information www.linear.com/LTC3330

APPLICATIONS

DANGEROUS AND LETHAL POTENTIALS ARE PRESENT IN OFFLINE CIRCUITS! BEFORE PROCEEDING ANY FURTHER, THE READER IS WARNED THAT

CAUTION MUST BE USED IN THE CONSTRUCTION, TESTING AND USE OF OFFLINE CIRCUITS. EXTREME CAUTION MUST BE USED IN WORKING

WITH AND MAKING CONNECTIONS TO THESE CIRCUITS. REPEAT: OFFLINE CIRCUITS CONTAIN DANGEROUS, AC LINE-CONNECTED HIGH VOLTAGE

POTENTIALS, USE CAUTION. ALL TESTING PERFORMED ON AN OFFLINE CIRCUIT MUST BE DONE WITH AN ISOLATION TRANSFORMER CONNECTED

BETWEEN THE OFFLINE CIRCUIT’S INPUT AND THE AC LINE. USERS AND CONSTRUCTORS OF OFFLINE CIRCUITS MUST OBSERVE THIS PRECAUTION

WHEN CONNECTING TEST EQUIPMENT TO THE CIRCUIT TO AVOID ELECTRIC SHOCK. REPEAT: AN ISOLATION TRANSFORMER MUST BE CONNECTED

BETWEEN THE CIRCUIT INPUT AND THE AC LINE IF ANY TEST EQUIPMENT IS TO BE CONNECTED.

Figure 10. AC Line Powered 5V UPS

LTC3330

3330 F10

AC1

VIN

CAP

VIN2

AC2

150k150k

120VAC

60Hz

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

VIN3

1µF

6.3V

22µH

UVLOR = 18V

UVLOF = 5V

IPEAK_BB = 250mA

22µF

25V 1µF, 6.3V

4.7µF, 6.3V

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

SWA

SWB

GND

2.5V

4.7µF

6.3V

22µF

6.3V

18V

(OPTIONAL) 5V

10mF

2.7V

10mF

2.7V

10µF

6.3V

22µH

150k150k

DANGER HIGH VOLTAGE

Li-ION

LTC3330 m ij II i: :L L7 LJUW 29

LTC3330

3330fc

For more information www.linear.com/LTC3330

Figure 11. Electric Field Energy Harvester

APPLICATIONS

LTC3330

3330 F11

AC1

VIN

CAP

VIN2

AC2

COPPER PANEL

(12" × 24")

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

VIN3

1µF

6.3V

1000µH

UVLOR = 14V

UVLOF = 5V

IPEAK_BB = 5mA

22µF

25V 1µF, 6.3V

4.7µF, 6.3V

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

SWA

SWB

GND

3.3V

4.7µF

6.3V

22µF

6.3V

4.5V

220mF

2.7V

220mF

2.7V

10µF

6.3V

22µH

Li-ION

COPPER PANEL

(12" × 24")

LTC3330 UH Package ’—fﬁﬂfﬁﬁﬁﬂﬁ:¢ Fig 1 d: Lrllﬂﬂﬂﬁlﬂﬂll ,_ﬁum; gm / / \ L a \UJUMUUUU \ + JUU UJU 1mm FHWH LL NmE V DRAWWG PROPOSED ma Mu-zzu VAALAHDN wrwu 2 DRAWWG NOTTO SCALE 3 ALL ulmEusmns ARE w MLLLLMEIERS 4 mMENsmNs or EXPOSED PM] ON aormm MOLD FLASN MOLD FLASH. LE PRESENT s 5 EXPOSED PAD SHALL BE SOLDER PLATED 5 EMBED AREA Ls DNLV A REFERENCE FDR on mE mp AND ammm 0E PACKAGE WWW L‘9‘LL:

LTC3330

3330fc

For more information www.linear.com/LTC3330

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

5.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES)

3.45 ±0.10

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

(UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05

0.70 ±0.05

3.50 REF

(4 SIDES)

4.10 ±0.05

5.50

±0.05

0.25 ±0.05

PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

3.45 ±0.05

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

LTC3330 L7 LJUW 3 1

LTC3330

3330fc

For more information www.linear.com/LTC3330

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 03/14 Clarified Typical Application

Clarified Absolute Maximum Ratings table

Clarified Electrical Characteristics table

Clarified graphs

Clarified Figure 1

3, 4, 5

6, 9, 10

B 11/14 Replaced PGOOD with PGVOUT on All Graphs

Replaced PGOOD with PGVOUT in Application Section

Clarified Figure 6 Schematic

Clarified Inductor Selection Paragraph

Clarified Figure 10 Schematic

C 08/15 Changed COUT Equation 21

LTC3330 |—|D|—| _____________________ . .l_1_l_l_l H La '—| {“1 "Tr—I T I. 32 L7ELUEN2

LTC3330

3330fc

For more information www.linear.com/LTC3330

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

 LINEAR TECHNOLOGY CORPORATION 2013

LT 0815 REV C • PRINTED IN USA

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3330

UPS System for Wireless Mesh Networks with Output Supercapacitor Energy Storage

LTC3330

3330 TA02

AC1

VIN

CAP

VIN2

AC2

VOUT

SCAP

BAL

LDO_IN

LDO2

LDO1

LDO0

LDO_EN

PGVOUT

PG_LDO

EH_ON

LDO_OUT

VIN3

1µF

6.3V

22µH

Li-SOCL2

UVLOR = 8V*

UVLOF = 7V

IPEAK_BB = 250mA

22µF

25V 1µF, 6.3V

4.7µF, 6.3V

UV3

UV2

UV1

UV0

BAT

IPK2 IPK1 IPK0 OUT2 OUT1 OUT0

SWA

SWB

GND

4.7µF

6.3V

MIDE V25W

LINEAR TECHNOLOGY DC9003A-AB

DUST MOTE FOR WIRELESS MESH NETWORKS

PGOOD

EHORBAT

VSUPPLY

GND

VOUT = 3.6V FOR EH_ON = 1

VOUT = 2.5V FOR EH_ON = 0

2.7V

10µF

6.3V

22µH

*FOR PEAK POWER TRANSFER, CENTER THE UVLO WINDOW

AT HALF THE RECTIFIED OPEN CIRCUIT VOLTAGE OF THE PIEZO

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LT1389 Nanopower Precision Shunt Voltage Reference VREF: 1.25V, 2.25V, 4.096V; IQ = 800nA; ISD < 1µA; SO-8 Package

LTC1540 Nanopower Comparator with Reference VIN: 2V to 11V; IQ = 0.3µA; ISD < 1µA; 3mm × 3mm DFN-8 Package

LT3009 3μA IQ, 20mA Low Dropout Linear Regulator VIN: 1.6V to 20V; VOUT(MIN): 0.6V, Fixed 1.2V to 5V; IQ = 3µA; ISD < 1µA;

SC-70-8, 2mm × 2mm DFN-8 Packages

LTC3105 400mA Step-Up Converter with MPPC and 250mV

Start-Up

VIN: 0.2V to 5V; VOUT(MIN): Max 5.25V; IQ = 22µA; ISD < 1µA; 3mm × 3mm DFN-10,

MSOP-12 Package

LTC3108 Ultralow Voltage Step-Up Converter and Power

Manager

VIN: 0.02V to 1V; VOUT(MIN): Fixed 2.35V to 5V; IQ = 7µA; ISD < 1µA;

TSSOP-16, 3mm × 4mm DFN-12 Packages

LTC3109 Auto-Polarity, Ultralow Voltage Step-Up Converter

and Power Manager

VIN: 0.03V to 1V; VOUT(MIN): Fixed 2.35V to 5V; IQ = 7µA; ISD < 1µA;

SSOP-20, 4mm × 4mm QFN-20 Packages

LTC3388-1/

LTC3388-3

20V, 50mA High Efficiency Nanopower

Step-Down Regulator

VIN: 2.7V to 20V; VOUT(MIN): Fixed 1.1V to 5.5V; IQ = 720nA; ISD = 400nA;

MSOP-10, 3mm × 3mm DFN-10 Packages

LTC3588-1/

LTC3588-2

Piezoelectric Energy Harvesting Power Supply with

Up to 100mA of Output Current

VIN: 2.7V to 20V; VOUT(MIN): Fixed 1.8V to 5V; IQ = 950nA; ISD = 450nA;

MSOP-10, 3mm × 3mm DFN-10 Packages

LTC4070 50mA Micropower Shunt Li-Ion Charge VOUT(MIN): 4V, 4.1V, 4.2V; IQ = 450nA; ISD = 45nA; MSOP-8, 2mm × 3mm DFN-8

Packages

LTC4071 50mA Micropower Shunt Li-Ion Charge with

PowerPath™ Control

VOUT(MIN): 4V, 4.1V, 4.2V; IQ = 450nA; ISD = 45nA; MSOP-8, 2mm × 3mm DFN-8

Packages

LTC3129/

LTC3129-1

Micropower 200mA Synchronous Buck-Boost

DC/DC Converter

VIN: 2.42V to 15V; VOUT(MIN): 1.4V to 15V; IQ = 1.3µA; ISD = 10nA;

MSOP-16E, 3mm × 3mm QFN-16 Packages

Analog Devices Inc. 的 LTC3330 规格书

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