EPC 的 EPC2216 规格书

RoHS (A @ Halogen-Free
eGaN® FET DATASHEET EPC2216
EPCPOWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
EPC2216 – Automotive 15 V (D-S) Enhancement
Mode Power Transistor
VDS , 15 V
RDS(on) , 26 mΩ
ID , 3.4 A
AEC-Q101
EPC2216 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 0.85 mm x 1.2 mm
Applications
• High Speed DC-DC conversion
• Lidar/Pulsed Power Applications
• Lidar for Augmented Reality Applications
Benefits
Ultra High Efficiency
Ultra Low RDS(on)
Ultra Low QG
Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 15 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 18
ID
Continuous (TA = 25°C) 3.4 A
Pulsed (25°C, TPULSE = 300 µs) 28
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage –4
TJOperating Temperature 40 to 150 °C
TSTG Storage Temperature 40 to 150
Static Characteristics (TJ= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.1 mA 15 V
IDSS Drain-Source Leakage VDS = 15 V, VGS = 0 V, TJ = 25°C 0.01 0.1 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.004 0.5 mA
Gate-to-Source Forward Leakage#VGS = 5 V, TJ = 125°C 0.02 1mA
Gate-to-Source Reverse Leakage VGS = -4 V, TJ = 25°C 0.01 0.1 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.7 12.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 1.5 A 20 26
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
# Defined by design. Not subject to production test.
All measurements were done with substrate connected to source.
Thermal Characteristics
PARAMETER TYP UNIT
R
θ
JC Thermal Resistance, Junction-to-Case 5.7
°C/WR
θ
JB Thermal Resistance, Junction-to-Board 39
R
θ
JA Thermal Resistance, Junction-to-Ambient (Note 1) 97
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
eGaN® FET DATASHEET EPC2216
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25
20
15
10
5
00 0.5 1.0 1.5 2.0 3.02.5
ID – Drain Current (A)
VDS – Drain-to-Source Voltage (V)
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
Figure 1: Typical Output Characteristics at 25°C
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
2.5 2.0 3.0 3.5 4.0 4.5 5.0
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 0.8 A
ID = 1.5 A
ID = 2.2 A
ID = 3 A
70
60
50
40
30
20
10
0
25
20
15
10
5
00.5 1.0 1.5 2.0 3.02.5 3.5 4.54.0 5.0
ID – Drain Current (A)
VGS – Gate-to-Source Voltage (V)
Figure 2: Transfer Characteristics
25˚C
125˚C
VDS = 3 V
25°C
125°C
VDS = 3 V
2.5 3.02.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
25°C
125°C
ID = 1.5 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
70
60
50
40
30
20
10
0
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance#
VDS = 7.5 V, VGS = 0 V
98 118
pF
CRSS Reverse Transfer Capacitance 20
COSS Output Capacitance#66 99
COSS(ER) Effective Output Capacitance, Energy Related (Note 2) VDS = 0 to 7.5 V, VGS = 0 V 69
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 71
RG Gate Resistance 0.5 Ω
QG Total Gate Charge#VDS = 7.5 V, VGS = 5 V, ID = 1.5 A 0.87 1.1
nC
QGS Gate-to-Source Charge
VDS = 7.5 V, ID = 1.5 A
0.21
QGD Gate-to-Drain Charge 0.13
QG(TH) Gate Charge at Threshold 0.16
QOSS Output Charge#VDS = 7.5 V, VGS = 0 V 0.53 0.8
QRR Source-Drain Recovery Charge 0
# Defined by design. Not subject to production test.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2216
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All measurements were done with substrate shortened to source.
1000
100
10
Capacitance (pF)
VDS – Drain-to-Source Voltage (V)
Figure 5b: Capacitance (Log Scale)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0 5.02.5 7.5 10.0 15.012.5
0 0.2 0.4 0.6 0.8 1.0
Figure 7: Gate Charge
ID = 1.5 A
VDS = 7.5 V
VGS Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
5
4
3
2
1
0
Figure 9: Normalized On-State Resistance vs. Temperature
I
D
= 1.5 A
V
GS
= 5 V
Normalized On-State Resistance R
DS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0 25 50 75 100 125 150
T
J
– Junction Temperature (°C)
120
100
80
60
40
20
0
Capacitance (pF)
Figure 5a: Capacitance (Linear Scale)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
0 5.02.5 7.5 10.0 15.012.5
VDS – Drain-to-Source Voltage (V)
Figure 6a: Output Charge and C
OSS
Stored Energy
QOSS – Output Charge (nC)
EOSS COSS Stored Energy (μJ)
1.20
0.96
0.72
0.48
0.24
0.00
0.0080
0.0064
0.0048
0.0032
0.0016
0.0000
2.5 5.0 7.5 15.012.510.0
VDS – Drain-to-Source Voltage (V)
Figure 6: Output Charge and COSS Stored Energy
0.0
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
5.0
I
SD
Source-to-Drain Current (A)
V
SD
– Source-to-Drain Voltage (V)
25
20
15
10
5
0
25°C
125°C
V
GS
= 0
Figure 8: Reverse Drain-Source Characteristics
fi’ fir
eGaN® FET DATASHEET EPC2216
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Figure 12: Transient Thermal Response Curves
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
0.2
0.1
0.02
0.05
Single Pulse
0.01
Duty Cycle:
Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 101
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.1
0.2
0.02
0.05
Single Pulse
0.01
Duty Cycle:
Junction-to-Board
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 101
1
0.1
0.01
0.001
100
10
1
0.10.1 1 10 100
Pulse Width
1 ms
100 μs
Figure 11: Safe Operating Area
I
D
– Drain Current (A)
V
DS
– Drain-Source Voltage (V)
Limited by RDS(on)
Figure 10: Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
T
J
– Junction Temperature (°C)
ID = 1 mA
EB EB 63 —— Dlmenslonmlm) large! mm max 8 9.09 7,90 9.30 n 1.75 1.65 1.95 2010122) 3.59 3.45 3,55 d 4.09 3.90 4.10 a 4.09 3.90 4,10 unmsz) 2.09 1.95 2.05 g 1.5 1.5 1.6
eGaN® FET DATASHEET EPC2216
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DIE MARKINGS
2216
YYYY
ZZZZ
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die orientation dot
Gate solder bump is
under this corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
EPC2216 (note 1)
Die orientation dot
Gate Pad bump is
under this corner
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
EPC2216 2216 YYYY
Lot_Date Code
Marking line 3
ZZZZ
2216
YYYY
ZZZZ
fa TL
eGaN® FET DATASHEET EPC2216
EPCPOWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6
Information subject to change
without notice.
Revised May, 2020
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED
LAND PATTERN
(measurements in µm) Pad 1 is Gate;
Pads 2 , 5 are Drain;
Pads 3, 4, 6 are Source
The land pattern is solder mask defined
Solder mask is 10 μm smaller per side than bump
DIE OUTLINE
Solder Bump View
Side View
DIM
Micrometers
MIN Nominal MAX
A820 850 880
B1170 1200 1230
c400
d187 208 229
e185 200 215
f210 225 240
1
c
B
e
d
c
c
f
41
25
36
695+/-15
Seating Plane
860 Typ
165+/- 17
A
Pad 1 is Gate;
Pads 2, 5 are Drain;
Pads 3, 4, 6 are Source
RECOMMENDED
STENCIL DRAWING
(measurements in µm)
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 4
solder,reference 88.5% metals content.
Additional assembly resources available at
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
400
1200
200
400
400
225
850
63
25
14
200 +20 / - 10 (*)
* minimum 190
Solder mask opening
200 μm
Stencil opening
250 μm rounded square (60 deg)
4 mil stencil stainless laser cut
type 4 solder
200 μm
400 μm
400 μm
400 μm
200 μm
+20 μm / -10 μm
Min 190 μm
250 μm
175 μm
175 μm