EPC 的 EPC2103 规格书

@ Halogen-Free
eGaN® FET DATASHEET EPC2103
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VDS , 80 V
RDS(on) , 5.5 mΩ
ID , 30 A
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
EPC2103 eGaN® ICs are supplied only in
passivated die form with solder bumps
Die Size: 6.05 mm x 2.3 mm
Applications
• High Frequency DC-DC
• Motor Drive
Benefits
Ultra High Efficiency
High Frequency Operation
High Density Footprint
EFFICIENT POWER CONVERSION
HAL
Maximum Ratings
DEVICE PARAMETER VALUE UNIT
Q1
&
Q2
VDS
Drain-to-Source Voltage (Continuous) 80 V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
96
ID
Continuous (TA = 25˚C, RθJA = 13°C/W) 30 A
Pulsed (25°C, TPULSE = 300 µs) 195
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature –40 to 150 °C
TSTG Storage Temperature –40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction-to-Case
0.3
°C/W
RθJB
Thermal Resistance, Junction-to-Board
2.2
RθJA
Thermal Resistance, Junction-to-Ambient (Note 1)
42
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
EPC2103 – Enhancement-Mode GaN Power
Transistor Half-Bridge
Static Characteristics (TJ = 25°C unless otherwise stated)
DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Q1 & Q2
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.5 mA 80 V
IDSS Drain-Source Leakage VDS = 64 V, VGS = 0 V 0.007 0.4 mA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.013 6.5 mA
Gate-to-Source Reverse Leakage VGS = -4 V 0.007 0.4 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA 0.8 1.3 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 20 A 4 5.5
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V
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Dynamic Characteristics (TJ = 25°C unless otherwise stated)
DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Q1
CISS Input Capacitance
VDS = 40 V, VGS = 0 V
730 880
pF
CRSS Reverse Transfer Capacitance 7
COSS Output Capacitance 445 670
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 40 V, VGS = 0 V
573
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 733
QG Total Gate Charge VDS = 40 V, VGS = 5 V, ID = 20 A 6.5 8
nC
QGS Gate-to-Source Charge
VDS = 40 V, ID = 20 A
2.2
QGD Gate-to-Drain Charge 1.1
QG(TH) Gate Charge at Threshold 1.5
QOSS Output Charge VDS = 40 V, VGS = 0 V 30 45
QRR Source-Drain Recovery Charge 0
Q2
CISS Input Capacitance
VDS = 40 V, VGS = 0 V
730 880
pF
CRSS Reverse Transfer Capacitance 7
COSS Output Capacitance 525 790
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)
VDS = 0 to 40 V, VGS = 0 V
668
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 855
QG Total Gate Charge VDS = 40 V, VGS = 5 V, ID = 20 A 6.5 8
nC
QGS Gate-to-Source Charge
VDS = 40 V, ID = 20 A
2.2
QGD Gate-to-Drain Charge 1.1
QG(TH) Gate Charge at Threshold 1.5
QOSS Output Charge VDS = 40 V, VGS = 0 V 34 51
QRR Source-Drain Recovery Charge 0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
E
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Capacitance (pF)
1000
100
10
10 20 40 60 80
Figure 5b (Q1): Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capacitance (pF)
0 20 40 60 80
Figure 5a (Q1): Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
2000
1500
1000
500
0
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
3.0 2.5 3.5 4.0 4.5 5.0
Figure 3 (Q1 & Q2): RDS(on) vs. VGS for Various Drain Currents
ID = 10 A
ID = 20 A
ID = 30 A
ID = 40 A
16
12
8
4
0
16
12
8
4
03.02.5 3.5 4.0 4.5 5.0
Figure 4 (Q1 & Q2): RDS(on) vs. VGS for Various Temperatures
25˚C
125˚C
ID = 20 A
RDS(on) – Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
150
100
50
00 0.5 1.0 1.5 2.0 2.5 3.0
ID
Drain Current (A)
VDS Drain-to-Source Voltage (V)
Figure 1 (Q1 & Q2): Typical Output Characteristics at 25°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
ID
Drain Current (A)
1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
25˚C
125˚C
VDS = 3 V
VGS – Gate-to-Source Voltage (V)
Figure 2 (Q1 & Q2): Transfer Characteristics
25˚C
125˚C
VDS = 3 V
150
100
50
0
L ”9'"? 63 ('11): 0MP“ ("3'99 3"" ( s Stored Energy Figure 6b (02): Output charge and C 5 Stored Energy /
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0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ISD Source-to-Drain Current (A)
VSD – Source-to-Drain Voltage (V)
Figure 8 (Q1 & Q2): Reverse Drain-Source Characteristics
150
100
50
0
25˚C
125˚C
VDS = 3 V
25˚C
125˚C
VGS = 0 V
0 2 4 6 8
Figure 7 (Q1 & Q2): Gate Charge
VGS Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
ID = 20 A
VDS = 40 V
5
4
3
2
1
0
Figure 6a: Output Charge and COSS Stored Energy
QOSS Output Charge (nC)
EOSS COSS Stored Energy (μJ)
50
40
30
20
10
0
2.0
1.6
1.2
0.8
0.4
0.0
0 20 40 60 80
VDS – Drain-to-Source Voltage (V)
Figure 6a (Q1): Output Charge and C
OSS
Stored Energy
Figure 6a: Output Charge and COSS Stored Energy
Q
OSS
Output Charge (nC)
E
OSS
C
OSS
Stored Energy (μJ)
60
50
40
30
20
10
0
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0 20 40 60 80
V
DS
– Drain-to-Source Voltage (V)
Figure 6b (Q2): Output Charge and COSS Stored Energy
Capacitance (pF)
0 20 40 60 80
Figure 5c (Q2): Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
2000
1500
1000
500
0
Capacitance (pF)
1000
100
10
10 20 40 60 80
Figure 5d (Q2): Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure9(01& 02): Figure 10 (01 8: 02): Normal ixed Threshold Voltage (01 51 01)]IIIIdion-ln-Board 43H— (01 &02)Jundinn-lu-(ase _| 4: T
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Figure 9 (Q1 & Q2):
Normalized On-State Resistance vs. Temperature
ID = 20 A
VGS = 5 V
Normalized On-State Resistance RDS(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.8 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
Figure 10 (Q1 & Q2):
Normalized Threshold Voltage vs. Temperature
Normalized Threshold Voltage
1.400
1.300
1.200
1.100
1.000
0.900
0.800
0.700
0.600 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 7 mA
Single Pulse
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
0.5
0.05
0.02
Single Pulse
0.01
0.1
0.2
Duty Cycle:
(Q1 & Q2) Junction-to-Board
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 101
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
ZθJC, Normalized Thermal Impedance
0.5
0.1
0.02
0.05
Single Pulse
0.01
0.2
Duty Cycle:
(Q1 & Q2) Junction-to-Case
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
Figure 11a
Transient Thermal
Response Curves
Figure 11b
Transient Thermal
Response Curves
T E} i“ a v :;> 00 Q ’« {0 000000 \ 71> é ¢ T b 3 l
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Figure 13: Typical Application Circuit
Gate driver/
controller
eGaNIC
GND
Gate 1
GR1
VIN
VIN+
+
_
_
VOUT
RLoad
PGND
VSW
Q1
Q2
Gate 2
VB
HO
VS
VCC
LO
1000
100
10
1
0.1
0.1 1 10 100
ID – Drain Current (A)
VDS – Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse
Limited by RDS(on)
Pulse Width
100 µs
1 ms
250 µs
Figure 12 (Q1 & Q2): Safe Operating Area
DIE MARKINGS
YYYY
2103
ZZZZ
TAPE AND REEL CONFIGURATION
8 mm pitch, 12 mm wide tape on 7” reel
7” inch reel
Die
orientation
dot
Gate solder bump
is under this
corner
Die is placed into pocket
solder bump side down
(face side down)
Loaded Tape Feed Direction
a
d
e
f g
h
c b
DIM Dimension (mm)
EPC2103 (Note 1) Target MIN MAX
a12.00 11.90 12.30
b1.75 1.65 1.85
c (Note 2) 5.50 5.45 5.55
d4.00 3.90 4.10
e8.00 7.90 8.10
f (Note 2) 2.00 1.95 2.05
g1.50 1.50 1.60
h1.50 1.50 1.75
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
2103
YYYY
ZZZZ
Die orientation dot
Gate bumps are along this edge of the die
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
EPC2103 2103 YYYY ZZZZ
OOOOOOOCOOCOOCO OOOOOOOOOOOOOO OOOOOOOOOOOOOON OOOOOOOOOOOOOO COOOOOCOMOOOCO w , UVUUUUUvUUL/UUUU’L : L OOOOOOOOOOOOOCO {*OOOOOOOOOOOOOOO Vi...............§ OOOOOOOOOOOOOOO OOOOOOOOOOOOOCC nose 4L flush “r 2m
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(625)
(785)
160+/−16
A
B
c
e
e
d
f
Seating plane
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Information subject to
change without notice.
Revised June, 2020
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
RECOMMENDED LAND PATTERN
(measurements in µm)
Pad 2 is Gate 1 (high side); Pad 3 is HS Gate Return;
Pad 4 is G2;
Pads 1, 11, 12, 13, 21, 22, 23, 31, 32, 33, 41, 42, 51,
52, 61, 62, 71, 72 are VIN ;
Pads 5, 14, 15, 24, 25, 34, 35, 43, 44, 45, 53, 54, 55,
63, 64, 65, 73, 74, 75 Ground;
Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29,
30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58,
59, 60, 66, 67, 68, 69, 70 are Switch Node
The land pattern is solder mask defined.
Suggest SMD Pads at 200 +20/–10 µm.
190 µm minimum.
DIE OUTLINE
Solder Bump View
Side View
DIM MIN Nominal MAX
A6020 6050 6080
B2270 2300 2330
c400 400 400
d450 450 450
e210 225 240
f187 208 229
RECOMMENDED STENCIL DRAWING
(measurements in µm)
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
Additional assembly resources available at:
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
6050
2300
400
450
5
3
1
10
8
6
15
13
11
20
18
16
25
23
21
30
28
26
35
33
31
38 43 48 53 58 63 68
36 41 46 51 56 61 66 71
2 7 12 17 22 27 32 37 42 47 52 57 62 67 72
73
4 9 14 19 24 29 34 39 44 49 54 59 64 69 74
40 45 50 55 60 65 70 75
6050
2300
400
225
275
450