Microchip Technology 的 MT9162 规格书

ZARLINK" SEMICONDUCTOR Pw RS 1 M
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Single 5 volt supply
• Programmable µ−law/A-law Codec and filters
• Fully differential output driver
• SSI digital interface
• SSI speed control via external pins CSLO-CSL2
• Individual transmit and receive mute controls
• 0 dB gain in receive path
• 6 dB gain in transmit path
• Low power operation
• ITU-T G.714 compliant
Applications
• Cellular radio sets
• Local area communications stations
• Line cards
Description
The MT9162 5 V single rail Codec incorporates a built-
in Filter/Codec, transmit anti-alias filter, a reference
voltage and bias source. The device supports both A-
law and µ-law requirements.
The analog interface is capable of driving a 20 k ohm
load.
The MT9162 is fabricated in Zarlink's ISO2-CMOS
technology ensuring low power consumption and high
reliability.
May 2006
Ordering Information
MT9162AE 20 Pin PDIP Tubes
MT9162AS 20 Pin SOIC Tubes
MT9162AN 20 Pin SSOP Tubes
MT9162AN1 20 Pin SSOP* Tubes
*Pb Free Matte Tin
-40°C to +85°C
ISO2-CMOS MT9162
5 Volt Single Rail Codec
Data Sheet
Figure 1 - Functional Block Diagram
AIN+
AIN-
AOUT +
AOUT -
FILTER/CODEC GAIN
ENCODER
DECODER
6dB
0 dB Analog
Interface
PCM
Serial
Interface
Timing
Control
VDD
VSS
VBias
VRef
Din
Dout
STB
CLOCKin
PWRST IC A/µCSL0 CSL1 CSL2 RXMute TXMute
3333333333 w EEEEEEEEEE MK 20 PIN PDIP SOIC 5501’ m m
MT9162 Data Sheet
2
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin # Name Description
1V
Bias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect
0.1 µ F capacitor to VSS. Connect 1 µF capacitor to Vref.
2V
Ref Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used internally. Connect 0.1
µ F capacitor to VSS. Connect 1 µF capacitor to VBias
3PWRSTPower-up Reset. Resets internal state of device via Schmitt Trigger input (active low).
4ICInternal Connection. Tie externally to VSS for normal operation.
5A/µA/µ Law Selection. CMOS level compatible input pin governs the companding law used by the
device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS.
6RXMuteReceive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation.
CMOS level compatible.
7TXMuteTransmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation.
CMOS level compatible.
8
9
10
CSL0
CSL1
CSL2
Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the conversion
rate between the externally supplied MCL clock and the 512 kHz clock required by the filter/codec.
Refer to Table 2 for details. CMOS level compatible.
11 Dout Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1 device.
Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot defined by
STB.
12 Din Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the falling
edge of BCL during the timeslot defined by STB. CMOS level compatible.
13 STB Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and receive
data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible.
14 CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions. Connect bit
clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin when the bit clock
is 128 kHz or 256 kHz. CMOS level compatible.
15 VDD Positive Power Supply. Nominally 5 volts.
AIN-
AIN+
VBias
VRef
IC
RXMUTE
CSL0
CSL1
CSL2
Din
Dout
VSS
AOUT +
AOUT -
VDD
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
PWRST
TXMUTE
STB
CLOCKin
20 PIN PDIP/SOIC/SSOP
A/µ
MT9162 Data Sheet
3
Zarlink Semiconductor Inc.
Overview
The 5 V single rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals
(Filter/Codec) and an analog interface to a standard analog transmitter and receiver (Analog Interface). The
receiver amplifier is capable of driving a 20 k ohm load.
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion.
The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the
nominal half-channel for the MT9162.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the analog
interface section to provide full chip realization of these capabilities for the external functions.
A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for
biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it
may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog
ground at all times. Likewise, although VRef may only be used internally, a 0.1µF capacitor from the VRef pin to
ground is required at all times. The analog ground reference point for these two capacitors must be physically the
same point. To facilitate this the VRef and VBias pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second
order lowpass implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the
sinx/x attenuation caused by the 8 kHz sampling rate.
Companding law selection for the Filter/Codec is provided by the A/ µ companding control pin. Table 1 illustrates
these choices.
16 AOUT- Inverting Analog Output. (balanced).
17 AOUT+ Non-Inverting Analog Output. (balanced).
18 VSS Ground. Nominally 0 volts.
19 Ain- Inverting Analog Input. No external anti-aliasing is required.
20 Ain+ Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.
Pin Description (continued)
Pin # Name Description
MT9162 Data Sheet
4
Zarlink Semiconductor Inc.
Table 1 - Law Selection
Analog Interfaces
Standard interfaces are provided by the MT9162. These are:
• The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 3.667Vpp µ−law and across
AIN+/AIN- 3.8Vpp A-law.
• The analog outputs (receiver), pins AOUT+/AOUT-.This internally compensated fully differential output driver is
capable of driving a load of 20k ohms.
PCM Serial Interface
A serial link is required to transport data between the MT9162 and an external digital transmission device. The
MT9162 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI).
The required mode of operation is selected via the CSL2-0 control pins. See Table 2 for selections based in CSL2-
0 pin settings.
Quiet Code
The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute
pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the
Figure 2 - Table 2: Bit Clock Rate Selection
TxMute pin is high. When either of these pins are low their respective paths function normally. The -Zero entry of
Table 1 is used for the quiet code definition.
Code
ITU-T (G.711)
µ -Law A-Law
+ Full Scale 1000 0000 1010 1010
+ Zero 1111 1111 1101 0101
-Zero
(quiet code)
0111 1111 0101 0101
- Full Scale 0000 0000 0010 1010
CSL2CSL1CSL0
External
Clock Bit
Rate (kHz)
CLOCKin
(kHz)
1 0 0 128 4096
1 0 1 256 4096
000 512 512
0 0 1 1536 1536
0 1 0 2048 2048
0 1 1 4096 4096
MT9162 Data Sheet
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Zarlink Semiconductor Inc.
SSI Mode
The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input
signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if
the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.
In SSI mode the MT9162 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel
data are always in the channel defined by the STB input.
The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This
is an active high signal with an 8 kHz repetition rate.
SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is
512 kHz or greater then it is used directly by the internal MT9162 functions allowing synchronous operation. If the
available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal
MT9162 functions.
Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9162 will re-align its
internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2,
CSL1 and CSL0 are used to program the bit rates.
Figure 3 - Audio Gain Partitioning
For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the
STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.
Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during
the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation.
Serial Port Filter/Codec and Analog Interface
PCM Receive
Filter Gain
0 dB
Receiver
Driver
-2.05 dB
Aout +
Aout- 20kΩ
Internal To Device External To Device
AIN+
AIN-
Transmit
Gain
8.42 dB
Transmit Gain
-0.37 dB
Transmit Filter
Gain
0 to +7 dB
(1 dB steps)
PCM Analog
Input
Din
Dout
Transmit Filter
Gain
0dB
Decoder
Encoder
2.05 dB
-2.05 dB
PWRST muk muk muk muk
MT9162 Data Sheet
6
Zarlink Semiconductor Inc.
For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output
jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit
cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications of Figures 5 & 6 for both synchronous and asynchronous SSI
timing.
PWRST
While the MT9162 is held in PWRST no device control or functionality is possible.
Applications
Figure 4 shows the MT9162 in a line card application.
Figure 4 - Line Card Application
0.1 µF
0.1 µF
VBias
+5V
+5V
DC to DC
Converter
Twisted Pair
+5V
Dout
Din
Lin
ZT
Lout
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
Frame Pulse
Clock
A/µMT9162
Typical External Gain
AV = 5 -1 0
()
100k
100k
100k
100k
100k
100k
100k
1k
1k
1k
1k
1k
1k
CS2
CS1
CS0
TxMUTE
RxMUTE
MT8972
DNIC
From Digital
Phone
Out to Subscriber Line
Interface
Input from Subscriber
Line Interface
1 µF
MT9162 Data Sheet
7
Zarlink Semiconductor Inc.
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 1: Power delivered to the load is in addition to the bias current requirements.
Absolute Maximum Ratings†
Parameter Symbol Min. Max. Units
1 Supply Voltage VDD - VSS - 0.3 7 V
2 Voltage on any I/O pin VI/VOVSS - 0.3 VDD + 0.3 V
3 Current on any I/O pin (transducers excluded) II/IO± 20 mA
4 Storage Temperature TS- 65 + 150 °C
5 Power Dissipation (package) PD750 mW
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1 Supply Voltage VDD 4.7555.25 V
2 CMOS Input Voltage (high) VIHC 4.5 VDD V
3 CMOS Input Voltage (low) VILC VSS 0.5 V
4 Operating Temperature TA- 40 + 85 °C
Power Characteristics
Characteristics Sym. Min. Typ. Max. Units Test Conditions
1 Static Supply Current (clock disabled) IDDC1 420µA Outputs unloaded, Input
signals static, not loaded
2 Dynamic Supply Current:
Total all functions enabled IDDFT 7.0 10 mA See Note 1
PWRST PWRST
MT9162 Data Sheet
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Zarlink Semiconductor Inc.
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1 - Magnitude measurement, ignore signs.
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Input HIGH Voltage CMOS inputs VIHC 3.5 V
2 Input LOW Voltage CMOS inputs VILC 1.5 V
3 VBias Voltage Output VBias VDD/2 V Max. Load = 10kΩ
4V
Ref Output Voltage VRef VDD/2-
1.9
VNo load
5 Input Leakage Current IIZ 0.1 10 µAV
IN=VDD to VSS
6 Positive Going Threshold
Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)
VT+
VT-
3.7
1.3
V
V
7 Output HIGH Current IOH 37 mAV
OH = 0.9*VDD
See Note 1
8 Output LOW Current IOL 510 mAV
OL = 0.1*VDD
See Note 1
9 Output Leakage Current IOZ 0.01 10 µAV
OUT = VDD and VSS
10 Output Capacitance Co15 pF
11 Input Capacitance Ci10 pF
Clockin Tolerance Characteristics†
Characteristics Min. Typ.‡Max. Units Test Conditions
1 CLOCKin Frequency (Asynchronous
Mode)
4095.6 4096 4096.4 kHz (i.e., 100 ppm)
MT9162 Data Sheet
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Zarlink Semiconductor Inc.
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
AC Characteristics† for A/D (Transmit) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and 0dBm0 = ALo3.14
- 3.14dB = 1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.)
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Analog input equivalent to overload
decision
ALi3.17
ALi3.14
7.334
7.6
Vp-p
Vp-p
µ-Law
A-Law
Both at Codec
2 Absolute half-channel gain
AIN ± to Dout GAX1 5.2 6.0 6.8 dB
Transmit filter gain=0dB
setting.
@1020Hz
3 Gain tracking vs. input level
ITU-T G.714 Method 2
GTX -0.3
-0.6
-1.6
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
4 Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
DQX 35
29
24
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
5 Transmit Idle Channel Noise NCX
NPX
8.5
-71
12
-69
dBrnC0
dBm0p
µ-Law
A-Law
6 Gain relative to gain at
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
GRX
-0.25
-0.9
-45
-23
-40
-25
-30
0.0
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
dB
dB
7 Absolute Delay DAX 360 µs at frequency of minimum
delay
8 Group Delay relative to DAX DDX 750
380
130
750
µs
µs
µs
µs
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9 Power Supply Rejection
f=1020 Hz
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz
PSSR
PSSR1
PSSR2
PSSR3
37 37
40
35
40
dB
dB
dB
dB
±100mV peak signal on
VDD
µ-law
PSSR1-3 not production
tested
MT9162 Data Sheet
10
Zarlink Semiconductor Inc.
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
AC Characteristics† for D/A (Receive) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and 0dBm0 = ALo3.14
- 3.14dB = 1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.)
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Analog output at the Codec full
scale
ALo3.17
ALo3.14
7.225
7.481
Vp-p
Vp-p
µ-Law
A-Law
2 Absolute half-channel gain.
Din to AOUT±
GAR1 -0.8 0 0.8 dB @1020Hz
3 Gain tracking vs. input level
ITU-T G.714 Method 2
GTR -0.3
-0.6
-1.6
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
4 Signal to total distortion vs. input
level.
ITU-T G.714 Method 2
GQR 35
29
24
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
5 Receive Idle Channel Noise NCR
NPR
7
-84
10
-80
dBrnC0
dBm0p
µ-Law
A-Law
6 Gain relative to gain at 1020Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
GRR
-0.25
-0.90
0.25
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
7 Absolute Delay DAR 240 µs at frequency of min. delay
8 Group Delay relative to DAR DDR 750
380
130
750
µs
µs
µs
µs
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9 CrosstalkD/A to A/D
A/D to D/A
CTRT
CTTR
-74
-80
dB
dB
G.714.16
ITU-T
Electrical Characteristics† for Analog Outputs
Characteristics Sym. Min. Typ.‡Max
.Units Test Conditions
1 Load impedance at Output EZL 20k ohms across AOUT±
2 Allowable output capacitive
load
ECL 20 pF each pin:AOUT+, AOUT-
3 Analog output harmonic distortion ED0.5 % 20k ohms load across
AOUT±
VO≤693mVRMS
MT9162 Data Sheet
11
Zarlink Semiconductor Inc.
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1:Not production tested, guaranteed by design.
Electrical Characteristics† for Analog Inputs
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Maximum input voltage without
overloading Codec
across AIN+/AIN- VIOLH 2.90
3.00
Vp-p A/µ = 0
A/µ = 1
2 Input Impedance ZI50 kΩAIN+/AIN- to VSS
AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 5)
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 BCL Clock Period tBCL 244 1953 ns BCL=4096 kHz to 512 kHz
2 BCL Pulse Width High tBCLH 122 ns BCL=4096 kHz
3 BCL Pulse Width Low tBCLL 122 ns BCL=4096 kHz
4 BCL Rise/Fall Time tR/tF20 ns Note 1
5 Strobe Pulse Width tENW 8 x tBCL ns Note 1
6 Strobe setup time before BCL falling tSSS 70 tBCL-80 ns
7 Strobe hold time after BCL falling tSSH 80 tBCL-80 ns
8 Dout High Impedance to Active Low
from Strobe rising
tDOZL 50 ns CL=150 pF, RL=1K
9 Dout High Impedance to Active High
from Strobe rising
tDOZH 50 ns CL=150 pF, RL=1K
10 Dout Active Low to High Impedance
from Strobe falling
tDOLZ 50 ns CL=150 pF, RL=1K
11 Dout Active High to High Impedance
from Strobe falling
tDOHZ 50 ns CL=150 pF, RL=1K
12 Dout Delay (high and low) from BCL
rising
tDD 50 ns CL=150 pF, RL=1K
13 Din Setup time before BCL falling tDIS 20 ns
14 Din Hold Time from BCL falling tDIH 50 ns
MT9162 Data Sheet
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Zarlink Semiconductor Inc.
Figure 5 - SSI Synchronous Timing Diagram
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6)
Characteristics Sym. Min. Typ.‡Max. Units Test Conditions
1 Bit Cell Period TDATA 7812
3906
ns
ns
BCL=128 kHz
BCL=256 kHz
2 Frame Jitter Tj600 ns
3 Bit 1 Dout Delay from STB going
high
tdda1 Tj+600 ns CL=150 pF, RL=1K
4 Bit 2 Dout Delay from STB going
high
tdda2 600+
TDATA-Tj
600+
TDATA
600 +
TDATA+Tj
ns CL=150 pF, RL=1K
5 Bit n Dout Delay from STB going
high
tddan 600 +
(n-1) x
TDATA-Tj
600 +
(n-1) x
TDATA
600 +
(n-1) x
TDATA+Tj
ns CL=150 pF, RL=1K
n=3 to 8
6 Bit 1 Data Boundary TDATA1 TDATA-TjTDATA+Tjns
7 Din Bit n Data Setup time from
STB rising
tSU TDATA\2
+500ns-Tj
+(n-1) x
TDATA
ns n=1-8
8 Din Data Hold time from STB
rising
tho TDATA\2
+500ns+Tj
+(n-1) x
TDATA
ns
(BCL)
Din
Dout
STB
70%
30%
70%
30%
70%
30%
70%
30%
tBCLH
tRtF
tBCLL
tDIS tDIH
tDOZL
tDD
tBCL
tDOZH
tSSS tENW tSSH
tDOLZ
tDOHZ
NOTE: Levels refer to% VDD (CMOS I/O)
CLOCKin
MT9162 Data Sheet
13
Zarlink Semiconductor Inc.
Figure 6 - SSI Asynchronous Timing Diagram
Din
Dout
STB
70%
30%
70%
30%
70%
30%
Tj
tdda1
NOTE: Levels refer to% VDD (CMOS I/O)
tdha1
TDATA1
tdda2
TDATA
Bit 1 Bit 2 Bit 3
D1 D2 D3
tho
tsu
TDATA/2 TDATA TDATA
MT9162 Data Sheet
14
Zarlink Semiconductor Inc.
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
8-Pin 16-Pin 18-Pin 20-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
A 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33)
A20.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95)
B0.014
(0.356)
0.022
(0.558)
0.014
(0.356)
0.022
(0.558)
0.014
(0.356)
0.022
(0.558)
0.014
(0.356)
0.022
(0.558)
B10.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77)
C0.008
(0.204)
0.015
(0.381)
0.008
(0.204)
0.015
(0.381)
0.008
(0.204)
0.015
(0.381)
0.008
(0.204)
0.015
(0.381)
D 0.348 (8.84) 0.430
(10.92)
0.745
(18.93)
0.840
(21.33)
0.845
(21.47)
0.925
(23.49)
0.925
(23.49)
1.060 (26.9)
D10.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13)
E 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38)
E10.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)
e 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54)
e1
eA0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62)
L 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06)
E1
32 1
E
n-2 n-1 n
L
D
D1
B1
A2
e
B
C
eA
α
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
A
MT9162 Data Sheet
15
Zarlink Semiconductor Inc.
NOTE: ( ) Millimeters
S
a15°15°15°15°
DIM
8-Pin 16-Pin 18-Pin 20-Pin
Plastic Plastic Plastic Plastic
Min Max Min Max Min Max Min Max
HHHHHHHHH/ 1 L
MT9162 Data Sheet
16
Zarlink Semiconductor Inc.
DIM
16-Pin 18-Pin 20-Pin 24-Pin 28-Pin
Min Max Min Max Min Max Min Max Min Max
A0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A10.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
C0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.469
(11.90)
0.496
(12.60)
0.518
(13.00)
0.598
(15.2)
0.614
(15.6)
0.697
(17.7)
0.712
(18.1)
E0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
e 0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
F0.044
(1.125)
0.064
(1.625)
0.044
(1.125)
0.064
(1.625)
0.044
(1.125)
0.064
(1.625)
0.044
(1.125)
0.064
(1.625)
0.044
(1.125)
0.064
(1.625)
Pin 1
A1
B
e
FE
A
L
H
C
G
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) O1 & O2 are SYMMETRY dimensions
5) A & B Maximum dimensions include allowable mold flash
DL
4 mils (lead coplanarity)
MT9162 Data Sheet
17
Zarlink Semiconductor Inc.
Lead SOIC Package - S Suffix
G0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
H0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
DIM
16-Pin 18-Pin 20-Pin 24-Pin 28-Pin
Min Max Min Max Min Max Min Max Min Max
HHHHHHHEEEH
MT9162 Data Sheet
18
Zarlink Semiconductor Inc.
Small Shrink Outline Package (SSOP) - N Suffix
Pin 1
A
1
B
e
D
FE
A
L
H
C
G
Dim
20-Pin 24-Pin 28-Pin 48-Pin
MinMaxMinMaxMinMaxMinMax
A0.079
(2)
-0.079
(2)
0.079
(2)
0.095
(2.41)
0.110
(2.79)
A10.004
(0.1)
0.004
(0.1)
0.004
(0.1)
0.008
(0.2)
0.015
(0.4)
B0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.0087
(0.22)
0.013
(0.33)
0.008
(0.2)
0.0135
(0.34)
C0.008
(0.21)
0.008
(0.21)
0.008
(0.21)
0.010
(0.25)
D0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.41
(10.5)
0.62
(15.75)
0.63
(16.00)
E0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e 0.025 BSC
(0.65 BSC)
0.025 BSC
(0.65 BSC)
0.025 BSC
(0.65 BSC)
0.025 BSC
(0.65 BSC)
F 0.049 REF
(1.25 REF)
0.049 REF
(1.25 REF)
0.049 REF
(1.25 REF)
0.056 REF
(1.42 REF)
G0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.25)
0.099
(2.52)
H0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150
5) A & B Maximum dimensions include allowable mold flash
Control Dimensions Altern. Dimensions Symbol in millimetres in inches —. MlN Nominal MAX MlN Nominal MAX HHHHHHHHHH A 1.70 2.00 0.067 0.079 A1 0.05 0.20 0.002 0.008 A2 i.65 1.85 0.065 0.073 D 6.90 7.50 0. 0.295 E 7.40 8.20 0.29i 0.3 3 E‘ E1 5.00 5.60 0.i97 0.2 0 L 0.55 0.95 0.022 0.037 e 0.65 880. 0.026 880. b 0.22 0.38 0.009 0.0i5 c 0.09 0.25 0.004 0.0i0 _i 0 0' 8' 0' 8' A Pin features \\,l N 20 l Conforms to JEDEC MO—i50 AE lss. B This drawing supersedes:— A2 J] l l l iseating PM“ 4i8/E0/5i48i/002 (Swindon/Plymouth) Milli; t N J.L i. A visual index feature, e.g. a dot, must be located within the crassihotched area. 2. Controlling dimension are in millimeters. 3. Dimensions D and Ei do not include mould flash or protusion. Mould flash or protusion shall not exceed 0.20 mm per side. D and E1 ore maximum plastic body size dimensions including mould mismatch. 4. Dimension 0 does not include dambar protusion/intrusion. Allowable dambar protusion shall be O.i3> mm total in excess of b dimension. Dambor intrusion shall not reduce dimension b by more than 0.07 mm. ;l_t ”J_L © Zarlink Semiconductor 2002 All rights reserved Package Code D D ISSUE 1 2 3 Previous package codes Package Outline for 20 lead AC“ 201933 205234 212477 \ ZARLINK NP / N SSOP (5.3mm Body Width) SEMICONDUCTOR DATE 27FebQ7 255e098 3Apr02 APPRD GPDOO294
U PHHHHHHHHH Index area-\ Wifitjfii mint: Notes: Contral Dimensions Altern. Dimensions Symbol in millimetres in inches Nominal MAX MiN Nominal MAX A 2.65 0.093 0.104 A1 0.30 0.004 0.012 A2 2.35 0.089 0 092 D 13.00 0.496 0.512 H 10.65 0.394 0.419 E 7.60 0.291 0299 L 1.27 0.016 0.050 e 1 27 ESC. 7 0.050 ESC. b 0.51 0.013 0020 c 0.32 0.009 0.013 9 8' 0‘ 8‘ h 0.75 0.010 0029 Pin features N 20 Conforms to JEDEC MS—013AC 155. C 1. The chamfer on the body is optional, if it not present, a visual index feature, ea. a dot, must be located within the crossihotched area. 2. Controlling dimension are in millimeters. 3. Dimension D do not include mould flash, protrusion or gate burrs. These shall not exceed 0.006" per side. 4. Dimension E1 do not include intereiead flash or protrusion. These shall not exceed 0.010 per side. ” 5. Dimension b does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.004 total in excess of b dimension. @ Zarlink Semiconduflor 2002 All ngms reserved Issue 1 2 3 Package Code D C ACN 6746 201941 213098 ZARUNK SEMICONDUCTOR DATE 7Apr95 27Feb97 15Ju|02 Previous package codes MP/S Package Outline for 20 lead SOIC (0300" Body Width) APPRD GPDOOOiS
index Area N/Z «o Notes: Base Pione _ Sealing P1one _- “”2 1A * —m Min Max M1n Max mm mm |nches1ri he End ieod oi 4 corners A 5.33 0.210 A1 0.38 0.015 b2(Full1eod A2 2.92 4.95 0.115 0.195 m (run Lead) b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 D|(Hu|1Lead) b3 ri/o n/o n/c rr/o c 0.20 0.36 0.008 0.014 ““30“" ‘90“) D 24.89 26.92 0.980 1.060 D1 013 0.005 ‘fl E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 e 2.54 BSC 0.100 BSC A eA 7.62 BSC 0.300 BSC 1T1 63 10.92 0.430 L Z/‘l \& eC 0.00 1.52 0.000 0060 "C111 L 2.92 3.81 0.115 0.150 N 20 20 i. Dimensions D, D1 8: E1 do not include mou1d flash or proirusions. 2. Dimensions E 8c eA are measured w1|h 1eods eonsiroined io be perpendieuior io doium , c , 3. Dimensions eB & 6C are measured with «he leads unconstrained 4. Controiiing dimensions ore 1nches. M1l1i'meter conversions are noi necessariiy exoci. 5, N 15 me mox1mum of lerm'ma1 positions. Conforms 1o Jedec MSsOO1AD 1ssue D Tnis drawing supersedesi UK drawing [I 418/ED/39502/005 @ Zarhnk Semrennaunor 2002 A11 ngnrs reserved ISSUE ‘1 2 ACN 202562 213107 DATE 9Jun97 15Ju102 APPRD Package Code DA ZARUNK SEMICONDUCTOR Previous package codes DP/E Package OutHne for 20 180d PDIP GPDOO347
CCCCCCCCCCCCC
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