SmartFusion cSoC Datasheet by Microsemi SoC

O Microsemi

November 2018 I

SmartFusion Customizable System-on-Chip (cSoC)

Microcontroller Subsystem (MSS)

• Hard 100 MHz 32-bit ARM® Cortex®-M3 Processor

– 1.25 DMIPS/MHz Throughput from Zero Wait State

Memory

– Memory Protection Unit (MPU)

– Single Cycle Multiplication, Hardware Divide

– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2

wires), and Single Wire Viewer (SWV) Interfaces

• Internal Memory

– Embedded Nonvolatile Flash Memory (eNVM), 128

Kbytes to 512 Kbytes

– Embedded High-Speed SRAM (eSRAM), 16 Kbytes

to 64 Kbytes, Implemented in 2 Physical Blocks to

Enable Simultaneous Access from 2 Different

Masters

• Multi-Layer AHB Communications Matrix

– Provides up to 16 Gbps of On-Chip Memory

Bandwidth,1 Allowing Multi-Master Schemes

• 10/100 Ethernet MAC with RMII Interface2

• Programmable External Memory Controller, Which

Supports:

– Asynchronous Memories

– NOR Flash, SRAM, PSRAM

– Synchronous SRAMs

•Two I

2C Peripherals

• Two 16550 Compatible UARTs

• Two SPI Peripherals

• Two 32-bit Timers

• 32-bit Watchdog Timer

• 8-channel DMA Controller to Offload the Cortex-M3 from

Data Transactions

• Clock Sources

– 32 KHz to 20 MHz Main Oscillator

– Battery-Backed 32 KHz Low Power Oscillator with

Real-Time Counter (RTC)

– 100 MHz Embedded RC Oscillator; 1% Accurate

– Embedded Analog PLL with 4 Output Phases (0, 90,

180, 270)

High-Performance FPGA

• Based on proven ProASIC®3 FPGA Fabric

• Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,

Flash-Based CMOS Process

• Nonvolatile, Instant On, Retains Program When

Powered Off

• 350 MHz System Performance

• Embedded SRAMs and FIFOs

– Variable Aspect Ratio 4,608-Bit SRAM Blocks

– x1, x2, x4, x9, and x18 Organizations

– True Dual-Port SRAM (excluding x18)

– Programmable Embedded FIFO Control Logic

• Secure ISP with 128-bit AES via JTAG

• FlashLock® to Secure FPGA Contents

• Five Clock Conditioning Circuits (CCCs) with up to 2

Integrated Analog PLLs

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75 to

350 MHz

Programmable Analog

Analog Front-End (AFE)

• Up to Three 12-Bit SAR ADCs

– 500 Ksps in 12-Bit Mode

– 550 Ksps in 10-Bit Mode

– 600 Ksps in 8-Bit Mode

• Internal 2.56 V Reference or Optional External

Reference

• One First-Order  DAC (sigma-delta) per ADC

– 8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate

• Up to 5 High-Performance Analog Signal Conditioning

Blocks (SCB) per Device, Each Including:

– Two High-Voltage Bipolar Voltage Monitors (with 4

input ranges from ±2.5 V to –11.5/+14 V) with 1%

Accuracy

– High Gain Current Monitor, Differential Gain = 50, up

to 14 V Common Mode

– Temperature Monitor (Resolution = ¼°C in 12-Bit

Mode; Accurate from –55°C to 150°C)

• Up to Ten High-Speed Voltage Comparators

(tpd =15ns)

Analog Compute Engine (ACE)

• Offloads Cortex-M3–Based MSS from Analog

Initialization and Processing of ADC, DAC, and SCBs

• Sample Sequence Engine for ADC and DAC Parameter

Set-Up

• Post-Processing Engine for Functions such as Low-

Pass Filtering and Linear Transformation

• Easily Configured via GUI in Libero® System-on-Chip

(SoC) Software

I/Os and Operating Voltage

• FPGA I/Os

– LVDS, PCI, PCI-X, up to 24 mA IOH/IOL

– Up to 350 MHz

• MSS I/Os

– Schmitt Trigger, up to 6 mA IOH, 8 mA IOL

– Up to 180 MHz

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• External 1.5 V Is Allowed by Bypassing Regulator

(digital VCC = 1.5 V for FPGA and MSS, analog VCC =

3.3 V and 1.5 V)

1 Theoretical maximum

2 A2F200 and larger devices

Revision 14

O Microsemi.

SmartFusion Customizable System-on-Chip (cSoC)

II Revision 14

SmartFusion cSoC Family Product Table

FPGA Fabric

A2F060 A2F200 A2F500

TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

System Gates 60,000 200,000 500,000

Tiles (D-flip-flops) 1,536 4,608 11,520

RAM Blocks (4,608 bits) 8 8 24

Microcontroller Subsystem (MSS)

A2F060 A2F200 A2F500

TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

Flash (Kbytes) 128 256 512

SRAM (Kbytes) 16 64 64

Cortex-M3 processor with MPU Yes Yes Yes

10/100 Ethernet MAC No Yes Yes

External Memory Controller (EMC) – 26-/16-bit

address/data

26-bit address,16-bit data – 26-/16-bit address/data

DMA 8 Ch 8 Ch 8 Ch

I2C222

SPI 1 2 1 2 1 2

16550 UART 2 2 2

32-Bit Timer 2 2 2

PLL 1 1 1 2 1 2

32 KHz Low Power Oscillator 1 1 1

100 MHz On-Chip RC Oscillator 1 1 1

Main Oscillator (32 KHz to 20 MHz) 1 1 1

Programmable Analog

A2F060 A2F200 A2F500

TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

ADCs (8-/10-/12-bit SAR) 1 2 2 3

DACs (8-/16-/24-bit sigma-delta) 1 2 2 3

Signal Conditioning Blocks (SCBs) 1 4 4 5

Comparator* 2 8 8 10

Current Monitors* 1 4 4 5

Temperature Monitors* 1 4 4 5

Bipolar High Voltage Monitors* 2 8 8 10

Note: *These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in

the http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=130925 for details.

O Microsemi AZFOGO A2F200 AZFSOO

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 III

Package I/Os: MSS + FPGA I/Os

SmartFusion cSoC Device Status

Device A2F0601A2F2002A2F5002

Package TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

Direct Analog Inputs 11 11 11 8 8 8 8 8 8 8 12

Shared Analog Inputs 4 4 4 16 16 16 16 16 16 16 20

Total Analog Inputs 15 15 15 24 24 24 24 24 24 24 32

Analog Outputs 1111222 122 3

MSS I/Os3,4 21528526522 31 25 41 22 31 25 41

FPGA I/Os 33668 66 66 78 66 94 66678 66 128

Total I/Os 70 112 108 113 135 117 161 113 135 117 204

Notes:

1. There are no LVTTL capable direct inputs available on A2F060 devices.

2. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors.

3. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for MSS. These I/Os support Schmitt triggers and

support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.

4. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is

not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V

standards.

5. 10/100 Ethernet MAC is not available on A2F060.

6. EMC is not available on the A2F500 PQ208 and A2F060 TQ144 package.

Table 1 • SmartFusion cSoC Package Sizes Dimensions

Package TQ144 PQ208 CS288 FG256 FG484

Length × Width (mm\mm) 20 × 20 28 × 28 11 × 11 17 × 17 23 × 23

Nominal Area (mm2)400 784 121 289 529

Pitch (mm) 0.5 0.5 0.5 1.0 1.0

Height (mm) 1.40 3.40 1.05 1.60 2.23

Device Status

A2F060 Preliminary: CS288, FG256, TQ144

A2F200 Production: CS288, FG256, FG484, PQ208

A2F500 Production: CS288, FG256, FG484, PQ208

Q Microsemi. —> A FUSION" _J _J _J

SmartFusion Customizable System-on-Chip (cSoC)

IV Revision 14

SmartFusion cSoC Block Diagram

Legend:

SDD – Sigma-delta DAC

SCB – Signal conditioning block

PDMA – Peripheral DMA

IAP – In-application programming

ABPS – Active bipolar prescaler

WDT – Watchdog Timer

SWD – Serial Wire Debug

Microcontroller Subsystem

Programmable Analog

FPGA Fabric

SRAM SRAM SRAM SRAM SRAM SRAM

SysReg

ENVM

10/100

EMAC

ESRAM

Timer2

Timer1

APB

I2C 2

UART 2

SPI 2

DAC

(SDD)

DAC

(SDD)

PPB

........

............

VersaTiles

3 V

I2C 1

UART 1

SPI 1

IAP PDMA APB EMC

AHB Bus Matrix

EFROM

APB

Sample Sequencing

Engine

Post Processing

Engine

ADC

Analog Compute

Engine

PLL

Supervisor

WDT

OSC

32 KHz

RC +

–

RTC

JTAG

Cortex-M3

SWD

NVIC SysTick

MPU

SD I

Volt Mon.

(ABPS)

Temp.

Mon.

SCB

Curr.

Mon. Comparator

ADC

Volt Mon.

(ABPS)

Temp.

Mon.

SCB

Curr.

Mon. Comparator

............

....

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SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 V

SmartFusion cSoC System Architecture

Note: Architecture for A2F200

Bank 4 Bank 5

Bank 0

Bank 3

Bank 1 Bank 2

PLL/CCC MSS FPGA Analog

ISP AES Decryption Charge Pumps

Embedded NVM

(eNVM)

Cortex-M3 Microcontroller Subsystem (MSS)

Embedded SRAM

(eSRAM)

Embedded FlashROM

(eFROM)

SCB SCB ADC and DAC ADC and DAC SCB SCB

Osc. CCC

SmartFusion Customizable System-on-Chip (cSoC)

VI Revision 14

Product Ordering Codes

Temperature Grade Offerings

Note: *Most devices in the SmartFusion cSoC family can be ordered with the Y suffix. Devices with a package size greater or equal to

5x5 mm are supported. Contact your local Microsemi SoC Products Group sales representative for more information.

SmartFusion cSoC A2F060 A2F200 A2F500

TQ144 C, I – –

PQ208 – C, I C, I

CS288 C, I C, I C, I

FG256 C, I C, I C, I

FG484 – C, I C, I

Notes:

1. C = Commercial Temperature Range: 0°C to 85°C Junction

2. I = Industrial Temperature Range: –40°C to 100°C Junction

A2F200

Part Number

SmartFusion Devices

Speed Grade

–1 = 100 MHz MSS Speed; FPGA Fabric 15% Faster than Standard

= 80 MHz MSS Speed; FPGA Fabric at Standard Speed

CPU Type

M3 = Cortex-M3

Package Type

484 IG

Package Lead Count

256

208

288

484

Application (junction temperature range)

Security Feature*

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Commercial (0 to +85°C)

I = Industrial (–40 to +100°C)

ES = Engineering Silicon (room temperature only)

200,000 System Gates

A2F200 =

60,000 System Gates

A2F060 =

500,000 System Gates

A2F500 =

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

TQ =Thin Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

CS =Chip Scale Package (0.5 mm pitch)

eNVM Size

A= 8 Kbytes

B=16 Kbytes

C=32 Kbytes

D=64 Kbytes

E=128 Kbytes

F=256 Kbytes

G=512 Kbytes

Lead-Free Packaging Options

G = RoHS-Compliant (green) Packaging

Blank = Standard Packaging

Blank

Currently only the following eNVM sizes are available

per device:

A2F500M3 – G

A2F200M3 – F

A2F060M3 – E

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14

SmartFusion Family Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SmartFusion DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

Main and Lower Power Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

FPGA Fabric SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65

Embedded Nonvolatile Memory Block (eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

Embedded FlashROM (eFROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

Programmable Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

Inter-Integrated Circuit (I2C) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

SmartFusion Development Tools

Types of Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

SmartFusion Ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

SmartFusion Programming

In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Typical Programming and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Global I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Microcontroller Subsystem (MSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Analog Front-End (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Analog Front-End Pin-Level Function Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

CS288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

O Microsemi

Table of Contents

Revision 14

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

Microsemi SoC Products Group Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . 6-14

0 Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 1-1

1 – SmartFusion Family Overview

Introduction

The SmartFusion® family of cSoCs builds on the technology first introduced with the Fusion mixed signal

FPGAs. SmartFusion cSoCs are made possible by integrating FPGA technology with programmable

high-performance analog and hardened ARM Cortex-M3 microcontroller blocks on a flash semiconductor

process. The SmartFusion cSoC takes its name from the fact that these three discrete technologies are

integrated on a single chip, enabling the lowest cost of ownership and smallest footprint solution to you.

General Description

Microcontroller Subsystem (MSS)

The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are

interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor,

FPGA fabric master, Ethernet media access controller (MAC), when available, and peripheral DMA

(PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded nonvolatile

memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller (EMC), and

analog compute engine (ACE) blocks.

SmartFusion cSoCs of different densities offer various sets of integrated peripherals. Available

peripherals include SPI, I2C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet

MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA

controller (PDMA).

Programmable Analog

Analog Front-End (AFE)

SmartFusion cSoCs offer an enhanced analog front-end compared to Fusion devices. The successive

approximation register analog-to-digital converters (SAR ADC) are similar to those found on Fusion

devices. SmartFusion cSoC also adds first order sigma-delta digital-to-analog converters (SDD DAC).

SmartFusion cSoCs can handle multiple analog signals simultaneously with its signal conditioning blocks

(SCBs). SCBs are made of a combination of active bipolar prescalers (ABPS), comparators, current

monitors and temperature monitors. ABPS modules allow larger bipolar voltages to be fed to the ADC.

Current monitors take the voltage across an external sense resistor and convert it to a voltage suitable

for the ADC input range. Similarly, the temperature monitor reads the current through an external PN-

junction (diode or transistor) and converts it internally for the ADC. The SCB also includes comparators

to monitor fast signal thresholds without using the ADC. The output of the comparators can be fed to the

analog compute engine or the ADC.

Analog Compute Engine (ACE)

The mixed signal blocks found in SmartFusion cSoCs are controlled and connected to the rest of the

system via a dedicated processor called the analog compute engine (ACE). The role of the ACE is to

offload control of the analog blocks from the Cortex-M3, thus offering faster throughput or better power

consumption compared to a system where the main processor is in charge of monitoring the analog

resources. The ACE is built to handle sampling, sequencing, and post-processing of the ADCs, DACs,

and SCBs.

O Microsemi

SmartFusion Family Overview

1-2 Revision 14

ProASIC3 FPGA Fabric

The SmartFusion cSoC family, based on the proven, low power, firm-error immune ProASIC®3 flash

FPGA architecture, benefits from the advantages only flash-based devices offer:

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-

based SmartFusion cSoCs are Instant On and do not need to be loaded from an external boot PROM at

each power-up. On-board security mechanisms prevent access to the programming information and

enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system

programming (ISP) to support future design iterations and critical field upgrades, with confidence that

valuable IP cannot be compromised or copied. Secure ISP can be performed using the industry standard

AES algorithm with MAC data authentication on the device.

Low Power

Flash-based SmartFusion cSoCs exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. With SmartFusion cSoCs, there is no power-on current

and no high current transition, both of which are common with SRAM-based FPGAs.

SmartFusion cSoCs also have low dynamic power consumption and support very low power time-

keeping mode, offering further power savings.

Security

As the nonvolatile, flash-based SmartFusion cSoC family requires no boot PROM, there is no vulnerable

external bitstream. SmartFusion cSoCs incorporate FlashLock®, which provides a unique combination of

reprogrammability and design security without external overhead, advantages that only a device with

nonvolatile flash programming can offer.

SmartFusion cSoCs utilize a 128-bit flash-based key lock and a separate AES key to provide security for

programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted

prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the AES-

128 block cipher encryption standard (FIPS Publication 192).

SmartFusion cSoCs with AES-based security are designed to provide protection for remote field updates

over public networks, such as the Internet, and help to ensure that valuable IP remains out of the hands

of system overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA

configuration data of a programmed Fusion device cannot be read back, although secure design

verification is possible. During design, the user controls and defines both internal and external access to

the flash memory blocks.

Security, built into the FPGA fabric, is an inherent component of the SmartFusion cSoC family. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. SmartFusion cSoCs, with FlashLock and AES security,

are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is

protected with industry standard security measures, making remote ISP feasible. A SmartFusion cSoC

provides the highest security available for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based SmartFusion

cSoCs do not require system configuration components such as electrically erasable programmable

read-only memories (EEPROMs) or microcontrollers to load device configuration data during power-up.

This reduces bill-of-materials costs and PCB area, and increases system security and reliability.

Instant On

Flash-based SmartFusion cSoCs are Instant On. Instant On SmartFusion cSoCs greatly simplify total

system design and reduce total system cost by eliminating the need for complex programmable logic

devices (CPLDs). SmartFusion Instant On clocking (PLLs) replace off-chip clocking resources. In

addition, glitches and brownouts in system power will not corrupt the SmartFusion flash configuration.

Unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored.

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 1-3

This enables reduction or complete removal of expensive voltage monitor and brownout detection

devices from the PCB design. Flash-based SmartFusion cSoCs simplify total system design and reduce

cost and design risk, while increasing system reliability.

Immunity to Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, strike a

configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O configuration behavior in an unpredictable

way.

Another source of radiation-induced firm errors is alpha particles. For alpha radiation to cause a soft or

firm error, its source must be in very close proximity to the affected circuit. The alpha source must be in

the package molding compound or in the die itself. While low-alpha molding compounds are being used

increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.

Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not occur in SmartFusion cSoCs. Once it is programmed, the

flash cell configuration element of SmartFusion cSoCs cannot be altered by high energy neutrons and is

therefore immune to errors from them. Recoverable (or soft) errors occur in the user data SRAMs of all

FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry

built into the FPGA fabric.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

The I/Os are controlled by the JTAG Boundary Scan register during programming, except for the analog

pins (AC, AT and AV). The Boundary Scan register of the AG pin can be used to enable/disable the gate

driver in software v9.0.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-1 on page 1-4).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

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SmartFusion Family Overview

1-4 Revision 14

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States During programming are saved to the ADB and resulting programming files after

completing programming file generation.

Figure 1-1 • I/O States During Programming Window

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-1

2 – SmartFusion DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond the operating conditions listed in Table 2-1 may cause permanent damage to the

device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-3 on page 2-3 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPP Programming voltage –0.3 to 3.75 V

VCCPLLx Analog power supply (PLL) –0.3 to 1.65 V

VCCFPGAIOBx DC FPGA I/O buffer supply voltage –0.3 to 3.75 V

VCCMSSIOBx DC MSS I/O buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V

(when I/O hot insertion mode is enabled)

–0.3 V to (VCCxxxxIOBx + 1 V) or 3.6 V,

whichever voltage is lower (when I/O hot-

insertion mode is disabled)

VCC33A Analog clean 3.3 V supply to the analog

circuitry

–0.3 to 3.75 V

VCC33ADCx Analog 3.3 V supply to ADC –0.3 to 3.75 V

VCC33AP Analog clean 3.3 V supply to the charge pump –0.3 to 3.75V

VCC33SDDx Analog 3.3 V supply to the sigma-delta DAC –0.3 to 3.75V

VAREFx Voltage reference for ADC 1.0 to 3.75 V

VCCRCOSC Analog supply to the integrated RC oscillator –0.3 to 3.75 V

VDDBAT External battery supply –0.3 to 3.75 V

VCCMAINXTAL Analog supply to the main crystal oscillator –0.3 to 3.75 V

VCCLPXTAL Analog supply to the low power 32 kHz crystal

oscillator

–0.3 to 3.75 V

VCCENVM Embedded nonvolatile memory supply –0.3 to 1.65 V

VCCESRAM Embedded SRAM supply –0.3 to 1.65 V

VCC15A Analog 1.5 V supply to the analog circuitry –0.3 to 1.65 V

VCC15ADCx Analog 1.5 V supply to the ADC –0.3 to 1.65 V

TSTG1Storage temperature –65 to +150 °C

TJ1Junction temperature 125 °C

Notes:

1. For flash programming and retention maximum limits, refer to Table 2-4 on page 2-4. For recommended operating

conditions, refer to Table 2-3 on page 2-3.

2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-5 on page 2-4.

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SmartFusion DC and Switching Characteristics

2-2 Revision 14

Table 2-2 • Analog Maximum Ratings

Parameter Conditions Min. Max. Units

ABPS[n] pad voltage (relative to ground) GDEC[1:0] = 00 (±15.36 V range)

Absolute maximum –11.5 14.4 V

Recommended –11 14 V

GDEC[1:0] = 01 (±10.24 V range) –11.5 12 V

GDEC[1:0] = 10 (±5.12 V range) –6 6 V

GDEC[1:0] = 11 (±2.56 V range) –3 3 V

CM[n] pad voltage relative to ground) CMB_DI_ON = 0 (ADC isolated)

COMP_EN = 0 (comparator off, for the

associated even-numbered comparator)

Absolute maximum –0.3 14.4 V

Recommended –0.3 14 V

CMB_DI_ON = 0 (ADC isolated)

COMP_EN = 1 (comparator on)

–0.3 3 V

TMB_DI_ON = 1 (direct ADC in) –0.3 3 V

TM[n] pad voltage (relative to ground) TMB_DI_ON = 0 (ADC isolated)

COMP_EN = 1(comparator on)

–0.3 3 V

TMB_DI_ON = 1 (direct ADC in) –0.3 3 V

ADC[n] pad voltage (relative to ground) –0.3 3.6 V

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-3

Table 2-3 • Recommended Operating Conditions5,6

Symbol Parameter1Commercial Industrial Units

TJ Junction temperature 0 to +85 –40 to +100 °C

VCC 21.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.425 to 3.6 1.425 to 3.6 V

VPP Programming voltage Programming mode3 3.15 to 3.45 3.15 to 3.45 V

Operation4 0 to 3.6 0 to 3.6 V

VCCPLLx Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575V

VCCFPGAIOBx/

VCCMSSIOBx5

1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

VCC33A6Analog clean 3.3 V supply to the analog circuitry 3.15 to 3.45 3.15 to 3.45 V

VCC33ADCx6Analog 3.3 V supply to ADC 3.15 to 3.45 3.15 to 3.45 V

VCC33AP6Analog clean 3.3 V supply to the charge pump 3.15 to 3.45 3.15 to 3.45 V

VCC33SDDx6Analog 3.3 V supply to sigma-delta DAC 3.15 to 3.45 3.15 to 3.45 V

VAREFx Voltage reference for ADC 2.527 to 3.3 2.527 to 3.3 V

VCCRCOSC Analog supply to the integrated RC oscillator 3.15 to 3.45 3.15 to 3.45 V

VDDBAT External battery supply 2.7 to 3.63 2.7 to 3.63 V

VCCMAINXTAL6Analog supply to the main crystal oscillator 3.15 to 3.45 3.15 to 3.45 V

VCCLPXTAL6Analog supply to the low power 32 KHz crystal

oscillator

3.15 to 3.45 3.15 to 3.45 V

VCCENVM Embedded nonvolatile memory supply 1.425 to 1.575 1.425 to 1.575 V

VCCESRAM Embedded SRAM supply 1.425 to 1.575 1.425 to 1.575 V

VCC15A2Analog 1.5 V supply to the analog circuitry 1.425 to 1.575 1.425 to 1.575 V

VCC15ADCx2 Analog 1.5 V supply to the ADC 1.425 to 1.575 1.425 to 1.575 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,

VCC15A, and VCC15ADCx.

3. The Programming temperature range supported is Tambient = 0°C to 85°C.

4. VPP can be left floating during operation (not programming mode).

5. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-19 on page 2-23. VCCxxxxIOBx should be at the same voltage within a given I/O bank.

6. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,

VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.

O Microsemi

SmartFusion DC and Switching Characteristics

2-4 Revision 14

Power Supply Sequencing Requirement

SmartFusion cSoCs have an on-chip 1.5 V regulator, but usage of an external 1.5 V supply is also

allowed while the on-chip regulator is disabled. In that case, the 3.3 V supplies (VCC33A, etc.) should be

powered before 1.5 V (VCC, etc.) supplies. The 1.5 V supplies should be enabled only after 3.3 V

supplies reach a value higher than 2.7 V.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every SmartFusion cSoC. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-6.

There are five regions to consider during power-up.

SmartFusion I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCxxxxIOBx are above the minimum specified trip points (Figure 2-1 on page 2-6).

2. VCCxxxxIOBx > VCC – 0.75 V (typical)

3. Chip is in the SoC Mode.

Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits

Product Grade Storage Temperature Element

Grade Programming

Cycles Retention

Commercial Min. TJ = 0°C FPGA/FlashROM 500 20 years

Max. TJ = 85°C Embedded Flash < 1,000 20 years

< 10,000 10 years

< 15,000 5 years

Industrial Min. TJ = –40°C FPGA/FlashROM 500 20 years

Max. TJ = 100°C Embedded Flash < 1,000 20 years

< 10,000 10 years

< 15,000 5 years

Table 2-5 • Overshoot and Undershoot Limits 1

VCCxxxxIOBx

Average VCCxxxxIOBx–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle2

Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-5

VCCxxxxIOBx Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the

following:

• By default, during programming I/Os become tristated and weakly pulled up to VCCxxxxIOBx.

You can modify the I/O states during programming in FlashPro. For more details, refer to

"Specifying I/O States During Programming" on page 1-3.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

The Microsemi SoC Products Group recommends using monotonic power supplies or voltage regulators

to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and

VCCPLLx exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case

(see Figure 2-1 on page 2-6 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation

OMicmsemi Vcc = VCCxxxxlOBx 4 VT Ex

SmartFusion DC and Switching Characteristics

2-6 Revision 14

Figure 2-1 • I/O State as a Function of VCCxxxxIOBx and VCC Voltage Levels

VCCxxxxIOBx

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCxxxxIOBx

/ V

are

below specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Min VCCxxxxIOBx datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Activation trip point:

= 0.9 V ± 0.3 V

Deactivation trip point:

= 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCxxxxIOBx

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCxxxxIOBx + VT

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-7

Thermal Characteristics

Introduction

The temperature variable in the SoC Products Group Designer software refers to the junction

temperature, not the ambient, case, or board temperatures. This is an important distinction because

dynamic and static power consumption will cause the chip's junction temperature to be higher than the

ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal

resistance, temperature gradient, and power.

EQ 1

EQ 2

EQ 3

where

JA = Junction-to-air thermal resistance

JB = Junction-to-board thermal resistance

JC = Junction-to-case thermal resistance

TJ= Junction temperature

TA= Ambient temperature

TB= Board temperature (measured 1.0 mm away from the

package edge)

TC= Case temperature

P = Total power dissipated by the device

Table 2-6 • Package Thermal Resistance

Product

JA

JC JB UnitsStill Air 1.0 m/s 2.5 m/s

A2F200M3F-FG256 33.7 30.0 28.3 9.3 24.8 °C/W

A2F200M3F-FG484 21.8 18.2 16.7 7.7 16.8 °C/W

A2F200M3F-CS288 26.6 20.2 18.1 7.3 9.4 °C/W

A2F200M3F-PQG208I 38.5 34.6 33.1 0.7 31.6 °C/W

JA

TJA

–

------------------=

JB

TJTB

–

-------------------=

JC

TJTC

–

-------------------=

O Microsemi

SmartFusion DC and Switching Characteristics

2-8 Revision 14

Theta-JA

Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by

JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with

caution but is useful for comparing the thermal performance of one package to another.

A sample calculation showing the maximum power dissipation allowed for the A2F200-FG484 package

under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:

EQ 4

where

EQ 5

The power consumption of a device can be calculated using the Microsemi SoC Products Group power

calculator. The device's power consumption must be lower than the calculated maximum power

dissipation by the package. If the power consumption is higher than the device's maximum allowable

power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must

be increased.

Theta-JB

Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the

surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance

from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a

means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a

JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.

Theta-JC

Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the

surface of the chip to the top or bottom surface of the package. It is applicable for packages used with

external heat sinks. Constant temperature is applied to the surface in consideration and acts as a

boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through

the surface in consideration.

Calculation for Heat Sink

For example, in a design implemented in an A2F200-FG484 package with 2.5 m/s airflow, the power

consumption value using the power calculator is 3.00 W. The user-dependent Ta and T

j are given as

follows:

From the datasheet:

JA = 19.00°C/W (taken from Table 2-6 on page 2-7).

TA= 75.00°C

TJ= 100.00°C

TA= 70.00°C

JA = 17.00°C/W

JC = 8.28°C/W

Maximum Power Allowed TJ(MAX) TA(MAX)

–

JA

---------------------------------------------=

Maximum Power Allowed 100.00°C 75.00°C–

19.00°C/W

---------------------------------------------------- 1.3 W==

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-9

EQ 6

The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the

airflow where the device is mounted should be increased. The design's total junction-to-air thermal

resistance requirement can be estimated by EQ 7:

EQ 7

Determining the heat sink's thermal performance proceeds as follows:

EQ 8

where

EQ 9

A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat

sinks is a function of airflow. The heat sink performance can be significantly improved with increased

airflow.

Carefully estimating thermal resistance is important in the long-term reliability of an FPGA. Design

engineers should always correlate the power consumption of the device with the maximum allowable

power dissipation of the package selected for that device.

Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard

(JESD-51) and assumptions made in building the model. It may not be realized in actual

application and therefore should be used with a degree of caution. Junction-to-case thermal

resistance assumes that all power is dissipated through the case.

Temperature and Voltage Derating Factors

JA = 0.37°C/W

= Thermal resistance of the interface material between

the case and the heat sink, usually provided by the

thermal interface manufacturer

SA = Thermal resistance of the heat sink in °C/W

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 85°C, worst-case VCC = 1.425 V)

Array

Voltage VCC

(V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 100°C

1.425 0.86 0.91 0.93 0.98 1.00 1.02

1.500 0.81 0.86 0.88 0.93 0.95 0.96

1.575 0.78 0.83 0.85 0.90 0.91 0.93

PTJTA

–

JA

-------------------100°C 70°C–

17.00 W

------------------------------------1.76 W== =

JA(total)

TJTA

–

-------------------100°C 70°C–

3.00 W

------------------------------------10.00°C/W== =

JA(TOTAL) JC CS SA

++=

SA JA(TOTAL) JC

–CS

–=

SA 13.33°C/W 8.28°C/W–0.37°C/W–5.01°C/W==

O Microsemi

SmartFusion DC and Switching Characteristics

2-10 Revision 14

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 2-8 • Power Supplies Configuration

Modes and Power

Supplies

VCCxxxxIOBx

VCCFPGAIOBx

VCCMSSIOBx

VCC33A / VCC33ADCx

VCC33AP / VCC33SDDx

VCCMAINXTAL / VCCLPXTAL

VCC / VCC15A / VCC15ADCx

VCCPLLx, VCCENVM,

VCCESRAM

VDDBAT

VCCRCOSC

VJTAG

VPP

eNVM (reset/off)

LPXTAL (enable/disable)

MAINXTAL (enable/disable)

Time Keeping mode 0 V 0 V 0 V 3.3 V 0 V 0 V 0 V Off Enable Disable

Standby mode On* 3.3 V 1.5 V N/A 3.3 V N/A N/A Reset Enable Disable

SoC mode On* 3.3 V 1.5 V N/A 3.3 V N/A N/A On Enable Enable

Note: *On means proper voltage is applied. Refer to Table 2-3 on page 2-3 for recommended operating conditions.

Table 2-9 • Quiescent Supply Current Characteristics

Parameter Modes

A2F060 A2F200 A2F500

1.5 V

Domain

3.3 V

Domain

1.5 V

Domain

3.3 V

Domain

1.5 V

Domain

3.3 V

Domain

IDC1 SoC mode 3 mA 2 mA 7 mA 4 mA 16.5 mA 4 mA

IDC2 Standby mode 3 mA 2 mA 7 mA 4 mA 16.5 mA 4 mA

IDC3 Time Keeping mode N/A 10 µA N/A 10 µA N/A 10 µA

Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

VCCFPGAIOBx (V)

Static Power

PDC7 (mW)

Dynamic Power PAC9

(µW/MHz)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.55

2.5 V LVCMOS 2.5 – 5.97

1.8 V LVCMOS 1.8 – 2.88

1.5 V LVCMOS (JESD8-11) 1.5 – 2.33

3.3 V PCI 3.3 – 19.21

3.3 V PCI-X 3.3 – 19.21

Differential

LVDS 2.5 2.26 0.82

LVPECL 3.3 5.72 1.16

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-11

Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to MSS I/O Banks

VCCMSSIOBx (V)

Static Power

PDC7 (mW)

Dynamic Power

PAC9 (µW/MHz)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.21

3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger 3.3 – 20.00

2.5 V LVCMOS 2.5 – 5.55

2.5 V LVCMOS – Schmitt trigger 2.5 – 7.03

1.8 V LVCMOS 1.8 – 2.61

1.8 V LVCMOS – Schmitt trigger 1.8 – 2.72

1.5 V LVCMOS (JESD8-11) 1.5 – 1.98

1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 1.93

Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings*

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

CLOAD (pF)

VCCFPGAIOBx

(V)

Static Power

PDC8 (mW)

Dynamic Power

PAC10 (µW/MHz)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 475.66

2.5 V LVCMOS 35 2.5 – 270.50

1.8 V LVCMOS 35 1.8 – 152.17

1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.44

3.3 V PCI 10 3.3 – 202.69

3.3 V PCI-X 10 3.3 – 202.69

Differential

LVDS – 2.5 7.74 88.26

LVPECL – 3.3 19.54 164.99

Note: *Dynamic power consumption is given for standard load and software default drive strength and output slew.

Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings

Applicable to MSS I/O Banks

CLOAD (pF) VCCMSSIOBx (V)

Static Power

PDC8 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS 10 3.3 – 155.65

2.5 V LVCMOS 10 2.5 – 88.23

1.8 V LVCMOS 10 1.8 – 45.03

1.5 V LVCMOS (JESD8-11) 10 1.5 – 31.01

O Microsemi

SmartFusion DC and Switching Characteristics

2-12 Revision 14

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs

Parameter Definition

Power Supply Device

UnitsName Domain A2F060 A2F200 A2F500

PAC1 Clock contribution of a Global Rib VCC 1.5 V 3.39 3.40 5.05 µW/MHz

PAC2 Clock contribution of a Global Spine VCC 1.5 V 1.14 1.83 2.50 µW/MHz

PAC3 Clock contribution of a VersaTile

row

VCC 1.5 V 1.15 1.15 1.15 µW/MHz

PAC4 Clock contribution of a VersaTile

used as a sequential module

VCC 1.5 V 0.12 0.12 0.12 µW/MHz

PAC5 First contribution of a VersaTile

used as a sequential module

VCC 1.5 V 0.07 0.07 0.07 µW/MHz

PAC6 Second contribution of a VersaTile

used as a sequential module

VCC 1.5 V 0.29 0.29 0.29 µW/MHz

PAC7 Contribution of a VersaTile used as

a combinatorial module

VCC 1.5 V 0.29 0.29 0.29 µW/MHz

PAC8 Average contribution of a routing net VCC 1.5 V 1.04 0.79 0.79 µW/MHz

PAC9 Contribution of an I/O input pin

(standard dependent)

VCCxxxxIOBx/VCC See Ta b l e 2 - 1 0 and Table 2-11 on page 2-11

PAC10 Contribution of an I/O output pin

(standard dependent)

VCCxxxxIOBx/VCC See Tab l e 2- 12 and Table 2-13 on page 2-11

PAC11 Average contribution of a RAM

block during a read operation

VCC 1.5 V 25.00 µW/MHz

PAC12 Average contribution of a RAM

block during a write operation

VCC 1.5 V 30.00 µW/MHz

PAC13 Dynamic Contribution for PLL VCC 1.5 V 2.60 µW/MHz

PAC15 Contribution of NVM block during a

read operation (F < 33MHz)

VCC 1.5 V 358.00 µW/MHz

PAC16 1st contribution of NVM block during

a read operation (F > 33MHz)

VCC 1.5 V 12.88 mW

PAC17 2nd contribution of NVM block

during a read operation (F > 33MHz)

VCC 1.5 V 4.80 µW/MHz

PAC18 Main Crystal Oscillator contribution VCCMAINXTAL 3.3 V 1.98 mW

PAC19a RC Oscillator contribution VCCRCOSC 3.3 V 3.30 mW

PAC19b RC Oscillator contribution VCC 1.5 V 3.00 mW

PAC20a Analog Block Dynamic Power

Contribution of the ADC

VCC33ADCx 3.3 V 8.25 mW

PAC20b Analog Block Dynamic Power

Contribution of the ADC

VCC15ADCx 1.5 V 3.00 mW

PAC21 Low Power Crystal Oscillator

contribution

VCCLPXTAL 3.3 V 33.00 µW

PAC22 MSS Dynamic Power Contribution –

Running Drysthone at 100MHz1

VCC 1.5 V 67.50 mW

PAC23 Temperature Monitor Power

Contribution

See Table 2-94 on

page 2-79

–1.23mW

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-13

PAC24 Current Monitor Power Contribution See Table 2-93 on

page 2-78

–1.03mW

PAC25 ABPS Power Contribution See Table 2-96 on

page 2-82

–0.70mW

PAC26 Sigma-Delta DAC Power

Contribution2

See Table 2-98 on

page 2-85

–0.58mW

PAC27 Comparator Power Contribution See Table 2-97 on

page 2-84

–1.02mW

PAC28 Voltage Regulator Power

Contribution3

See Table 2-99 on

page 2-87

–36.30mW

Notes:

1. For a different use of MSS peripherals and resources, refer to SmartPower.

2. Assumes Input = Half Scale Operation mode.

3. Assumes 100 mA load on 1.5 V domain.

Table 2-15 • Different Components Contributing to the Static Power Consumption in SmartFusion cSoCs

Parameter Definition

Power Supply Device

UnitsName Domain A2F060 A2F200 A2F200

PDC1 Core static power contribution in

SoC mode

VCC 1.5 V 11.10 23.70 37.95 mW

PDC2 Device static power contribution in

Standby Mode

See Tab le 2- 8 o n

page 2-10

– 11.10 23.70 37.95 mW

PDC3 Device static power contribution in

Time Keeping mode

See Tab le 2- 8 o n

page 2-10

3.3 V 33.00 33.00 33.00 µW

PDC7 Static contribution per input pin

(standard dependent contribution)

VCCxxxxIOBx/VCC See Tab le 2 - 1 0 and Table 2-11 on page 2-11.

PDC8 Static contribution per output pin

(standard dependent contribution)

VCCxxxxIOBx/VCC See Table 2-12 and Table 2-13 on page 2-11.

PDC9 Static contribution per PLL VCC 1.5 V 2.55 2.55 2.55 mW

Table 2-16 • eNVM Dynamic Power Consumption

Parameter Description Condition Min. Typ. Max. Units

eNVM System eNVM array operating power Idle 795 µA

Read operation See Table 2-14 on page 2-12.

Erase 900 µA

Write 900 µA

PNVMCTRL eNVM controller operating power 20 µW/MHz

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs

Parameter Definition

Power Supply Device

UnitsName Domain A2F060 A2F200 A2F500

O Microsemi

SmartFusion DC and Switching Characteristics

2-14 Revision 14

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

• The number of PLLs/CCCs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

• The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• The number of eNVM blocks used in the design

• The analog block used in the design, including the temperature monitor, current monitor, ABPS,

sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal

oscillator

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-17 on

page 2-18.

• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-18 on

page 2-18.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-18 on page 2-18.

• Read rate to the eNVM blocks

The calculation should be repeated for each clock domain defined in the design.

Methodology

Total Power Consumption—PTOTAL

SoC Mode, Standby Mode, and Time Keeping Mode.

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

SoC Mode

PSTAT = PDC1 + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) + (NPLLS * PDC9)

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

NPLLS is the number of PLLs available in the device.

Standby Mode

PSTAT = PDC2

Time Keeping Mode

PSTAT = PDC3

Total Dynamic Power Consumption—PDYN

SoC Mode

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PeNVM +

PXTL-OSC + PRC-OSC + PAB + PLPXTAL-OSC + PMSS

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-15

Standby Mode

PDYN = PRC-OSC + PLPXTAL-OSC

Time Keeping Mode

PDYN = PLPXTAL-OSC

Global Clock Dynamic Contribution—PCLOCK

SoC Mode

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in the

"Device Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.

NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Device

Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

Standby Mode and Time Keeping Mode

PCLOCK = 0 W

Sequential Cells Dynamic Contribution—PS-CELL

SoC Mode

PS-CELL = NS-CELL * (PAC5 + (1 / 2) * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the global clock signal frequency.

Standby Mode and Time Keeping Mode

PS-CELL = 0 W

Combinatorial Cells Dynamic Contribution—PC-CELL

SoC Mode

PC-CELL = NC-CELL* (1 / 2) * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the global clock signal frequency.

Standby Mode and Time Keeping Mode

PC-CELL = 0 W

Routing Net Dynamic Contribution—PNET

SoC Mode

PNET = (NS-CELL + NC-CELL) * (1 / 2) * PAC8 * FCLK

NS-CELL is the number VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the frequency of the clock driving the logic including these nets.

O Microsemi

SmartFusion DC and Switching Characteristics

2-16 Revision 14

Standby Mode and Time Keeping Mode

PNET = 0 W

I/O Input Buffer Dynamic Contribution—PINPUTS

SoC Mode

PINPUTS = NINPUTS * (2 / 2) * PAC9 * FCLK

Where:

NINPUTS is the number of I/O input buffers used in the design.

2 is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the global clock signal frequency.

Standby Mode and Time Keeping Mode

PINPUTS = 0 W

I/O Output Buffer Dynamic Contribution—POUTPUTS

SoC Mode

POUTPUTS = NOUTPUTS * (2 / 2) * 1 * PAC10 * FCLK

Where:

NOUTPUTS is the number of I/O output buffers used in the design.

2 is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18.

1 is the I/O buffer enable rate—guidelines are provided in Table 2-18 on page 2-18.

FCLK is the global clock signal frequency.

Standby Mode and Time Keeping Mode

POUTPUTS = 0 W

FPGA Fabric SRAM Dynamic Contribution—PMEMORY

SoC Mode

PMEMORY = (NBLOCKS * PAC11 * 2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * 3 * FWRITE-CLOCK)

Where:

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

2 is the RAM enable rate for read operations—guidelines are provided in Table 2-18 on

page 2-18.

3 the RAM enable rate for write operations—guidelines are provided in Table 2-18 on page 2-18.

FWRITE-CLOCK is the memory write clock frequency.

Standby Mode and Time Keeping Mode

PMEMORY = 0 W

PLL/CCC Dynamic Contribution—PPLL

SoC Mode

PPLL = PAC13 * FCLKOUT

FCLKIN is the input clock frequency.

FCLKOUT is the output clock frequency.1

Standby Mode and Time Keeping Mode

1.The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL

contribution.

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-17

PPLL = 0 W

Embedded Nonvolatile Memory Dynamic Contribution—PeNVM

SoC Mode

The eNVM dynamic power consumption is a piecewise linear function of frequency.

PeNVM = NeNVM-BLOCKS * 4 * PAC15 * FREAD-eNVM when FREAD-eNVM 33 MHz,

PeNVM = NeNVM-BLOCKS * 4 *(PAC16 + PAC17 * FREAD-eNVM) when FREAD-eNVM > 33 MHz

Where:

NeNVM-BLOCKS is the number of eNVM blocks used in the design.

4 is the eNVM enable rate for read operations. Default is 0 (eNVM mainly in idle state).

FREAD-eNVM is the eNVM read clock frequency.

Standby Mode and Time Keeping Mode

PeNVM = 0 W

Main Crystal Oscillator Dynamic Contribution—PXTL-OSC

SoC Mode

PXTL-OSC = PAC18

Standby Mode

PXTL-OSC = 0 W

Time Keeping Mode

PXTL-OSC = 0 W

Low Power Oscillator Crystal Dynamic Contribution—PLPXTAL-OSC

Operating, Standby, and Time Keeping Mode

PLPXTAL-OSC = PAC21

RC Oscillator Dynamic Contribution—PRC-OSC

SoC Mode

PRC-OSC = PAC19A + PAC19B

Standby Mode and Time Keeping Mode

PRC-OSC = 0 W

Analog System Dynamic Contribution—PAB

SoC Mode

PAB = PAC23 * NTM + PAC24 * NCM + PAC25 * NABPS + PAC26 * NSDD + PAC27 * NCOMP + PADC * NADC

+ PVR

Where:

NCM is the number of current monitor blocks

NTM is the number of temperature monitor blocks

NSDD is the number of sigma-delta DAC blocks

NABPS is the number of ABPS blocks

NADC is the number of ADC blocks

NCOMP is the number of comparator blocks

PVR= PAC28

PADC= PAC20A + PAC20B

O Microsemi uuuu

SmartFusion DC and Switching Characteristics

2-18 Revision 14

Microcontroller Subsystem Dynamic Contribution—PMSS

SoC Mode

PMSS = PAC22

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some

examples:

• The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock

frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

non-tristate output buffers are used, the enable rate should be 100%.

Table 2-17 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

1 Toggle rate of VersaTile outputs 10%

2 I/O buffer toggle rate 10%

Table 2-18 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

1 I/O output buffer enable rate Toggle rate of the logic driving the

output buffer

2 FPGA fabric SRAM enable rate for read

operations

12.5%

3FPGA fabric SRAM enable rate for write

operations

12.5%

4 eNVM enable rate for read operations < 5%

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-19

User I/O Characteristics

Timing Model

Figure 2-2 • Timing Model

Operating Conditions: –1 Speed, Commercial Temperature Range (TJ = 85°C),

Worst Case VCC = 1.425 V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (applicable to

FPGA /O bank, EMC pin)

LVPECL

(Applicable

to FPGA

I/O Bank,

EMC pin)

LVDS,

BLVDS,

M-LVDS

(Applicable for

FPGA I/O Bank,

EMC pin)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTLOutput drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 V Output drive strength = 4 mA

High slew rate

LVTTLOutput drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

= 0.57 ns t

= 0.49 ns

= 1.53 ns

= 0.89 ns t

= 2.81 ns (FPGA I/O Bank, EMC pin)

= 0.51 ns

= 3.87 ns (FPGA I/O Bank, EMC pin)

= 0.48 ns t

= 4.13 ns (FPGA I/O Bank, EMC pin)

= 0.48 ns

= 0.81 ns

(FPGA I/O Bank, EMC pin)

CLKQ

= 0.56 ns t

OCLKQ

= 0.60 ns

SUD

= 0.44 ns t

OSUD

= 0.32 ns

= 2.81 ns

(FPGA I/O Bank, EMC pin)

= 0.81 ns (FPGA I/O Bank, EMC pin)

= 1.55 ns

CLKQ

= 0.56 ns

SUD

= 0.44 ns

= 0.81 ns

(FPGA I/O Bank, EMC pin)

ICLKQ

= 0.24 ns

ISUD

= 0.27 ns

= 1.46 ns

O Microsemi W J

SmartFusion DC and Switching Characteristics

2-20 Revision 14

Figure 2-3 • Input Buffer Timing Model and Delays (example)

(R)

PAD

trip

GND t

(F)

trip

50%

VIH

VCC

VIL

DOUT

(R)

DIN

GND t

DOUT

(F)

50%50%

VCC

PAD Y

CLK

I/O Interface

DIN

To Array

= MAX(t

(R), t

(F))

DIN

= MAX(t

DIN

(R), t

DIN

(F))

o Microsemi J F III—M—

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-21

Figure 2-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

O Microsemi

SmartFusion DC and Switching Characteristics

2-22 Revision 14

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% VCCxxxxIOBx

tZL

Vtrip

50%

tHZ

90% VCCxxxxIOBx

tZH

Vtrip

50% 50% tLZ

50%

EOUT

PAD

E50%

tEOUT (R)

50%tEOUT (F)

PAD

DOUT

EOUT

I/O Interface

tEOUT

tZLS

Vtrip

50%

tZHS

Vtrip

50%

EOUT

PAD

E50% 50%

tEOUT (R) tEOUT (F)

50%

VCC

VCCxxxxIOBx

VCC

VOH

VOL

tZL, tZH, tHZ, tLZ, tZLS, tZHS

tEOUT = MAX(tEOUT(r), tEOUT(f))

G Microsemi Slew 0L OH

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-23

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial

Conditions—Software Default Settings

Applicable to FPGA I/O Banks

I/O Standard

Drive

Strgth.

Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min.

Max.

Min.

Max.

Min.

VmAmA

3.3VLVTTL/

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 *

VCCxxxxIOBx

0.65*

VCCxxxxIOBx

3.6 0.45 VCCxxxxIOBx

– 0.45

12 12

1.5 V LVCMOS 12 mA High –0.3 0.35 *

VCCxxxxIOBx

0.65*

VCCxxxxIOBx

3.6 0.25 *

VCCxxxxIOBx

0.75*

VCCxxxxIOBx

12 12

3.3 V PCI Per PCI specifications

3.3 V PCI-X Per PCI-X specifications

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output slew rate can be extracted by the IBIS Models.

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial

Conditions—Software Default Settings

Applicable to MSS I/O Banks

I/O Standard

Drive

Strgth.

Slew

Rate

VIL VIH VOL VOH IOL1IOH1

Min.

Max.

Min.

Max.

Min.

VmAmA

3.3VLVTTL/

3.3 V LVCMOS

8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8

2.5 V LVCMOS 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8

1.8 V LVCMOS 4 mA High –0.3 0.35*

VCCxxxxIOBx

0.65*

VCCxxxxIOBx

3.6 0.45 VCCxxxxIOBx

– 0.45

1.5 V LVCMOS 2 mA High –0.3 0.35*

VCCxxxxIOBx

0.65*

VCCxxxxIOBx

3.6 0.25*

VCCxxxxIOBx

0.75*

VCCxxxxIOBx

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output slew rate can be extracted by the IBIS Models.

O Microsemi

SmartFusion DC and Switching Characteristics

2-24 Revision 14

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial Conditions in all I/O Bank Types

DC I/O Standards

Commercial

IIL IIH

µA µA

3.3 V LVTTL / 3.3 V LVCMOS 15 15

2.5 V LVCMOS 15 15

1.8 V LVCMOS 15 15

1.5 V LVCMOS 15 15

3.3 V PCI 15 15

3.3 V PCI-X 15 15

Table 2-22 • Summary of AC Measuring Points Applicable to All I/O Bank Types

Standard Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS 1.4 V

2.5 V LVCMOS 1.2 V

1.8 V LVCMOS 0.90 V

1.5 V LVCMOS 0.75 V

3.3 V PCI 0.285 * VCCxxxxIOBx (RR)

0.615 * VCCxxxxIOBx (FF)

3.3 V PCI-X 0.285 * VCCxxxxIOBx (RR)

0.615 * VCCxxxxIOBx (FF)

LVDS Cross point

LVPECL Cross point

Table 2-23 • I/O AC Parameter Definitions

Parameter Parameter Definition

tDP Data to pad delay through the output buffer

tPY Pad to data delay through the input buffer

tDOUT Data to output buffer delay through the I/O interface

tEOUT Enable to output buffer tristate control delay through the I/O interface

tDIN Input buffer to data delay through the I/O interface

tHZ Enable to pad delay through the output buffer—High to Z

tZH Enable to pad delay through the output buffer—Z to High

tLZ Enable to pad delay through the output buffer—Low to Z

tZL Enable to pad delay through the output buffer—Z to Low

tZHS Enable to pad delay through the output buffer with delayed enable—Z to High

tZLS Enable to pad delay through the output buffer with delayed enable—Z to Low

G Microsemi 25‘ 25‘

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-25

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Worst Commercial-Case Conditions: TJ = 85°C, Worst Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx (per standard)

Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins

I/O Standard

Drive Strength

Slew Rate

Capacitive Load (pF)

External Resistor ()

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

Units

3.3VLVTTL/

3.3 V LVCMOS

12 mA High 35 – 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns

2.5 V LVCMOS 12 mA High 35 – 0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.622.704.604.41 ns

1.8 V LVCMOS 12 mA High 35 – 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns

1.5 V LVCMOS 12 mA High 35 – 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns

3.3 V PCI Per PCI spec High 10 2510.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns

3.3 V PCI-X Per PCI-X

spec

High 10 2510.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns

LVDS 24 mA High – – 0.50 1.53 0.03 1.55 – – – – – – – ns

LVPECL 24 mA High – – 0.50 1.46 0.03 1.46 – – – – – – – ns

Notes:

1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-39 for

connectivity. This resistor is not required during normal operation.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Worst Commercial-Case Conditions: TJ = 85°C, Worst Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx (per standard)

Applicable to MSS I/O Banks

I/O Standard

Drive Strength

Slew Rate

Capacitive Load (pF)

External Resistor

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

Units

3.3 V LVTTL /

3.3 V LVCMOS

8 mA High 10 – 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns

2.5 V LVCMOS 8 mA High 10 – 0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.821.93 ns

1.8 V LVCMOS 4 mA High 10 – 0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.841.87 ns

1.5 V LVCMOS 2 mA High 10 – 0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.871.85 ns

Notes:

1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-39 for

connectivity. This resistor is not required during normal operation.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

O Microsemi

SmartFusion DC and Switching Characteristics

2-26 Revision 14

Detailed I/O DC Characteristics

Table 2-26 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-27 • I/O Output Buffer Maximum Resistances1

Applicable to FPGA I/O Banks

Standard Drive Strength

RPULL-DOWN

()2

RPULL-UP

()3

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 100 300

4 mA 100 300

6 mA 50 150

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 2 mA 100 200

4 mA 100 200

6 mA 50 100

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

Notes:

1. These maximum values are provided for information only. Minimum output buffer resistance values

depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located on the

Microsemi SoC Products Group website (also generated by the SoC Products Group Libero SoC toolset).

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-27

Table 2-28 • I/O Output Buffer Maximum Resistances1

Applicable to MSS I/O Banks

Standard Drive Strength

RPULL-DOWN

()2

RPULL-UP

()3

3.3 V LVTTL / 3.3 V LVCMOS 8mA 50 150

2.5 V LVCMOS 8 mA 50 100

1.8 V LVCMOS 4 mA 100 112

1.5 V LVCMOS 2 mA 200 224

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located on the

Microsemi SoC Products Group website.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCxxxxIOBx

R(WEAK PULL-UP)1

()

R(WEAK PULL-DOWN)2

()

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes:

1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)

2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)

O Microsemi

SmartFusion DC and Switching Characteristics

2-28 Revision 14

Table 2-30 • I/O Short Currents IOSH/IOSL

Applicable to FPGA I/O Banks

Drive Strength IOSL (mA)*IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25

4 mA 27 25

6 mA 54 51

8 mA 54 51

12 mA 109 103

16 mA 127 132

24 mA 181 268

2.5 V LVCMOS 2 mA 18 16

4 mA 18 16

6 mA 37 32

8 mA 37 32

12 mA 74 65

16 mA 87 83

24 mA 124 169

1.8 V LVCMOS 2 mA 11 9

4 mA 22 17

6 mA 44 35

8 mA 51 45

12 mA 74 91

16 mA 74 91

1.5 V LVCMOS 2 mA 16 13

4 mA 33 25

6 mA 39 32

8 mA 55 66

12 mA 55 66

3.3 V PCI/PCI-X Per PCI/PCI-X specification 109 103

Note: *TJ = 85°C.

Table 2-31 • I/O Short Currents IOSH/IOSL

Applicable to MSS I/O Banks

Drive Strength IOSL (mA)* IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 8 mA 54 51

2.5 V LVCMOS 8 mA 37 32

1.8 V LVCMOS 4 mA 22 17

1.5 V LVCMOS 2 mA 16 13

Note: *TJ = 85°C

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-29

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than 2200

operation hours to cause a reliability concern. The I/O design does not contain any short circuit

protection, but such protection would only be needed in extremely prolonged stress conditions.

Table 2-32 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

Table 2-33 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typical)

3.3 V LVTTL / LVCMOS / PCI / PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

Table 2-34 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS No requirement 10 ns * 20 years (100°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

No requirement 10 ns * 10 years (100°C)

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board

noise. Microsemi SoC Products Group recommends signal integrity evaluation/characterization of

the system to ensure that there is no excessive noise coupling into input signals.

O Microsemi <—h—‘><—h—‘—w—|>

SmartFusion DC and Switching Characteristics

2-30 Revision 14

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-35 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 15 15

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 15 15

6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 15 15

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15

12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 15 15

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 15 15

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-36 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-6 • AC Loading

Table 2-37 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 3.3 1.4 – 35

Note: *Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Test Point

Enable Path

Datapath 35 pF

R = 1 K R to GND for t

/ t

ZHS

R to VCCxxxxIOBx for t

/ t

ZLS

35 pF for t

/ t

ZHS

/ t

ZLS

35 pF for t

/ t

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-31

Timing Characteristics

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.60 7.20 0.04 0.97 0.39 7.34 6.18 2.52 2.46 9.39 8.23 ns

–1 0.50 6.00 0.03 0.81 0.32 6.11 5.15 2.10 2.05 7.83 6.86 ns

8 mA Std. 0.60 4.64 0.04 0.97 0.39 4.73 3.84 2.85 3.02 6.79 5.90 ns

–1 0.50 3.87 0.03 0.81 0.32 3.94 3.20 2.37 2.52 5.65 4.91 ns

12 mA Std. 0.60 3.37 0.04 0.97 0.39 3.43 2.67 3.07 3.39 5.49 4.73 ns

–1 0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns

16 mA Std. 0.60 3.18 0.04 0.97 0.39 3.24 2.43 3.11 3.48 5.30 4.49 ns

–1 0.50 2.65 0.03 0.81 0.32 2.70 2.03 2.59 2.90 4.42 3.74 ns

24 mA Std. 0.60 2.93 0.04 0.97 0.39 2.99 2.03 3.17 3.83 5.05 4.09 ns

–1 0.50 2.45 0.03 0.81 0.32 2.49 1.69 2.64 3.19 4.21 3.41 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.60 9.75 0.04 0.97 0.39 9.93 8.22 2.52 2.31 11.99 10.28 ns

–1 0.50 8.12 0.03 0.81 0.32 8.27 6.85 2.10 1.93 9.99 8.57 ns

8 mA Std. 0.60 6.96 0.04 0.97 0.39 7.09 5.85 2.84 2.87 9.15 7.91 ns

–1 0.50 5.80 0.03 0.81 0.32 5.91 4.88 2.37 2.39 7.62 6.59 ns

12 mA Std. 0.60 5.35 0.04 0.97 0.39 5.45 4.58 3.06 3.23 7.51 6.64 ns

–1 0.50 4.46 0.03 0.81 0.32 4.54 3.82 2.55 2.69 6.26 5.53 ns

16 mA Std. 0.60 5.01 0.04 0.97 0.39 5.10 4.30 3.11 3.32 7.16 6.36 ns

–1 0.50 4.17 0.03 0.81 0.32 4.25 3.58 2.59 2.77 5.97 5.30 ns

24 mA Std. 0.60 4.67 0.04 0.97 0.39 4.75 4.28 3.16 3.66 6.81 6.34 ns

–1 0.50 3.89 0.03 0.81 0.32 3.96 3.57 2.64 3.05 5.68 5.28 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-40 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

8 mA Std. 0.22 2.31 0.09 0.94 1.30 0.22 2.35 1.86 2.20 2.45 ns

–1 0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

G Microsemi <—h—‘><—h—‘—w—|>

SmartFusion DC and Switching Characteristics

2-32 Revision 14

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-41 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 15 15

4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 15 15

6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 15 15

8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 15 15

12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 15 15

16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 15 15

24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-42 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.,

mA1µA2µA2

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-43 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 2.5 1.2 – 35

*Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Test Point

Enable Path

Datapath 35 pF

R = 1 K R to GND for t

/ t

ZHS

R to VCCxxxxIOBx for t

/ t

ZLS

35 pF for t

/ t

ZHS

/ t

ZLS

35 pF for t

/ t

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-33

Timing Characteristics

Table 2-44 • 2.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 2.3 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.55 8.10 0.04 1.23 0.39 7.37 8.10 2.54 2.17 9.43 10.15 ns

–1 0.46 6.75 0.03 1.03 0.32 6.14 6.75 2.12 1.81 7.85 8.46 ns

8 mA Std. 0.55 4.85 0.04 1.23 0.39 4.76 4.85 2.90 2.83 6.82 6.91 ns

–1 0.46 4.04 0.03 1.03 0.32 3.97 4.04 2.42 2.36 5.68 5.76 ns

12 mA Std. 0.60 3.28 0.04 1.23 0.39 3.46 3.23 3.15 3.24 5.52 5.29 ns

–1 0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns

16 mA Std. 0.60 3.09 0.04 1.23 0.39 3.27 2.88 3.20 3.35 5.33 4.94 ns

–1 0.50 2.57 0.03 1.03 0.32 2.72 2.40 2.67 2.79 4.44 4.12 ns

24 mA Std. 0.60 2.95 0.04 1.23 0.39 3.01 2.31 3.27 3.76 5.07 4.37 ns

–1 0.50 2.46 0.03 1.03 0.32 2.51 1.93 2.73 3.13 4.22 3.64 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-45 • 2.5 V LVCMOS Low Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 2.3 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA Std. 0.55 10.50 0.04 1.23 0.39 10.69 10.50 2.54 2.07 12.75 12.56 ns

–1 0.46 8.75 0.03 1.03 0.32 8.91 8.75 2.12 1.73 10.62 10.47 ns

8 mA Std. 0.55 7.61 0.04 1.23 0.39 7.46 7.19 2.81 2.66 9.52 9.25 ns

–1 0.46 6.34 0.03 1.03 0.32 6.22 5.99 2.34 2.22 7.93 7.71 ns

12 mA Std. 0.60 5.92 0.04 1.23 0.39 5.79 5.45 3.04 3.06 7.85 7.51 ns

–1 0.50 4.93 0.03 1.03 0.32 4.83 4.54 2.53 2.55 6.54 6.26 ns

16 mA Std. 0.60 5.53 0.04 1.23 0.39 5.40 5.09 3.09 3.16 7.46 7.14 ns

–1 0.50 4.61 0.03 1.03 0.32 4.50 4.24 2.58 2.64 6.22 5.95 ns

24 mA Std. 0.60 5.18 0.04 1.23 0.39 5.28 5.14 3.27 3.64 7.34 7.20 ns

–1 0.50 4.32 0.03 1.03 0.32 4.40 4.29 2.72 3.03 6.11 6.00 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-46 • 2.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

8 mA Std. 0.22 2.35 0.09 1.18 1.39 0.22 2.40 2.18 2.19 2.32 ns

–1 0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

G Microsemi Min. Max. .3 0.45 0 3 0.45 0 3 0.45 0 3 0.45 0.3 0 3 0.45 —0.3 Figure 2-8 - Ac Loading 1 T 4—.

SmartFusion DC and Switching Characteristics

2-34 Revision 14

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

2 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.9 0.45 VCCxxxxIOBx

– 0.45

2 2 11 9 15 15

4 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.9 0.45 VCCxxxxIOBx

– 0.45

4 4 22 17 15 15

6 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.9 0.45 VCCxxxxIOBx

– 0.45

6 6 44 35 15 15

8 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.9 0.45 VCCxxxxIOBx

– 0.45

8 8 51 45 15 15

12 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.9 0.45 VCCxxxxIOBx

– 0.45

12 12 74 91 15 15

16 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.9 0.45 VCCxxxxIOBx

– 0.45

16 16 74 91 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

4 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

3.6 0.45 VCCxxxxIOBx

– 0.45

4 4 22 17 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 1.8 0.9 – 35

*Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Test Point

Enable Path

Datapath 35 pF

R = 1 K R to GND for t

/ t

ZHS

R to VCCxxxxIOBx for t

/ t

ZLS

35 pF for t

/ t

ZHS

/ t

ZLS

35 pF for t

/ t

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-35

Timing Characteristics

Table 2-50 • 1.8 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.7 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.60 11.06 0.04 1.14 0.39 8.61 11.06 2.61 1.59 10.67 13.12 ns

–1 0.50 9.22 0.03 0.95 0.32 7.17 9.22 2.18 1.33 8.89 10.93 ns

4 mA Std. 0.60 6.46 0.04 1.14 0.39 5.53 6.46 3.04 2.66 7.59 8.51 ns

–1 0.50 5.38 0.03 0.95 0.32 4.61 5.38 2.54 2.22 6.33 7.10 ns

6 mA Std. 0.60 4.16 0.04 1.14 0.39 3.99 4.16 3.34 3.18 6.05 6.22 ns

–1 0.50 3.47 0.03 0.95 0.32 3.32 3.47 2.78 2.65 5.04 5.18 ns

8 mA Std. 0.60 3.69 0.04 1.14 0.39 3.76 3.67 3.40 3.31 5.81 5.73 ns

–1 0.50 3.07 0.03 0.95 0.32 3.13 3.06 2.84 2.76 4.85 4.78 ns

12 mA Std. 0.60 3.38 0.04 1.14 0.39 3.44 2.86 3.50 3.82 5.50 4.91 ns

–1 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns

16 mA Std. 0.60 3.38 0.04 1.14 0.39 3.44 2.86 3.50 3.82 5.50 4.91 ns

–1 0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-51 • 1.8 V LVCMOS Low Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.7 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.60 14.24 0.04 1.14 0.39 13.47 14.24 2.62 1.54 15.53 16.30 ns

–1 0.50 11.87 0.03 0.95 0.32 11.23 11.87 2.18 1.28 12.94 13.59 ns

4 mA Std. 0.60 9.74 0.04 1.14 0.39 9.92 9.62 3.05 2.57 11.98 11.68 ns

–1 0.50 8.11 0.03 0.95 0.32 8.26 8.02 2.54 2.14 9.98 9.74 ns

6 mA Std. 0.60 7.67 0.04 1.14 0.39 7.81 7.24 3.34 3.08 9.87 9.30 ns

–1 0.50 6.39 0.03 0.95 0.32 6.51 6.03 2.79 2.56 8.23 7.75 ns

8 mA Std. 0.60 7.15 0.04 1.14 0.39 7.29 6.75 3.41 3.21 9.34 8.80 ns

–1 0.50 5.96 0.03 0.95 0.32 6.07 5.62 2.84 2.68 7.79 7.34 ns

12 mA Std. 0.60 6.76 0.04 1.14 0.39 6.89 6.75 3.50 3.70 8.95 8.81 ns

–1 0.50 5.64 0.03 0.95 0.32 5.74 5.62 2.92 3.08 7.46 7.34 ns

16 mA Std. 0.60 6.76 0.04 1.14 0.39 6.89 6.75 3.50 3.70 8.95 8.81 ns

–1 0.50 5.64 0.03 0.95 0.32 5.74 5.62 2.92 3.08 7.46 7.34 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

O Microsemi

SmartFusion DC and Switching Characteristics

2-36 Revision 14

Table 2-52 • 1.8 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.7 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

4 mA Std. 0.22 2.77 0.09 1.09 1.64 0.22 2.82 2.72 2.21 2.25 ns

–1 0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

G Microsemi <—h—‘><—h—'~w~|>

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-37

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-53 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

2 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.575 0.25*

VCCxxxxIOBx

0.75 *

VCCxxxxIOBx

2 2 16 13 15 15

4 mA –

0.3

0.35*

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.575 0.25*

VCCxxxxIOBx

0.75 *

VCCxxxxIOBx

4 4 33 25 15 15

6 mA –

0.3

0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.575 0.25*

VCCxxxxIOBx

0.75 *

VCCxxxxIOBx

6 6 39 32 15 15

8 mA –

0.3

0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.575 0.25* VCC 0.75 *

VCCxxxxIOBx

8 8 55 66 15 15

12 mA –

0.3

0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.575 0.25 *

VCCxxxxIOBx

0.75 *

VCCxxxxIOBx

12 12 55 66 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-54 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2

µA

2 mA –0.3 0.35 *

VCCxxxxIOBx

0.65 *

VCCxxxxIOBx

1.575 0.25 *

VCCxxxxIOBx

0.75 *

VCCxxxxIOBx

2 2 16 13 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 1.5 0.75 – 35

*Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Test Point

Enable Path

Datapath 35 pF

R = 1 K R to GND for t

/ t

ZHS

R to VCCxxxxIOBx for t

/ t

ZLS

35 pF for t

/ t

ZHS

/ t

ZLS

35 pF for t

/ t

0 Microsemi

SmartFusion DC and Switching Characteristics

2-38 Revision 14

Timing Characteristics

Table 2-56 • 1.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.425 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP t

DIN t

PY t

EOUT t

ZL t

ZH t

LZ t

HZ t

ZLS t

ZHS Units

2 m Std. 0.60 7.79 0.04 1.34 0.39 6.43 7.79 3.19 2.59 8.49 9.85 ns

–1 0.50 6.49 0.03 1.12 0.32 5.36 6.49 2.66 2.16 7.08 8.21 ns

4 mA Std. 0.60 4.95 0.04 1.34 0.39 4.61 4.96 3.53 3.19 6.67 7.02 ns

–1 0.50 4.13 0.03 1.12 0.32 3.85 4.13 2.94 2.66 5.56 5.85 ns

6 mA Std. 0.60 4.36 0.04 1.34 0.39 4.34 4.36 3.60 3.34 6.40 6.42 ns

–1 0.50 3.64 0.03 1.12 0.32 3.62 3.64 3.00 2.78 5.33 5.35 ns

8 mA Std. 0.60 3.89 0.04 1.34 0.39 3.96 3.34 3.72 3.92 6.02 5.40 ns

–1 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns

12 mA Std. 0.60 3.89 0.04 1.34 0.39 3.96 3.34 3.72 3.92 6.02 5.40 ns

–1 0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-57 • 1.5 V LVCMOS Low Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.4 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA Std. 0.60 11.96 0.04 1.34 0.39 12.18 11.70 3.20 2.47 14.24 13.76 ns

–1 0.50 9.96 0.03 1.12 0.32 10.15 9.75 2.67 2.06 11.86 11.46 ns

4 mA Std. 0.60 9.51 0.04 1.34 0.39 9.68 8.76 3.54 3.07 11.74 10.82 ns

–1 0.50 7.92 0.03 1.12 0.32 8.07 7.30 2.95 2.56 9.79 9.02 ns

6 mA Std. 0.60 8.86 0.04 1.34 0.39 9.03 8.17 3.61 3.22 11.08 10.23 ns

–1 0.50 7.39 0.03 1.12 0.32 7.52 6.81 3.01 2.68 9.24 8.52 ns

8 mA Std. 0.60 8.44 0.04 1.34 0.39 8.60 8.18 3.73 3.78 10.66 10.24 ns

–1 0.50 7.04 0.03 1.12 0.32 7.17 6.82 3.11 3.15 8.88 8.53 ns

12 mA Std. 0.60 8.44 0.04 1.34 0.39 8.60 8.18 3.73 3.78 10.66 10.24 ns

–1 0.50 7.04 0.03 1.12 0.32 7.17 6.82 3.11 3.15 8.88 8.53 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-58 • 1.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units

2 mA Std. 0.22 3.24 0.09 1.28 1.86 0.22 3.30 3.20 2.24 2.21 ns

–1 0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

0 Microsemi HM <—h—|—w~>

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-39

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; SoC Products Group loadings

for enable path characterization are described in Figure 2-10.

AC loadings are defined per PCI/PCI-X specifications for the datapath; SoC Products Group loading for

tristate is described in Table 2-60.

Timing Characteristics

Table 2-59 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmAmA

Max.

mA1

Max.

mA1µA2µA2

Per PCI specification Per PCI curves 15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-10 • AC Loading

Test Point

Enable Path

R to VCCXXXXIOBX for t

/ t

ZLS

10 pF for t

/ t

ZHS

/ t

ZLS

10 pF for t

/ t

R to GND for t

/ t

ZHS

R = 1 k

Test Point

Datapath

R = 25 R to VCCXXXXIOBX for t

(F)

R to GND for t

(R)

Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 3.3 0.285 * VCCxxxxIOBx for tDP(R)

0.615 * VCCxxxxIOBx for tDP(F)

–10

*Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Table 2-61 • 3.3 V PCI

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.60 2.54 0.04 0.82 0.39 2.58 1.88 3.06 3.39 4.64 3.94 ns

–1 0.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-62 • 3.3 V PCI-X

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

Std. 0.60 2.54 0.04 0.77 0.39 2.58 1.88 3.06 3.39 4.64 3.94 ns

–1 0.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

O Microsemi EQEQ

SmartFusion DC and Switching Characteristics

2-40 Revision 14

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by SoC Products Group Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, SmartFusion cSoCs also support bus LVDS structure and multipoint LVDS

(M-LVDS) configuration (up to 40 nodes).

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

140 100 

= 50 

165 

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-41

Timing Characteristics

Table 2-63 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCFPGAIOBx Supply voltage 2.375 2.5 2.625 V

VOL Output low voltage 0.9 1.075 1.25 V

VOH Output high voltage 1.25 1.425 1.6 V

IOL1Output lower current 0.65 0.91 1.16 mA

IOH1Output high current 0.65 0.91 1.16 mA

VI Input voltage 0 2.925 V

IIH2Input high leakage current 15 µA

IIL2Input low leakage current 15 µA

VODIFF Differential output voltage 250 350 450 mV

VOCM Output common mode voltage 1.125 1.25 1.375 V

VICM Input common mode voltage 0.05 1.25 2.35 V

VIDIFF Input differential voltage 100 350 mV

Notes:

1. IOL/I

OH defined by VODIFF/(resistor network).

2. Currents are measured at 85°C junction temperature.

Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V)

1.075 1.325 Cross point –

*Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Table 2-65 • LVDS

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCFPGAIOBx = 2.3 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade tDOUT tDP tDIN tPY Units

Std. 0.60 1.83 0.04 1.87 ns

–1 0.50 1.53 0.03 1.55 ns

Notes:

1. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

2. The above mentioned timing parameters correspond to 24mA drive strength.

O Microsemi eeeeeeee rrrrrr eeeeeeee

SmartFusion DC and Switching Characteristics

2-42 Revision 14

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. SoC Products Group LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require

series terminations for better signal quality and to control voltage swing. Termination is also required at

both ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using SoC Products Group LVDS macros can achieve up to 200 MHz with a maximum

of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available

in the LVDS section in Ta bl e 2- 6 5.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case commercial operating conditions, at the farthest receiver: RS=60

and RT=70, given Z0=50 (2") and Zstub =50 (~1.5").

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

+-T

+-R

+-T

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

RSRSRSRSRSRSRSRS

RSRS

Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

187 W 100 

= 50 

100 

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-43

Timing Characteristics

Table 2-66 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCFPGAIOBx Supply Voltage 3.0 3.3 3.6 V

VOL Output Low Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output High Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input Low, Input High Voltages 0 3.6 0 3.6 0 3.6 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V) VREF (typ.) (V)

1.64 1.94 Cross point –

*Measuring point = Vtrip. See Table 2-22 on page 2-24 for a complete table of trip points.

Table 2-68 • LVPECL

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCFPGAIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade tDOUT tDP tDIN tPY Units

Std. 0.60 1.76 0.04 1.76 ns

–1 0.50 1.46 0.03 1.46 ns

Notes:

1. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

2. The above mentioned timing parameters correspond to 24mA drive strength.

O Microsemi

SmartFusion DC and Switching Characteristics

2-44 Revision 14

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-45

Table 2-69 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-14 on page 2-44 for more information.

O Microsemi

SmartFusion DC and Switching Characteristics

2-46 Revision 14

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-47

Table 2-70 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-15 on page 2-46 for more information.

O Microsemi

SmartFusion DC and Switching Characteristics

2-48 Revision 14

Input Register

Timing Characteristics

Figure 2-16 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

ISUE

50%

ISUD

IHD

50% 50%

ICLKQ

IHE

IRECPRE

IREMPRE

IRECCLR

IREMCLR

IWCLR

IWPRE

IPRE2Q

ICLR2Q

ICKMPWH

ICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-71 • Input Data Register Propagation Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.29 ns

tISUD Data Setup Time for the Input Data Register 0.27 0.32 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.38 0.45 ns

tIHE Enable Hold Time for the Input Data Register 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.46 0.55 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.46 0.55 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.230.27 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.000.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.23 0.27 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.22 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.22 ns

tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.36 0.36 ns

tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.32 0.32 ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9

for derating values.

o Microsemi /\I\r\f\r\7P\ 1W x x x —M “V W TV f? m! ﬁ‘w

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-49

Output Register

Timing Characteristics

Figure 2-17 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

tOSUE

50%

tOSUD tOHD

50% 50%

tOCLKQ

tOHE

tORECPRE

tOREMPRE

tORECCLR tOREMCLR

tOWCLR

tOWPRE

tOPRE2Q

tOCLR2Q

tOCKMPWH tOCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-72 • Output Data Register Propagation Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tOCLKQ Clock-to-Q of the Output Data Register 0.60 0.72 ns

tOSUD Data Setup Time for the Output Data Register 0.32 0.38 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 ns

tOSUE Enable Setup Time for the Output Data Register 0.44 0.53 ns

tOHE Enable Hold Time for the Output Data Register 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 0.98 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.82 0.98 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.000.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.23 0.27 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.23 0.27 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.22 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.22 ns

tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.36 0.36 ns

tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.32 0.32 ns

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on

page 2-9 for derating values.

O Microsemi J / r / r ”W ’XW x XX: 4M “K m M _/7JL‘

SmartFusion DC and Switching Characteristics

2-50 Revision 14

Output Enable Register

Timing Characteristics

Figure 2-18 • Output Enable Register Timing Diagram

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

OESUE

50%

OESUD

OEHD

50% 50%

OECLKQ

OEHE

OERECPRE

OEREMPRE

OERECCLR

OEREMCLR

OEWCLR

OEWPRE

OEPRE2Q

OECLR2Q

OECKMPWH

OECKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-73 • Output Enable Register Propagation Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.45 0.54 ns

tOESUD Data Setup Time for the Output Enable Register 0.32 0.38 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 ns

tOESUE Enable Setup Time for the Output Enable Register 0.44 0.53 ns

tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.68 0.81 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.68 0.81 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.23 0.27 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.23 0.27 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.22 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.22 ns

tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.36 0.36 ns

tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.320.32 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

o Microsemi Input DDR

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-51

DDR Module Specifications

Input DDR Module

Figure 2-19 • Input DDR Timing Model

Table 2-74 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

O Microsemi WKXX XXXXX _/ L” L” x4 L”

SmartFusion DC and Switching Characteristics

2-52 Revision 14

Timing Characteristics

Figure 2-20 • Input DDR Timing Diagram

DDRICLR2Q2

DDRIREMCLR

DDRIRECCLR

DDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

DDRICLKQ1

246

357

DDRIHD

DDRISUD

DDRICLKQ2

Table 2-75 • Input DDR Propagation Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst Case VCC = 1.425 V

Parameter Description –1 Units

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.28 ns

tDDRISUD Data Setup for Input DDR 0.29 ns

tDDRIHD Data Hold for Input DDR 0.00 ns

tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.58 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.47 ns

tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.23 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 ns

tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 ns

tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 ns

FDDRIMAX Maximum Frequency for Input DDR 350 MHz

Note: For derating values at specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for

derating values.

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-53

Output DDR Module

Figure 2-21 • Output DDR Timing Model

Table 2-76 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

O Microsemi

SmartFusion DC and Switching Characteristics

2-54 Revision 14

Timing Characteristics

Figure 2-22 • Output DDR Timing Diagram

116

910

28 3 9

DDROREMCLR

DDROHD1

DDROREMCLR

DDROHD2

DDROSUD2

DDROCLKQ

DDRORECCLR

CLK

Data_R

Data_F

CLR

Out

DDROCLR2Q

7104

Table 2-77 • Output DDR Propagation Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.71 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.81 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.23 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 ns

tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 ns

tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 ns

FDDOMAX Maximum Frequency for the Output DDR 350 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-55

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The SmartFusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing

characteristics are presented for a sample of the library. For more details, refer to the IGLOO/e, Fusion,

ProASIC3/E, and SmartFusion Macro Library Guide.

Figure 2-23 • Sample of Combinatorial Cells

MAJ3

MUX2

XOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3 Y

NAND2

SmartFusion DC and Switching Characteristics

2-56 Revision 14

Figure 2-24 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF),

tPD(FF), tPD(FR)) where edges are

applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50% 50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

0 Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-57

Timing Characteristics

VersaTile Specifications as a Sequential Module

The SmartFusion library offers a wide variety of sequential cells, including flip-flops and latches. Each

has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented

for a representative sample from the library. For more details, refer to the IGLOO/e, Fusion, ProASIC3/E,

and SmartFusion Macro Library Guide.

Table 2-78 • Combinatorial Cell Propagation Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –1 Std. Units

INV Y = !A tPD 0.41 0.49 ns

AND2 Y = A · B tPD 0.48 0.57 ns

NAND2 Y = !(A · B) tPD 0.48 0.57 ns

OR2 Y = A + B tPD 0.49 0.59 ns

NOR2 Y = !(A + B) tPD 0.49 0.59 ns

XOR2 Y = A Bt

PD 0.75 0.90 ns

MAJ3 Y = MAJ(A, B, C) tPD 0.71 0.85 ns

XOR3 Y = A  B Ct

PD 0.89 1.07 ns

MUX2 Y = A !S + B S tPD 0.51 0.62 ns

AND3 Y = A · B · C tPD 0.57 0.68 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

Figure 2-25 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

O Microsemi

SmartFusion DC and Switching Characteristics

2-58 Revision 14

Timing Characteristics

Figure 2-26 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

SUE

50%

SUD

50% 50%

CLKQ

RECPRE

REMPRE

RECCLR

REMCLR

WCLR

WPRE

PRE2Q

CLR2Q

CKMPWH

CKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-79 • Register Delays

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tCLKQ Clock-to-Q of the Core Register 0.56 0.67 ns

tSUD Data Setup Time for the Core Register 0.44 0.52 ns

tHD Data Hold Time for the Core Register 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.46 0.55 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.41 0.49 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.41 0.49 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.23 0.27 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 0.27 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.220.22 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.22 ns

tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.32 0.32 ns

tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.36 0.36 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-59

Global Resource Characteristics

A2F200 Clock Tree Topology

Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The

global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A2F200 device. It

is used to drive all D-flip-flops in the device.

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-63. Table 2-80 through Table 2-82 on page 2-61

present minimum and maximum global clock delays for the SmartFusion cSoCs. Minimum and maximum

delays are measured with minimum and maximum loading.

Figure 2-27 • Example of Global Tree Use in an A2F200 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

O Microsemi

SmartFusion DC and Switching Characteristics

2-60 Revision 14

Timing Characteristics

Table 2-80 • A2F500 Global Resource

Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V

Parameter Description

–1 Std.

UnitsMin.1Max.2Min.1Max.2

tRCKL Input Low Delay for Global Clock 1.54 1.73 1.84 2.08 ns

tRCKH Input High Delay for Global Clock 1.53 1.76 1.84 2.12 ns

tRCKMPWH Minimum Pulse Width High for Global Clock 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns

tRCKSW Maximum Skew for Global Clock 0.23 0.28 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating

values.

Table 2-81 • A2F200 Global Resource

Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V

Parameter Description

–1 Std.

UnitsMin.1Max.2Min.1Max.2

tRCKL Input Low Delay for Global Clock 0.74 0.99 0.88 1.19 ns

tRCKH Input High Delay for Global Clock 0.76 1.05 0.91 1.26 ns

tRCKMPWH Minimum Pulse Width High for Global Clock 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns

tRCKSW Maximum Skew for Global Clock 0.29 0.35 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating

values.

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-61

RC Oscillator

The table below describes the electrical characteristics of the RC oscillator.

RC Oscillator Characteristics

Table 2-82 • A2F060 Global Resource

Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V

Parameter Description

–1 Std.

UnitsMin.1Max.2Min.1Max.2

tRCKL Input Low Delay for Global Clock 0.75 0.96 0.90 1.15 ns

tRCKH Input High Delay for Global Clock 0.72 0.98 0.86 1.17 ns

tRCKMPWH Minimum Pulse Width High for Global Clock 0.85 1.00 ns

tRCKMPWL Minimum Pulse Width Low for Global Clock 0.85 1.00 ns

tRCKSW Maximum Skew for Global Clock 0.26 0.31 ns

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating

values.

Table 2-83 • Electrical Characteristics of the RC Oscillator

Parameter Description Condition Min. Typ. Max. Units

FRC Operating

frequency

100 MHz

Accuracy Temperature: –40°C to 100°C

Voltage: 3.3 V ± 5%

1 %

Output jitter Period jitter (at 5 K cycles) 100 ps RMS

Cycle-to-cycle jitter (at 5 K cycles) 100 ps RMS

Period jitter (at 5 K cycles) with 1 KHz / 300

mV peak-to-peak noise on power supply

150 ps RMS

Cycle-to-cycle jitter (at 5 K cycles) with 1 KHz

/ 300 mV peak-to-peak noise on power

supply

150 ps RMS

Output duty cycle 50 %

IDYNRC Operating current 3.3 V domain 1 mA

1.5 V domain 2 mA

O Microsemi

SmartFusion DC and Switching Characteristics

2-62 Revision 14

Main and Lower Power Crystal Oscillator

The tables below describes the electrical characteristics of the main and low power crystal oscillator.

Table 2-84 • Electrical Characteristics of the Main Crystal Oscillator

Parameter Description Condition Min. Typ. Max. Units

Operating frequency Using external crystal 0.032 20 MHz

Using ceramic resonator 0.5 8 MHz

Using RC Network 0.032 4 MHz

Output duty cycle 50 %

Output jitter With 10 MHz crystal 1 ns RMS

IDYNXTAL Operating current RC 0.6 mA

0.032–0.2 0.6 mA

0.2–2.0 0.6 mA

2.0–20.0 0.6 mA

ISTBXTAL Standby current of crystal oscillator 10 µA

PSRRXTAL Power supply noise tolerance 0.5 Vp-p

VIHXTAL Input logic level High 90%

VCC

VILXTAL Input logic level Low 10%

VCC

Startup time RC [Tested at 3.24Mhz] 300 550 µs

0.032–0.2 [Tested at 32KHz] 500 3,000 µs

0.2–2.0 [Tested at 2MHz] 8 12 µs

2.0–20.0 [Tested at 20MHz] 160 180 µs

Table 2-85 • Electrical Characteristics of the Low Power Oscillator

Parameter Description Condition Min. Typ. Max. Units

Operating frequency 32 KHz

Output duty cycle 50 %

Output jitter 30 ns RMS

IDYNXTAL Operating current 32 KHz 10 µA

ISTBXTAL Standby current of crystal oscillator 2 µA

PSRRXTAL Power supply noise tolerance 0.5 Vp-p

VIHXTAL Input logic level High 90% of VCC V

VILXTAL Input logic level Low 10% of VCC V

Startup time Test load used: 20 pF 2.5 s

Test load used: 30 pF 3.7 13 s

G Microsemi e De‘ay 1 ‘ e De‘ay ‘

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-63

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-86 • SmartFusion CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 3501MHz

Delay Increments in Programmable Delay Blocks2,3,4 160 ps

Number of Programmable Values in Each

Programmable Delay Block

Input Period Jitter 1.5 ns

Acquisition Time

LockControl = 0 300 µs

LockControl = 1 6.0 ms

Tracking Jitter5

LockControl = 0 1.6 ns

LockControl = 1 0.8 ns

Output Duty Cycle 48.5 5.15 %

Delay Range in Block: Programmable Delay 12,3 0.6 5.56 ns

Delay Range in Block: Programmable Delay 22,3 0.025 5.56 ns

Delay Range in Block: Fixed Delay2,3 2.2 ns

CCC Output Peak-to-Peak Period Jitter FCCC_OUT 6,7 Maximum Peak-to-Peak Period Jitter

SSO  2 SSO  4 SSO  8 SSO  16

FG/CS PQ FG/CS PQ FG/CS PQ FG/CS PQ

0.75 MHz to 50 MHz 0.5% 1.6% 0.9% 1.6% 0.9% 1.6% 0.9% 1.8%

50 MHz to 250 MHz 1.75% 3.5% 9.3% 9.3% 9.3% 17.9% 10.0% 17.9%

250 MHz to 350 MHz 2.5% 5.2% 13.0% 13.0% 13.0% 25.0% 14.0% 25.0%

Notes:

1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details

regarding CCC/PLL are in the "PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators" chapter of the

SmartFusion Microcontroller Subsystem User's Guide.

2. This delay is a function of voltage and temperature. See Table 2-7 on page 2-9 for deratings.

3. TJ = 25°C, VCC = 1.5 V

4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help associated with the core for more information.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge.

Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.

6. Measurement done with LVTTL 3.3 V 12 mA I/O drive strength and High slew rate. VCC/VCCPLL = 1.425 V,

VCCI = 3.3V, 20 pF output load. All I/Os are placed outside of the PLL bank.

7. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out within ± 200 ps of each other.

8. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying

the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For

example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps.

O Microsemi Peak-to»peakjmer measurements are deﬁned by Tpeamrpsak = Tpgmd max , Tpemd mm

SmartFusion DC and Switching Characteristics

2-64 Revision 14

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.

Figure 2-28 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

o Microsemi IJHLIIII IJHLIIIII | A

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-65

FPGA Fabric SRAM and FIFO Characteristics

FPGA Fabric SRAM

Figure 2-29 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

O Microsemi J J

SmartFusion DC and Switching Characteristics

2-66 Revision 14

Timing Waveforms

Figure 2-30 • RAM Read for Pass-Through Output. Applicable to both RAM4K9 and RAM512x18.

Figure 2-31 • RAM Read for Pipelined Output Applicable to both RAM4K9 and RAM512x18.

CLK

[R|W]ADDR

BLK

WEN

DOUT|RD

CYC

CKH

CKL

BKS

ENS

ENH

DOH1

BKH

CKQ1

CLK

[R|W]ADDR

BLK

WEN

DOUT|RD

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

XX >k ><><><><><><><><><><><><><>C _* +31 X> kXXXX XXXX>C “ * ﬂ? WW W

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-67

Figure 2-32 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.

Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 only.

CYC

CKH

CKL

BKS

ENS

ENH

CLK

BLK

WEN

[R|W]ADDR

DIN|WD

DOUT|RD

BKH

CYC

CKH

CKL

BKS

ENS

CLK

BLK

WEN

ADDR

DIN

BKH

DOUT

(pass-through) DI

DOUT

(pipelined) DI

O Microsemi

SmartFusion DC and Switching Characteristics

2-68 Revision 14

Figure 2-34 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.

CLK

RESET

DOUT|RD D

CYC

CKH

CKL

RSTBQ

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-69

Timing Characteristics

Table 2-87 • RAM4K9

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tAS Address setup time 0.25 0.30 ns

tAH Address hold time 0.00 0.00 ns

tENS REN, WEN setup time 0.15 0.17 ns

tENH REN, WEN hold time 0.10 0.12 ns

tBKS BLK setup time 0.24 0.28 ns

tBKH BLK hold time 0.02 0.02 ns

tDS Input data (DIN) setup time 0.19 0.22 ns

tDH Input data (DIN) hold time 0.00 0.00 ns

tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 1.81 2.18 ns

Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.39 2.87 ns

tCKQ2 Clock High to new data valid on DOUT (pipelined) 0.91 1.09 ns

tC2CWWH1Address collision clk-to-clk delay for reliable write after write on same

address—applicable to rising edge

0.23 0.26 ns

tC2CRWH1Address collision clk-to-clk delay for reliable read access after write on same

address—applicable to opening edge

0.34 0.38 ns

tC2CWRH1Address collision clk-to-clk delay for reliable write access after read on same

address— applicable to opening edge

0.37 0.42 ns

tRSTBQ RESET Low to data out Low on DOUT (flow-through) 0.94 1.12 ns

RESET Low to Data Out Low on DOUT (pipelined) 0.94 1.12 ns

tREMRSTB RESET removal 0.29 0.35 ns

tRECRSTB RESET recovery 1.52 1.83 ns

tMPWRSTB RESET minimum pulse width 0.22 0.22 ns

tCYC Clock cycle time 3.28 3.28 ns

FMAX Maximum clock frequency 305 305 MHz

Notes:

1. For more information, refer to the Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and

FPGAs application note.

2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

O Microsemi

SmartFusion DC and Switching Characteristics

2-70 Revision 14

Table 2-88 • RAM512X18

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tAS Address setup time 0.25 0.30 ns

tAH Address hold time 0.00 0.00 ns

tENS REN, WEN setup time 0.09 0.11 ns

tENH REN, WEN hold time 0.06 0.07 ns

tDS Input data (WD) setup time 0.19 0.22 ns

tDH Input data (WD) hold time 0.00 0.00 ns

tCKQ1 Clock High to new data valid on RD (output retained, WMODE = 0) 2.19 2.63 ns

tCKQ2 Clock High to new data valid on RD (pipelined) 0.91 1.09 ns

tC2CRWH1Address collision clk-to-clk delay for reliable read access after write on same

address—applicable to opening edge

0.38 0.43 ns

tC2CWRH1Address collision clk-to-clk delay for reliable write access after read on same

address—applicable to opening edge

0.44 0.50 ns

tRSTBQ RESET Low to data out Low on RD (flow-through) 0.94 1.12 ns

RESET Low to data out Low on RD (pipelined) 0.94 1.12 ns

tREMRSTB RESET removal 0.29 0.35 ns

tRECRSTB RESET recovery 1.52 1.83 ns

tMPWRSTB RESET minimum pulse width 0.22 0.22 ns

tCYC Clock cycle time 3.28 3.28 ns

FMAX Maximum clock frequency 305 305 MHz

Notes:

1. For more information, refer to the Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and

FPGAs application note.

2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

o Microsemi || |J>|| III II |||||||| lléél

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-71

FIFO

Figure 2-35 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

O Microsemi 4:I.m J“ "P w ﬁr ( ><>O<><> __>L ><><> XXXX _/—\_/—\_/—L

SmartFusion DC and Switching Characteristics

2-72 Revision 14

Timing Waveforms

Figure 2-36 • FIFO Read

Figure 2-37 • FIFO Write

ENS

ENH

CKQ1

CKQ2

CYC

BKS

BKH

RCLK

RBLK

REN

(flow-through)

(pipelined)

WCLK

WEN

ENS

ENH

CYC

BKH

BKS

WBLK

o Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-73

Figure 2-38 • FIFO Reset

Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A0)

tMPWRSTB

tRSTFG

tRSTCK

tRSTAF

RCLK/

WCLK

RESET

EMPTY

AEMPTY

WA/RA

(Address Counter)

tRSTFG

tRSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

CKAF

RCKEF

EMPTY

AEMPTY

CYC

WA/RA

(Address Counter)

O Microsemi 4—1 —>

SmartFusion DC and Switching Characteristics

2-74 Revision 14

Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion

Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

tRCKEF

tCKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

WCKF

CKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-75

Timing Characteristics

Table 2-89 • FIFO

Worst Commercial-Case Conditions: TJ = 85°C, VCC = 1.425 V

Parameter Description –1 Std. Units

tENS REN, WEN Setup Time 1.40 1.68 ns

tENH REN, WEN Hold Time 0.02 0.02 ns

tBKS BLK Setup Time 0.19 0.19 ns

tBKH BLK Hold Time 0.00 0.00 ns

tDS Input Data (WD) Setup Time 0.19 0.22 ns

tDH Input Data (WD) Hold Time 0.00 0.00 ns

tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.39 2.87 ns

tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.91 1.09 ns

tRCKEF RCLK High to Empty Flag Valid 1.74 2.09 ns

tWCKFF WCLK High to Full Flag Valid 1.66 1.99 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.29 7.54 ns

tRSTFG RESET Low to Empty/Full Flag Valid 1.72 2.06 ns

tRSTAF RESET Low to Almost Empty/Full Flag Valid 6.22 7.47 ns

tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.94 1.12 ns

RESET Low to Data Out Low on RD (pipelined) 0.94 1.12 ns

tREMRSTB RESET Removal 0.29 0.35 ns

tRECRSTB RESET Recovery 1.52 1.83 ns

tMPWRSTB RESET Minimum Pulse Width 0.22 0.22 ns

tCYC Clock Cycle Time 3.28 3.28 ns

FMAX Maximum Frequency for FIFO 305 305 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

O Microsemi

SmartFusion DC and Switching Characteristics

2-76 Revision 14

Embedded Nonvolatile Memory Block (eNVM)

Electrical Characteristics

Table 2-90 describes the eNVM maximum performance.

Embedded FlashROM (eFROM)

Electrical Characteristics

Table 2-91 describes the eFROM maximum performance

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-19 for more details.

Timing Characteristics

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C, VCC = 1.425 V

Parameter Description

A2F060 A2F200 A2F500

Units–1 Std. –1 Std. –1 Std.

tFMAXCLKeNVM Maximum frequency for clock for the control logic – 5

cycles (5:1:1:1*)

50 50 50 50 50 50 MHz

tFMAXCLKeNVM Maximum frequency for clock for the control logic – 6

cycles (6:1:1:1*)

100 80 100 80 100 80 MHz

Note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles

for the first access and 1 each for the next three accesses.

Note: *Moving from 5:1:1:1 mode to 6:1:1:1 mode results in throughput change that is dependent on the system

functionality. When the Cortex-M3 code is executed from eNVM - with sequential firmware (sequential address

reads), the throughput reduction can be around 10%.

Table 2-91 • FlashROM Access Time, Worse Commercial Case Conditions: TJ = 85°C, VCC = 1.425 V

Parameter Description –1 Std. Units

tCK2Q Clock to out per configuration* 28.68 32.98 ns

Fmax Maximum Clock frequency 15.00 15.00 MHz

Table 2-92 • JTAG 1532

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

tDISU Test Data Input Setup Time 0.67 0.77 ns

tDIHD Test Data Input Hold Time 1.33 1.53 ns

tTMSSU Test Mode Select Setup Time 0.67 0.77 ns

tTMDHD Test Mode Select Hold Time 1.33 1.53 ns

tTCK2Q Clock to Q (data out) 8.00 9.20 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

0 Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-77

tRSTB2Q Reset to Q (data out) 26.67 30.67 ns

FTCKMAX TCK Maximum Frequency 19.00 21.85 MHz

tTRSTREM ResetB Removal Time 0.00 0.00 ns

tTRSTREC ResetB Recovery Time 0.27 0.31 ns

tTRSTMPW ResetB Minimum Pulse TBD TBD ns

Table 2-92 • JTAG 1532

Worst Commercial-Case Conditions: TJ = 85°C, Worst-Case VCC = 1.425 V

Parameter Description –1 Std. Units

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

O Microsemi

SmartFusion DC and Switching Characteristics

2-78 Revision 14

Programmable Analog Specifications

Current Monitor

Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply

voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit

mode and 91 Ksps, after digital compensation. All results are based on averaging over 16 samples.

Table 2-93 • Current Monitor Performance Specification

Specification Test Conditions Min. Typical Max. Units

Input voltage range (for driving ADC

over full range)

0 – 48 0 – 50 1 – 51 mV

Analog gain From the differential voltage across the

input pads to the ADC input

50 V/V

Input referred offset voltage Input referred offset voltage 0 0.1 0.5 mV

–40ºC to +100ºC 0 0.1 0.5 mV

Gain error Slope of BFSL vs. 50 V/V ±0.1 ±0.5 % nom.

–40ºC to +100ºC ±0.5 % nom.

Overall Accuracy Peak error from ideal transfer function,

25°C

±(0.1 +

0.25%)

±(0.4 +

1.5%)

mV plus

reading

Input referred noise 0 VDC input (no output averaging) 0.3 0.4 0.5 mVrms

Common-mode rejection ratio 0 V to 12 VDC common-mode voltage –86 –87dB

Analog settling time To 0.1% of final value (with ADC load)

From CM_STB (High) 5 µs

From ADC_START (High) 5 200 µs

Input capacitance 8pF

Input biased current CM[n] or TM[n] pad,

–40°C to +100°C over maximum input

voltage range (plus is into pad)

Strobe = 0; IBIAS on CM[n] 0 µA

Strobe = 1; IBIAS on CM[n] 1 µA

Strobe = 0; IBIAS on TM[n] 2 µA

Strobe = 1; IBIAS on TM[n] 1 µA

Power supply rejection ratio DC (0 – 10 KHz) 41 42 dB

Incremental operational current

monitor power supply current

requirements (per current monitor

instance, not including ADC or

VAREFx)

VCC33A 150 µA

VCC33AP 140 µA

VCC15A 50 µA

Note: Under no condition should the TM pad ever be greater than 10 mV above the CM pad. This restriction is

applicable only if current monitor is used.

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-79

Temperature Monitor

Unless otherwise noted, temperature monitor performance is specified with a 2N3904 diode-connected

bipolar transistor from National Semiconductor or Infineon Technologies, nominal power supply voltages,

with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and

62.5 Ksps. After digital compensation. Unless otherwise noted, the specifications pertain to conditions

where the SmartFusion cSoC and the sensing diode are at the same temperature.

Table 2-94 • Temperature Monitor Performance Specifications

Specification Test Conditions Min. Typical Max. Units

Input diode temperature range –55 150 °C

233.2 378.15 K

Temperature sensitivity 2.5 mV/K

Intercept Extrapolated to 0K 0 V

Input referred temperature offset

error

At 25°C (298.15K) ±1 1.5 °C

Gain error Slope of BFSL vs. 2.5 mV/K ±1 2.5 % nom.

Overall accuracy Peak error from ideal transfer function ±2 ±3 °C

Input referred noise At 25°C (298.15K) – no output averaging 4 °C rms

Output current Idle mode 100 µA

Final measurement phases 10 µA

Analog settling time Measured to 0.1% of final value, (with

ADC load)

From TM_STB (High) 5 µs

From ADC_START (High) 5 105 µs

AT parasitic capacitance 500 pF

Power supply rejection ratio DC (0–10 KHz) 1.2 0.7 °C/V

Input referred temperature

sensitivity error

Variation due to device temperature

(–40°C to +100°C). External temperature

sensor held constant.

0.005 0.008 °C/°C

Temperature monitor (TM)

operational power supply current

requirements (per temperature

monitor instance, not including ADC

or VAREFx)

VCC33A 200 µA

VCC33AP 150 µA

VCC15A 50 µA

Note: All results are based on averaging over 64 samples.

O Microsemi __J_._

SmartFusion DC and Switching Characteristics

2-80 Revision 14

Figure 2-43 • Temperature Error Versus External Capacitance

-7

-6

-5

-4

-3

-2

-1

1.00E -06 1.00E -05 1.00E -04 1.00E -03 1.00E -02 1.00E -01 1.00E+00

Temperature Error (°C)

Capacitance (µF)

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-81

Analog-to-Digital Converter (ADC)

Unless otherwise noted, ADC direct input performance is specified at 25°C with nominal power supply

voltages, with the output measured using the external voltage reference with the internal ADC in 12-bit

mode and 500 KHz sampling frequency, after trimming and digital compensation.

Table 2-95 • ADC Specifications

Specification Test Conditions Min. Typ. Max. Units

Input voltage range (for driving ADC

over its full range)

2.56 V

Gain error ±0.4 ±0.7 %

–40ºC to +100ºC ±0.4 ±0.7 %

Input referred offset voltage ±1 ±2 mV

–40ºC to +100ºC ±1 ±2

Integral non-linearity (INL) RMS deviation from BFSL

12-bit mode 1.71 LSB

10-bit mode 0.60 1.00 LSB

8-bit mode 0.2 0.33 LSB

Differential non-linearity (DNL) 12-bit mode 2.4 LSB

10-bit mode 0.80 0.94 LSB

8-bit mode 0.2 0.23 LSB

Signal to noise ratio 62 64 dB

Effective number of bits (ENOB)

EQ 10

–1 dBFS input

12-bit mode 10 KHz 9.9 10 Bits

12-bit mode 100 KHz 9.9 10 Bits

10-bit mode 10 KHz 9.5 9.6 Bits

10-bit mode 100 KHz 9.5 9.6 Bits

8-bit mode 10 KHz 7.8 7.9 Bits

8-bit mode 100 KHz 7.8 7.9 Bits

Full power bandwidth At –3 dB; –1 dBFS input 300 KHz

Analog settling time To 0.1% of final value (with 1 Kohm source

impedance and with ADC load)

2µs

Input capacitance Switched capacitance (ADC sample

capacitor)

12 15 pF

Cs: Static capacitance (Figure 2-44 on page 2-86)

CM[n] input 5 7 pF

TM[n] input 5 7 pF

ADC[n] input 5 7 pF

Input resistance Rin: Series resistance (Figure 2-44)2K

Rsh: Shunt resistance, exclusive of

switched capacitance effects (Figure 2-44)

10 M

Note: All 3.3 V supplies are tied together and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant.

ENOB SINAD 1.76 dB–

6.02 dB/bit

---------------------------------------------=

O Microsemi

SmartFusion DC and Switching Characteristics

2-82 Revision 14

Analog Bipolar Prescaler (ABPS)

With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15.36

V to +15.36 V is scaled and offset by the ABPS input amplifier to match the ADC full range of 0 V to 2.56

V using a nominal gain of –0.08333 V/V. However, due to reliability considerations, the voltage applied to

the ABPS input should never be outside the range of –11.5 V to +14.4 V, restricting the usable ADC input

voltage to 2.238 V to 0.080 V and the corresponding 12-bit output codes to the range of 3581 to 128

(decimal), respectively.

Unless otherwise noted, ABPS performance is specified at 25°C with nominal power supply voltages,

with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and

100 KHz sampling frequency, after trimming and digital compensation; and applies to all ranges.

Input leakage current –40°C to +100°C 1 µA

Power supply rejection ratio DC 44 53 dB

ADC power supply operational current

requirements

VCC33ADCx 2.5 mA

VCC15A 2 mA

Table 2-95 • ADC Specifications (continued)

Specification Test Conditions Min. Typ. Max. Units

Note: All 3.3 V supplies are tied together and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant.

Table 2-96 • ABPS Performance Specifications

Specification Test Conditions Min. Typ. Max. Units

Input voltage range (for driving ADC

over its full range)

GDEC[1:0] = 11 ±2.56 V

GDEC[1:0] = 10 ±5.12 V

GDEC[1:0] = 01 ±10.24 V

GDEC[1:0] = 00 (limited by

maximum rating)

See note 1 V

Analog gain (from input pad to ADC

input)

GDEC[1:0] = 11 –0.5 V/V

GDEC[1:0] = 10 –0.25 V/V

GDEC[1:0] = 01 –0.125 V/V

GDEC[1:0] = 00 –0.0833 V/V

Gain error –2.8 –0.4 0.7 %

–40ºC to +100ºC –2.8 –0.4 0.7 %

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-83

Input referred offset voltage

GDEC[1:0] = 11 –0.31 –0.07 0.31 % FS*

–40ºC to +100ºC –1.00 1.47 % FS*

GDEC[1:0] = 10 –0.34 –0.07 0.34 % FS*

–40ºC to +100ºC –0.90 1.37 % FS*

GDEC[1:0] = 01 –0.61 –0.07 0.35 % FS*

–40ºC to +100ºC –1.05 1.35 % FS*

GDEC[1:0] = 00 –0.39 –0.07 0.35 % FS*

–40ºC to +100ºC –1.06 1.38 % FS*

SINAD 53 56 dB

Non-linearity RMS deviation from BFSL 0.5 % FS*

Effective number of bits (ENOB)

EQ 11

GDEC[1:0] = 11

(±2.56 range), –1 dBFS input

12-bit mode 10 KHz 8.6 9.1 Bits

12-bit mode 100 KHz 8.6 9.1 Bits

10-bit mode 10 KHz 8.5 8.9 Bits

10-bit mode 100 KHz 8.5 8.9 Bits

8-bit mode 10 KHz 7.7 7.8 Bits

8-bit mode 100 KHz 7.7 7.8 Bits

Large-signal bandwidth –1 dBFS input 1 MHz

Analog settling time To 0.1% of final value (with ADC

load)

10 µs

Input resistance 1M

Power supply rejection ratio DC (0–1 KHz) 38 40 dB

ABPS power supply current

requirements (not including ADC or

VAREFx)

ABPS_EN = 1 (operational mode)

VCC33A 123 134 µA

VCC33AP 89 94 µA

VCC15A 1 µA

Table 2-96 • ABPS Performance Specifications (continued)

Specification Test Conditions Min. Typ. Max. Units

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

ENOB SINAD 1.76 dB–

6.02 dB/bit

---------------------------------------------=

O Microsemi

SmartFusion DC and Switching Characteristics

2-84 Revision 14

Comparator

Unless otherwise specified, performance is specified at 25°C with nominal power supply voltages.

Table 2-97 • Comparator Performance Specifications

Specification Test Conditions Min. Typ. Max. Units

Input voltage range Minimum 0 V

Maximum 2.56 V

Input offset voltage HYS[1:0] = 00

(no hysteresis)

±1 ±3 mV

Input bias current Comparator 1, 3, 5, 7, 9 (measured at 2.56 V) 40 100 nA

Comparator 0, 2, 4, 6, 8 (measured at 2.56 V) 150 300 nA

Input resistance 10 M

Power supply rejection ratio DC (0 – 10 KHz) 50 60 dB

Propagation delay 100 mV overdrive

HYS[1:0] = 00

(no hysteresis) 15 18 ns

100 mV overdrive

HYS[1:0] = 10

(with hysteresis) 25 30 ns

Hysteresis

(± refers to rising and falling

threshold shifts, respectively)

HYS[1:0] = 00 Typical (25°C) 0 0 ±5 mV

Across all corners (–40ºC to +100ºC) 0 ±5 mV

HYS[1:0] = 01 Typical (25°C) ±3 ± 16 ±30 mV

Across all corners (–40ºC to +100ºC) 0 ±36 mV

HYS[1:0] = 10 Typical (25°C) ±19 ± 31 ±48 mV

Across all corners (–40ºC to +100ºC) ±12 ±54 mV

HYS[1:0] = 11 Typical (25°C) ±80 ± 105 ±190 mV

Across all corners (–40ºC to +100ºC) ±80 ±194 mV

Comparator current

requirements

(per comparator)

VCC33A = 3.3 V (operational mode); COMP_EN = 1

VCC33A 150 165 µA

VCC33AP 140 165 µA

VCC15A 1 3 µA

G Microsemi

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-85

Analog Sigma-Delta Digital to Analog Converter (DAC)

Unless otherwise noted, sigma-delta DAC performance is specified at 25°C with nominal power supply

voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator

inputs updated at a 100 KHz rate, in voltage output mode with an external 160 pF capacitor to ground,

after trimming and digital [pre-]compensation.

Table 2-98 • Analog Sigma-Delta DAC

Specification Test Conditions Min. Typ. Max. Units

Resolution 8 24 Bits

Output range 0 to 2.56 V

Current output mode 0 to 256 µA

Output Impedance 6 10 12 K

Current output mode 10 M

Output voltage compliance Current output mode 0–3.0 V

–40ºC to +100ºC 0–2.7 0–3.4 V

Gain error Voltage output mode 0.3 ±2 %

A2F060: –40ºC to +100ºC 0.3 ±2 %

A2F200: –40ºC to +100ºC 1.2 ±5.3 %

A2F500: –40ºC to +100ºC 0.3 ±2 %

Current output mode 0.3 ±2 %

A2F060: –40ºC to +100ºC 0.3 ±2 %

A2F200: –40ºC to +100ºC 1.2 ±5.3 %

A2F500: –40ºC to +100ºC 0.3 ±2 %

Output referred offset DACBYTE0 = h’00 (8-bit) 0.25 ±1 mV

–40ºC to +100ºC 1 ±2.5 mV

Current output mode 0.3 ±1 µA

–40ºC to +100ºC 1 ±2.5 µA

Integral non-linearity RMS deviation from BFSL 0.1 0.3 % FS*

Differential non-linearity 0.05 0.4 % FS*

Analog settling time Refer to

Figure 2-44 on

page 2-86

µs

Power supply rejection ratio DC, full scale output 33 34 dB

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

O Microsemi Sigma DeHa DAC Settling Time Semmg Time (us)

SmartFusion DC and Switching Characteristics

2-86 Revision 14

Sigma-delta DAC power supply current

requirements (not including VAREFx)

Input = 0, EN = 1

(operational mode)

VCC33SDDx 30 35 µA

VCC15A 3 5 µA

Input = Half scale, EN = 1

(operational mode)

VCC33SDDx 160 165 µA

VCC15A 33 35 µA

Input = Full scale, EN = 1

(operational mode)

VCC33SDDx 280 285 µA

VCC15A 70 75 µA

Figure 2-44 • Sigma-Delta DAC Setting Time

Table 2-98 • Analog Sigma-Delta DAC (continued)

Specification Test Conditions Min. Typ. Max. Units

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

0 1 2 3 4 5 6 7 8 9 10 32 48 64 128 255

100

120

140

160

180

200

220

Settling Time (us)

Input Code

Sigma Delta DAC Settling Time

G Microsemi me

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-87

Voltage Regulator

Table 2-99 • Voltage Regulator

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VOUT Output voltage TJ = 25°C 1.425 1.5 1.575 V

VOS Output offset voltage TJ = 25°C 11 mV

ICC33A Operation current TJ = 25°C ILOAD = 1 mA 3.4 mA

ILOAD = 100 mA 11 mA

ILOAD = 0.5 A 21 mA

VOUT Load regulation TJ = 25°C ILOAD = 1 mA to 0.5 A 5.8 mV

VOUT Line regulation TJ = 25°C VCC33A = 2.97 V to 3.63 V

ILOAD = 1 mA

5.3 mV/V

VCC33A = 2.97 V to 3.63 V

ILOAD= 100 mA

5.3 mV/V

VCC33A = 2.97 V to 3.63 V

ILOAD = 500mA

5.3 mV/V

Dropout voltage1 T

J = 25°C ILOAD = 1 mA 0.63 V

ILOAD = 100 mA 0.84 V

ILOAD = 0.5 A 1.35 V

IPTBASE PTBase current TJ = 25°C ILOAD = 1 mA 48 µA

ILOAD = 100 mA 736 µA

ILOAD = 0.5 A 12 mA

Startup time2TJ = 25°C 200 µs

Notes:

1. Dropout voltage is defined as the minimum VCC33A voltage. The parameter is specified with respect to the output

voltage. The specification represents the minimum input-to-output differential voltage required to maintain regulation.

2. Assumes 10 µF.

icroseml. M G // Load Regulation $5 .53 5E woman; 55:0 5 maﬁa

SmartFusion DC and Switching Characteristics

2-88 Revision 14

Figure 2-45 • Typical Output Voltage

Figure 2-46 • Load Regulation

Load = 10 mA

Load = 100 mA

Load = 500 mA

-0.025

-0.02

-0.015

-0.01

-0.005

0.005

0.01

0.015

-40-20 0 20406080100

Offset Voltage (V)

Temperature (°C)

Typical Output Voltage

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

-40 -20 0 20 40 60 80 100

Change in Output Voltage with Load (mV)

Temperature (°C)

Load Regulation

G Microsemi “Argon/a)

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-89

Serial Peripheral Interface (SPI) Characteristics

This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output

characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to

SPI_x_CLK. For timing parameter definitions, refer to Figure 2-47 on page 2-90.

Table 2-100 • SPI Characteristics

Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Speed Grade

Symbol Description and Condition A2F060 A2F200 A2F500 Unit

sp1 SPI_x_CLK minimum period

SPI_x_CLK = PCLK/2 20 NA 20 ns

SPI_x_CLK = PCLK/4 40 40 40 ns

SPI_x_CLK = PCLK/8 80 80 80 ns

SPI_x_CLK = PCLK/16 0.16 0.16 0.16 µs

SPI_x_CLK = PCLK/32 0.32 0.32 0.32 µs

SPI_x_CLK = PCLK/64 0.64 0.64 0.64 µs

SPI_x_CLK = PCLK/128 1.28 1.28 1.28 µs

SPI_x_CLK = PCLK/256 2.56 2.56 2.56 µs

sp2 SPI_x_CLK minimum pulse width high

SPI_x_CLK = PCLK/2 10 NA 10 ns

SPI_x_CLK = PCLK/4 20 20 20 ns

SPI_x_CLK = PCLK/8 40 40 40 ns

SPI_x_CLK = PCLK/16 0.08 0.08 0.08 µs

SPI_x_CLK = PCLK/32 0.16 0.16 0.16 µs

SPI_x_CLK = PCLK/64 0.32 0.32 0.32 µs

SPI_x_CLK = PCLK/128 0.64 0.64 0.64 µs

SPI_x_CLK = PCLK/256 1.28 1.28 1.28 us

sp3 SPI_x_CLK minimum pulse width low

SPI_x_CLK = PCLK/2 10 NA 10 ns

SPI_x_CLK = PCLK/4 20 20 20 ns

SPI_x_CLK = PCLK/8 40 40 40 ns

SPI_x_CLK = PCLK/16 0.08 0.08 0.08 µs

SPI_x_CLK = PCLK/32 0.16 0.16 0.16 µs

SPI_x_CLK = PCLK/64 0.32 0.32 0.32 µs

SPI_x_CLK = PCLK/128 0.64 0.64 0.64 µs

SPI_x_CLK = PCLK/256 1.28 1.28 1.28 µs

sp4 SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%) 14.7 4.7 4.7 ns

sp5 SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%) 13.4 3.4 3.4 ns

Notes:

1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,

use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/index.php?option=com_microsemi&Itemid=489&lang=en&view=salescontact.

2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion

Microcontroller Subsystem User’s Guide.

O Microsemi I setup lime 2 2 S ‘ s s I 5P5 D ‘ . 10v. 3 E I 5P8 ‘1. v". i A

SmartFusion DC and Switching Characteristics

2-90 Revision 14

sp6 Data from master (SPI_x_DO) setup time 2(SPI_x_CLK_period/2) – 4.0 ns

sp7 Data from master (SPI_x_DO) hold time 2(SPI_x_CLK_period/2) – 4.0 ns

sp8 SPI_x_DI setup time 210.4 (load of 20 pF)

11.2 (load of 35 pF)

sp9 SPI_x_DI hold time 22.5 ns

Figure 2-47 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)

Table 2-100 • SPI Characteristics

Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Speed Grade (continued)

Symbol Description and Condition A2F060 A2F200 A2F500 Unit

Notes:

1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,

use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/index.php?option=com_microsemi&Itemid=489&lang=en&view=salescontact.

2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion

Microcontroller Subsystem User’s Guide.

SPI_x_CLK

SPO = 0

SPI_x_DO

SP6 SP7

50%50%

MSB

50% 50% 50%

SP2

SP1

90%

10% 10%

SP4 SP5

SP8 SP9

50%

50% MSB

SPI_x_DI

10%

90%

SP5

90%

10%

SP4

90%

10%10%

SP4SP5

90%

SPI_x_SS

SPI_x_CLK

SPO = 1

SP3

G Microsemi a START semp «me 3 a a

SmartFusion Customizable System-on-Chip (cSoC)

Revision 14 2-91

Inter-Integrated Circuit (I2C) Characteristics

This section describes the DC and switching of the IC interface. Unless otherwise noted, all output

characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer to Figure 2-

48 on page 2-92.

Table 2-101 • I2C Characteristics

Commercial Case Conditions: TJ= 85ºC, VDD = 1.425 V, –1 Speed Grade

Parameter Definition Condition Value Unit

VIL Minimum input low voltage – SeeTable 2-36 on

page 2-30

–

Maximum input low voltage – See Tab l e 2- 36 –

VIH Minimum input high voltage – See Ta b le 2 - 3 6 –

Maximum input high voltage – See Ta b l e 2- 3 6 –

VOL Maximum output voltage low IOL =8mA See Ta b l e 2 -3 6 –

IIL Input current high – See Ta b le 2 -3 6 –

IIH Input current low – See Tab l e 2- 36 –

Vhyst Hysteresis of Schmitt trigger

inputs

– See Table 2-33 on

page 2-29

TFALL Fall time 2VIHmin to VILMax, Cload = 400 pF 15.0 ns

VIHmin to VILMax, Cload = 100 pF 4.0 ns

TRISE Rise time 2VILMax to VIHmin, Cload = 400pF 19.5 ns

VILMax to VIHmin, Cload = 100pF 5.2 ns

Cin Pin capacitance VIN = 0, f = 1.0 MHz 8.0 pF

Rpull-up Output buffer maximum pull-

down Resistance 1

–50

Rpull-down Output buffer maximum pull-up

Resistance 1

– 150 

Dmax Maximum data rate Fast mode 400 Kbps

tLOW Low period of I2C_x_SCL 3– 1 pclk cycles

tHIGH High period of I2C_x_SCL 3– 1 pclk cycles

tHD;STA START hold time 3– 1 pclk cycles

tSU;STA START setup time 3– 1 pclk cycles

tHD;DAT DATA hold time 3– 1 pclk cycles

tSU;DAT DATA setup time 3– 1 pclk cycles

Notes:

1. These maximum values are provided for information only. Minimum output buffer resistance values depend on

VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output

buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at

http://www.microsemi.com/index.php?option=com_microsemi&Itemid=489&lang=en&view=salescontact.

2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the SoC Products Group website at

http://www.microsemi.com/index.php?option=com_microsemi&Itemid=489&lang=en&view=salescontact.

3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I2C) Peripherals section in the SmartFusion

Microcontroller Subsystem User’s Guide.

O Microsemi

SmartFusion DC and Switching Characteristics

2-92 Revision 14

tSU;STO STOP setup time 3– 1 pclk cycles

tFILT Maximum spike width filtered – 50 ns

Figure 2-48 • I2C Timing Parameter Definition